CN113569513B - On-chip multidimensional logic gate design method based on waveguide mode - Google Patents

Abstract

The invention discloses a method for designing multi-dimensional logic gates on a chip based on a waveguide mode. The method uses a reverse design method to set a structure area into an m×n structure matrix. According to the sequence number of the array, there are a nm×a nm pixel points at the position of the structure matrix, and the pixel points are assigned different initial values. Then, the FDTD algorithm and the initial value assigned to each pixel of the m×n structure matrix are used to calculate the proportion of each mode in the output port of different input modes, and the corresponding position in the structure matrix is found according to the sequence number in the structure matrix array for transformation operation. If the new FOM value after the operation is greater than the previous FOM value, the structural change is retained, and the FOM is updated to the FOM of the new structure. Otherwise, vice versa; if the FOM does not change, the local optimal solution is obtained. The invention continuously changes the refractive index distribution of the device area, and finally obtains the local optimal solution or the global optimal solution, which greatly improves the accuracy of the structure and improves the performance of the silicon-based sub-wavelength structure.

Description

A design method for on-chip multidimensional logic gates based on waveguide modes

Technical Field

The invention relates to the field of micro-nano optoelectronics and quantum information technology, and in particular to an on-chip multi-dimensional logic gate design method based on a waveguide mode.

Background technique

Quantum computation is a new computing method with super parallel computing capabilities based on the basic principles of quantum mechanics. If binary "0" and "1" are used to represent information, the classical bit that processes information in a classical computer can only be in "0" or "1" at a specific moment, and a single operation of N bits can only operate on 1 number out of ^2N numbers. However, the quantum bit (qubit) in a quantum computer can be in any superposition state (α|0>+β|1>) of |0> and |1>. A single operation of N qubits can simultaneously realize parallel operations on 2N numbers. This superposition characteristic gives quantum computers a clear advantage over classical computers when dealing with certain specific problems such as code cracking and data search.

The processor of a general-purpose quantum computer is composed of quantum logic gates. Quantum logic gates complete the controlled evolution of quantum bits through unitary transformations in quantum mechanics and are the basis for realizing quantum computing.

Among many quantum systems, photon quantum systems have been in a leading position in the development of quantum information for decades due to their natural advantages. Photons are flying quantum bits, and their ultra-fast propagation speed is very conducive to being used as a carrier for information transmission. During the transmission process, the photon quantum state is very immune to environmental noise and can still maintain its coherence after a long transmission distance and time. At the same time, photons have many degrees of freedom that can be used for encoding, including the path, polarization, orbital angular momentum, frequency, time, etc. of the photons. At the same time, in integrated optical devices, waveguide modes can also be used to encode information. Among all quantum systems, the photon quantum system has the lowest hardware requirements and does not need to operate in a vacuum and low-temperature environment. This reduces the difficulty of controlling the quantum state and makes the photon system most conducive to principle demonstration and experimental verification.

There are two main research directions at present: one is linear optical quantum computing that manipulates photons in free space. It is simple to operate and has mature technology. At present, most quantum computing schemes are first verified in free-space optical systems, but they have poor scalability and stability and are very susceptible to environmental disturbances; the other is optical quantum computing based on integrated chips, in which optical waveguides are usually used to build complex photon circuits. Although the waveguide chip system is still in its infancy, it has good scalability, stability and high integration, so it has broad prospects. At the same time, high-dimensional quantum communication has many advantages as follows: 1) It has a larger information capacity; 2) It has a higher tolerance to noise; 3) It has enhanced robustness to quantum cloning; 4) It more significantly violates the local theory and Bell's inequality. Therefore, in recent years, high-dimensional quantum communication has attracted the keen attention of more and more researchers.

Sub-wavelength structure (SWS) is an array structure with a period much smaller than the material's equivalent wavelength, that is, the period Λ＜＜λ(2n _eff ), where λ is the vacuum wavelength and n _eff is the equivalent refractive index. Since its period is much smaller than the wavelength, there is only zero-order diffraction in the sub-wavelength structure, and the higher-order diffraction orders of light cannot propagate into the free space and can only be bound inside the structure. Therefore, it can be regarded as a layer of anisotropic medium as a whole. By etching a design pattern that changes according to the sub-wavelength scale on the surface of silicon on insulator (SOI) and filling it with other materials (such as air, silicon dioxide, etc.), a device with the target function can be realized.

Since the waveguide dielectric constant can be flexibly changed at an ultra-small scale, silicon-based subwavelength structures can efficiently control the light field and realize ultra-small, high-performance silicon-based photonic devices. In the past, when designing silicon-based photonic devices, we mainly relied on some physical models or effects with prior knowledge, and then used simple parameter adjustment or parameter scanning methods based on experience to find the best points of various geometric size parameters in these models that can match the required functions. This design process is "blind" to a certain extent. The design method of finding the model parameters of the device through parameter adjustment or parameter scanning belongs to "forward design". The device model designed in this way usually has a simpler structure and generally has a certain theoretical physical model, which can be analyzed by analytical methods. Through parameter scanning, we can manually pick out devices with target functions from a series of devices with different structural parameters.

However, this conventional design method considers very limited parameter dimensions, and it is impossible to predict whether it can achieve relatively good results. More importantly, some devices with special functions and size requirements cannot be designed using this method. Therefore, it is necessary to further improve the existing design scheme of silicon-based subwavelength structures.

Summary of the invention

In order to solve the above technical problems, the present invention provides a method for manufacturing a high-dimensional on-chip multi-dimensional logic gate based on a waveguide mode to improve the performance of an optical quantum logic gate.

To achieve the above object, the technical solution adopted by the present invention is as follows: a method for designing an on-chip multi-dimensional logic gate based on a waveguide mode, the method comprising the following steps:

A method for designing on-chip multi-dimensional logic gates based on waveguide modes, characterized in that the method comprises the following steps:

Step 1: Determine the size of the structure area and the initial value of the pixel point: Use the reverse design method to set the structure area into an m×n structure matrix. According to the sequence number of the array, there are a nm×a nm pixel points at the positions of the structure matrix. A circular hole with a diameter of d nm is set at the center of the pixel point position. The material of the circular hole is Si or SiO _2. Different initial values are assigned to the pixel points according to different materials.

Step 2: Calculate the proportion of each mode in the output port of different input modes using the FDTD algorithm and the initial value assigned to each pixel of the m×n structure matrix, where the input and output modes are TE _i , and use them to form the FOM for evaluating the structure. The FOM expression is as follows:

Where _ti1 is ^the transmittance of the target mode after inputting TE _i mode, _ti2 is ^the transmittance of other modes after inputting TE _i , α is the balance factor of loss and crosstalk, m is the number of modes, i = 0, 1, 2, …, m;

Step 3: Find the corresponding position in the structure matrix according to the serial number in the structure matrix array to perform the structure conversion operation:

Operation 1: If the material of the circular hole in the corresponding position is Si, the circular hole material is modified to SiO ₂ through the control program, and then the FOM is calculated to obtain a new FOM value;

Operation 2: If the material of the circular hole in the corresponding position is SiO ₂ , the circular hole material is modified to Si through the control program, and then the FOM is calculated to obtain a new FOM value;

Compare the new FOM value obtained by operation 1 or operation 2 with the FOM before the conversion. If the new FOM value is greater than the previous FOM value, the structure after the structural conversion operation is retained, and the FOM is updated to the FOM of the new structure. Otherwise, the original structure and its FOM value are retained.

Step 4: assign a set of randomly generated 1-mn natural number sequences to each pixel of the corresponding sequence of the structure matrix in turn, and compare and retain the FOM values with large FOM values and their corresponding structure matrices in the order of 1-mn from small to large, and obtain a round of optimized FOM and structure matrix;

Then the FOM and structure matrix of this round are used as the initial FOM and structure matrix of the next round of optimization, and the optimization is carried out in this way. If the FOM does not change after this round of optimization, the local optimal solution is obtained.

Preferably, the initial value of a pixel is set to 0 or 1.

Preferably, the value range of m and n in the m×n structure matrix is 10-50;

Preferably, the value range of a in the a nm×a nm pixel is 80 nm-220 nm.

Preferably, the diameter d of the circular hole ranges from 60 nm to 150 nm.

Preferably, the size of the structure region is 2.5-4.5 μm×1-2.5 μm.

Preferably, the etching depth h of the structure region is 150-250 nm.

Beneficial technical effects of the present invention: The present invention adopts a reverse design method, utilizes multiple waveguide modes in a multimode waveguide, continuously transforms the matrix structure, retains large FOM values and corresponding mechanisms, and ultimately obtains a local optimal or global optimal solution, thereby obtaining a design of a silicon-based sub-wavelength high-dimensional quantum logic gate device with a fine structure, greatly improving the performance of the optical quantum logic gate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a flow chart showing the steps of a method for designing an on-chip multi-dimensional logic gate based on a waveguide mode according to the present invention.

FIG. 2 is a schematic diagram of a three-dimensional X-gate structure according to an embodiment of the present invention.

FIG. 3 is a transmission spectrum of a three-dimensional X-input TE0 mode according to an embodiment of the present invention.

FIG. 4 is a transmission spectrum of a three-dimensional X-input TE1 mode according to an embodiment of the present invention.

FIG. 5 is a transmission spectrum of a three-dimensional X-input TE2 mode according to an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments, but the scope of protection claimed in the present invention is not limited to the following specific embodiments.

Another device design method different from forward design is "reverse design". Reverse design refers to the process of treating the device area as a "black box" and designing the refractive index distribution of the device area according to the target function we need.

According to the process characteristics of ordinary passive SOI devices, the refractive index of the device area usually shows two states: "etched" or "not etched". When the upper cladding of the SOI device is air, the etched part is composed of air, and the unetched part is composed of silicon.

The overall idea of reverse design is to set a figure of merit (FOM) according to the target function of the device, and find a device shape that can maximize the FOM through a reverse optimization algorithm. In addition, the shape of the device usually needs to meet certain constraints. Compared with traditional forward design, the reverse design method opens up a larger parameter space, and can obtain a very fine structure through optimization calculation, obtain a local optimal or global optimal solution, and make full use of existing high-precision manufacturing processes and high-performance computing capabilities.

This embodiment uses reverse design to realize the design of on-chip multi-dimensional logic gates based on waveguide modes. The specific scheme of this embodiment is as follows:

As shown in FIG1 , a method for designing an on-chip multi-dimensional logic gate based on a waveguide mode includes the following steps:

Step 1: Determine the size of the structure area and the initial value of the pixel point: Use the reverse design method to set the structure area into an m×n structure matrix, in which the value range of m and n is 12-50. According to the sequence number of the array, there are a nm×a nm pixels at the position of the structure matrix corresponding to the position of the array, and the value range of a is 100nm-200nm. There is a circular hole with a diameter of d nm in the center of the pixel point position, and the value range of d is 90nm-150nm. The material of the circular hole is Si or SiO _2. Different initial values are assigned to the pixels according to different materials, and the initial value of the pixels is set to 0 or 1. The assignment of the initial value of the structure is analogous to the asymmetric structure of the mode conversion device, which can accelerate the convergence of the iterative calculation.

Here, the size of the structure region is 2.5-4.5 μm×1-2.5 μm, and the etching depth h of the structure region is 150-250 nm.

Step 2: Use the FDTD algorithm (FDTD algorithm, full name time domain difference method, is a commonly used simulation method for photonic devices) to calculate the proportion of each mode in the output port of different input modes according to the initial value assigned to each circular hole position in the m×n structure matrix (the structures corresponding to different structure matrices have different proportions of each mode in the output port after different modes are input into their input ports). The proportion of each mode in the output port is calculated by the method of multiple integration, which is a method commonly used to analyze mode components when using the 3D-FDTD algorithm to simulate silicon-based photonic passive devices.

The input-output mode is TEi, and it is used to form the FOM for evaluating the structure. The FOM expression is as follows:

Where _ti1 is ^the transmittance of the target mode after inputting TE _i mode, _ti2 is ^the transmittance of other modes after inputting TE _i , α is the balance factor of loss and crosstalk, m is the number of modes, i = 0, 1, 2, …, m.

Taking TE0 mode input as an example, the target is converted to TE1 mode, so t ₀ ¹ is the transmittance of TE1 mode after TE0 mode is input, so t ₀ ² is the transmittance of TE0 or TE2 mode after TE0 mode is input; α is the balance factor of loss and crosstalk. When α tends to 0, a result with lower loss can be obtained. When α tends to 1, a result with lower crosstalk can be obtained.

Step 3: Find the corresponding position in the structure matrix according to the serial number in the structure matrix array to perform the structure conversion operation:

Operation 1: If the material of the circular hole in the corresponding position is Si, the circular hole material is modified to SiO ₂ through the control program, and then the FOM is recalculated to obtain a new FOM value;

Operation 2: If the material of the circular hole in the corresponding position is SiO ₂ , the circular hole material is modified to Si through the control program, and then the FOM is recalculated to obtain a new FOM value;

The purpose of converting different materials in operations 1 and 2 is to change the material of the circular hole in the pixel, that is, the refractive index in the circular hole, so as to successfully regulate the distribution of the refractive index in the device. The value of the pixel corresponding to the circular hole position will also change with the change of the material. The conversion of materials is to control the change of the structure matrix by writing a script, thereby changing the structure of the device.

Compare the new FOM value obtained by operation 1 or operation 2 with the FOM before the conversion. If the new FOM value is greater than the previous FOM value, the structural conversion operation is retained and the FOM is updated to the FOM of the new structure. Otherwise, the FOM remains unchanged and the original structure is retained.

Step 4: assign a set of randomly generated 1-mn natural number sequences to each pixel of the corresponding sequence of the structure matrix in turn, and compare and retain the larger FOM and corresponding structure matrix in the order of 1-mn from small to large, and obtain a round of optimized FOM and structure matrix;

Since each matrix element of the m×n structure matrix corresponds to a material (Si or SiO ₂ ), the total number of matrix elements is mn. If we want to use the structure matrix to get the structure we want, we need to complete 2mn comparisons to get it, but this is time-consuming and labor-intensive, and difficult to complete. Therefore, using step 4 can greatly save calculation time and improve efficiency.

Then use the FOM and structure matrix of this round as the initial FOM and structure matrix of the next round of optimization, and optimize in this way. If the FOM does not change after a round of optimization, the local optimal solution is obtained. The no change here refers to the FOM between two adjacent rounds. After a round of optimization, the FOM value has not changed, so the optimal value has been reached.

The above method can be applied to designing any multi-dimensional logic gate structure. The following is a three-dimensional X gate designed by using the method of this embodiment.

As shown in FIG. 2 , the size of the three-dimensional X-gate structure obtained in this embodiment is 3.6 μm×1.8 μm, and the etching depth h is 220 nm, wherein the size of the pixel is 150 nm×150 nm, and there is a circular hole with a diameter of 100 nm in the center of the pixel. At this time, the reverse design structure area corresponds to a 24×12 structure matrix.

When TE0 mode is input, TE1 mode is output; when TE1 mode is input, TE2 mode is output; when TE2 mode is input, TE0 mode is output. In this case, X-gate operation is realized.

Figures 3-5 are the transmission spectra of the input TE0 mode, TE1 mode and TE2 mode respectively. In the 1540nm-1560nm band, the loss of TE0 mode converted to TE1 mode is <1dB, and the crosstalk is <22dB; the loss of TE1 mode converted to TE2 mode is <1.13dB, and the crosstalk is <21.24dB; the loss of TE2 mode converted to TE0 mode is <0.73dB, and the crosstalk is <22.9dB.

By adopting the reverse design solution of the present invention, the refractive index distribution of the device area is continuously changed to finally obtain a local optimal or global optimal solution, thereby greatly improving the accuracy of the structure and the performance of the silicon-based subwavelength structure.

According to the disclosure and teaching of the above description, those skilled in the art to which the present invention belongs may also make changes and modifications to the above embodiments. Therefore, the present invention is not limited to the specific embodiments disclosed and described above, and some modifications and changes to the invention should also fall within the scope of protection of the claims of the present invention. In addition, although some specific terms are used in this specification, these terms are only for the convenience of description and do not constitute any limitation to the invention.

Claims (7)

1. An on-chip multidimensional logic gate design method based on a waveguide mode is characterized by comprising the following steps:

step 1: determining the size of a structural area and the initial value of a pixel point: the structural area is set to be an m multiplied by n structural matrix by adopting a reverse design method, a pixel point with a nm multiplied by a nm is arranged at the position corresponding to the structural matrix according to the serial number of the array, a round hole with a diameter of d nm is arranged at the center of the pixel point, and the round hole is made of Si or SiO ₂ Different initial values are given according to different pixel points of the material;

step 2: calculating the proportion of each mode in the output ports of different input modes by using FDTD algorithm and the initial value given by each pixel point of m multiplied by n structural matrix, wherein the input and output modes are TE _i And the FOM of this structure was evaluated using its constitution, the FOM expression is as follows:

wherein t is _i ¹ To input TE _i Transmittance of target mode after mode, t _i ² To input TE _i Transmittance of the latter other modes, alpha being the balance of loss and crosstalkFactor, m, is the number of modes, i=0, 1,2, …, m;

step 3: finding the corresponding position in the structure matrix according to the sequence number in the structure matrix array to perform structure conversion operation:

operation 1: if the material of the round hole in the corresponding position is Si, modifying the round hole material into SiO through a control program ₂ Then recalculate the FOM to obtain a new FOM value;

operation 2: if the material of the round hole in the corresponding position is SiO ₂ Modifying the round hole material into Si through a control program and then recalculating the FOM to obtain a new FOM value;

comparing the new FOM value obtained in the operation 1 or the operation 2 with the FOM before conversion, if the new FOM value is larger than the previous FOM value, reserving the structure conversion operation, and meanwhile, updating the FOM into the FOM with the new structure, otherwise, reserving the FOM with the original structure;

step 4: sequentially giving a group of randomly generated 1-mn natural number sequences to each pixel point of corresponding number sequences of the structural matrix, sequentially comparing and retaining FOM with large numerical value FOM in the comparison structure and the corresponding structural matrix according to the sequence from 1-mn to large, and obtaining a round of optimized FOM and structural matrix;

and then taking the FOM and the structural matrix of the round as the initial FOM and the structural matrix of the next round of optimization, and advancing the row optimization, wherein if the FOM is unchanged after the round of optimization, the local optimal solution is obtained.

2. The method of designing a multi-dimensional logic gate on a chip based on a waveguide mode according to claim 1, wherein an initial value of a pixel point is set to 0 or 1.

3. The method for designing a multi-dimensional logic gate on a chip based on a waveguide mode according to claim 1, wherein the m and n values in the m x n structural matrix range from 10 to 50.

4. The method of on-chip multi-dimensional logic gate design based on waveguide mode according to claim 1, wherein the value of a in the pixel of a nm x a nm is in the range of 80nm-220nm.

5. The method for designing the on-chip multidimensional logic gate based on the waveguide mode as recited in claim 1, wherein the diameter d of the round hole is in the range of 60nm-150nm.

6. A method of designing a multi-dimensional logic gate on a chip based on a waveguide mode as claimed in claim 1, wherein the size of the structural region is 2.5-4.5 μm x 1-2.5 μm.

7. The method for designing a multi-dimensional logic gate on a chip based on a waveguide mode according to claim 6, wherein the etching depth h of the structural region is 150-250nm.