CN113555503B - Preparation method of ion trap chip, ion trap chip and quantum computer - Google Patents
Preparation method of ion trap chip, ion trap chip and quantum computer Download PDFInfo
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- CN113555503B CN113555503B CN202111090075.XA CN202111090075A CN113555503B CN 113555503 B CN113555503 B CN 113555503B CN 202111090075 A CN202111090075 A CN 202111090075A CN 113555503 B CN113555503 B CN 113555503B
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- 150000002500 ions Chemical class 0.000 claims abstract description 45
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N99/00—Subject matter not provided for in other groups of this subclass
- H10N99/05—Devices based on quantum mechanical effects, e.g. quantum interference devices or metal single-electron transistors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J3/00—Details of electron-optical or ion-optical arrangements or of ion traps common to two or more basic types of discharge tubes or lamps
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Abstract
The invention discloses a preparation method of an ion trap chip, the ion trap chip and a quantum computer, wherein the preparation method comprises the following steps: providing a substrate; forming a laminated structure comprising a plurality of conductive layers and a plurality of dielectric layers on one side of a substrate; etching the laminated structure to form at least two first openings, and forming a sacrificial layer in the first openings; forming a first photoresist layer on one side of the laminated structure far away from the substrate and patterning; the patterned first photoresist layer comprises second openings, and the second openings expose the laminated structure to be etched between two adjacent first openings; etching the laminated structure to be etched between two adjacent first openings to form a third opening; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate; the sacrificial layer is removed to form an ion well region for trapping ions, so that the alignment of holes with different sizes in the laminated structure is accurate, the distribution of the electromagnetic field of the chip and the potential well of the trapped ions are ensured, and the working performance of the chip is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of quantum computing, in particular to a preparation method of an ion trap chip, the ion trap chip and a quantum computer.
Background
Quantum computing is one of important leading-edge technologies, and is an important path which continues to develop from the Moore's law approaching the physical limit, wherein an ion trap quantum computer uses trapped ions as qubits, and has the advantages of high fidelity and long coherence time.
An ion trap chip in an ion trap quantum computer has a function of trapping ions, wherein the position of a trap at the center of the chip relates to etching and alignment processes of multiple layers of conductive materials and insulating materials, but the alignment process in the prior art has the problem of counterpoint deviation when etching for multiple times to form openings with different sizes, so that the openings with different sizes have dislocation phenomenon in the direction along the depth of the openings, the position deviation of multiple layers of metal in holes formed by combining the openings with different sizes in the horizontal direction is caused, the distribution of an electromagnetic field of the chip is influenced, the potential well of the trapped ions is influenced, and the working performance of the ion trap chip is reduced.
Disclosure of Invention
The embodiment of the invention provides a preparation method of an ion trap chip, the ion trap chip and a quantum computer, which are used for ensuring the distribution of an electromagnetic field of the chip and trapping a potential well of ions and improving the working performance of the ion trap chip.
In a first aspect, an embodiment of the present invention provides a method for manufacturing an ion trap chip, including:
providing a substrate;
forming a laminated structure comprising a plurality of conductive layers and a plurality of dielectric layers on one side of a substrate; the conducting layers and the dielectric layers are alternately arranged;
etching the laminated structure to form at least two first openings;
forming a sacrificial layer in the first opening;
forming a first photoresist layer on one side of the laminated structure far away from the substrate, and patterning the first photoresist layer; the patterned first photoresist layer comprises a second opening, and the second opening exposes a laminated structure to be etched between two adjacent first openings;
etching the laminated structure to be etched between two adjacent first openings to form a third opening; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate;
and removing the sacrificial layer to form an ion well region trapping ions.
Optionally, the etching the stacked structure to form at least two first openings includes:
on the basis of a mask, etching the laminated structure in a dry etching or wet etching mode to form at least two first openings; the first opening exposes the substrate, and the mask comprises a photoresist mask, a metal mask or a laminated mask of metal and photoresist.
Optionally, the material of the sacrificial layer includes photoresist;
the forming a sacrificial layer in the first opening includes:
forming a second photoresist layer on one side of the laminated structure far away from the substrate and in the first opening in a blade coating or spin coating mode; wherein the second photoresist layer filled in the first opening forms the sacrificial layer.
Optionally, in the stacked structure, a dielectric layer is closest to the substrate, and a conductive layer is farthest from the substrate; before forming the first photoresist layer on the side of the laminated structure far away from the substrate, the method further comprises:
and removing the second photoresist layer on the surface of the conductive layer farthest from the substrate in the laminated structure by oxygen plasma.
Optionally, the length of the second opening is smaller than the distance between two adjacent first openings; the second opening exposes the part of the laminated structure between two adjacent first openings;
the etching is located between two adjacent first openings to form a third opening, and the third opening comprises:
alternately etching the conducting layer and the dielectric layer in a dry etching or wet etching mode to form a third opening; the third opening exposes a conductive layer in the stacked structure.
Optionally, the etching a stacked structure to be etched between two adjacent first openings to form a third opening, further includes:
and etching the dielectric layer exposed by the third opening in the laminated structure through mixed gas containing hydrofluoric acid or mixed solution containing hydrofluoric acid.
Optionally, the removing the sacrificial layer to form an ion well region trapping ions includes:
and removing the sacrificial layer through an organic solvent, so that the suspended conductive layer exposed by the third opening is stripped along with the removal of the sacrificial layer, and the ion well region is formed.
Optionally, a distance between the second opening and the first opening is smaller than the thickness of the dielectric layer.
Optionally, in the stacked structure, a dielectric layer is closest to the substrate, and a conductive layer is farthest from the substrate; the length of the second opening is larger than the distance between two adjacent first openings; the second opening exposes part of the first opening and the whole laminated structure between two adjacent first openings;
the etching is located between two adjacent first openings to form a third opening, and the third opening comprises:
and alternately etching the conducting layer and the dielectric layer by a dry etching method or a wet etching method, and etching the sacrificial layer exposed from the second opening in the first opening while alternately etching the conducting layer and the dielectric layer to form the third opening.
Optionally, the etching rates of the sacrificial layer are both less than or equal to the etching rates of the conductive layer and the dielectric layer.
In a second aspect, an embodiment of the present invention provides an ion trap chip, which is prepared by the method for preparing an ion trap chip according to any one of the first aspect, including:
a substrate and a laminated structure on one side of the substrate;
the laminated structure comprises a plurality of conducting layers and a plurality of dielectric layers, wherein the conducting layers and the dielectric layers are alternately arranged; the laminated structure further comprises at least two first openings, and a third opening located between two adjacent first openings; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate; and the adjacent two first openings and the third opening positioned between the adjacent two first openings are combined to form an ion well region for trapping ions.
In a third aspect, an embodiment of the present invention provides a quantum computer, including the ion trap chip of the second aspect.
The embodiment of the invention provides a preparation method of an ion trap chip, the ion trap chip and a quantum computer, wherein the preparation method comprises the following steps: providing a substrate; forming a laminated structure comprising a plurality of conductive layers and a plurality of dielectric layers on one side of a substrate; the conducting layers and the dielectric layers are alternately arranged; etching the laminated structure to form at least two first openings, and forming a sacrificial layer in the first openings; forming a first photoresist layer on one side of the laminated structure far away from the substrate, and patterning the first photoresist layer; the patterned first photoresist layer comprises second openings, and the second openings expose the laminated structure to be etched between two adjacent first openings; etching the laminated structure to be etched between two adjacent first openings to form a third opening; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate; and removing the sacrificial layer to form an ion well region trapping ions. According to the technical scheme provided by the embodiment of the invention, by designing the redundant structure, a sacrificial layer is formed in at least two first openings formed by etching the laminated structure, and then a photoresist pattern formed on the basis of a first photoresist layer is used as a mask to etch the laminated structure to be etched between two adjacent first openings to form a third opening; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate, so that after the sacrificial layer is removed, the first opening and the third opening are combined to form a large hole, and a part of the first opening, which is deeper than the third opening, forms a small hole; the side walls of the first openings are shared by the large holes and the small holes, so that the positions of the holes with different sizes in the laminated structure are accurate, namely, the position deviation of the multilayer metal in the holes formed by combining the openings with different sizes in the horizontal direction does not exist, the distribution of an electromagnetic field of the chip and the potential well trapping ions are ensured, and the working performance of the ion trap chip is improved.
Drawings
Fig. 1 is a flow chart of a method for manufacturing an ion trap chip provided in the prior art;
fig. 2-3 are cross-sectional views of the structure corresponding to step S1 in the method for manufacturing the ion trap chip of fig. 1;
fig. 4 is a cross-sectional view of a structure corresponding to step S2 in the method for manufacturing the ion trap chip of fig. 1;
fig. 5 is a cross-sectional view of the structure corresponding to step S3 in the method for manufacturing the ion trap chip of fig. 1;
fig. 6 is a cross-sectional view of the structure corresponding to step S4 in the method for manufacturing the ion trap chip of fig. 1;
fig. 7 is a cross-sectional view of the structure corresponding to step S5 in the method for manufacturing the ion trap chip of fig. 1;
fig. 8 is a flowchart of a method for manufacturing an ion trap chip according to an embodiment of the present invention;
fig. 9 is a cross-sectional view of the structure corresponding to step S120 in the method for manufacturing the ion trap chip of fig. 8;
fig. 10 is a cross-sectional view of the structure corresponding to step S130 in the method for manufacturing the ion trap chip of fig. 8;
fig. 11 is a cross-sectional view of the structure corresponding to step S140 in the method for manufacturing the ion trap chip of fig. 8;
fig. 12 is a cross-sectional view of the structure corresponding to step S150 in the method for manufacturing the ion trap chip of fig. 8;
fig. 13 is a cross-sectional view of the structure corresponding to step S160 in the method for manufacturing the ion trap chip of fig. 8;
fig. 14 is a cross-sectional view of the structure corresponding to step S170 in the method for manufacturing the ion trap chip of fig. 8;
fig. 15 is a flow chart of another method for manufacturing an ion trap chip according to an embodiment of the present invention;
fig. 16 is a cross-sectional view of the structure corresponding to step S270 in the method for manufacturing an ion trap chip of fig. 15;
fig. 17 is a flow chart of another method for manufacturing an ion trap chip according to an embodiment of the present invention;
fig. 18 is a cross-sectional view of the structure corresponding to step S350 in the method for manufacturing the ion trap chip of fig. 17.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As background art, quantum computing is one of the important leading technologies, and is an important path that continues to develop following moore's law, which is approaching the physical limit. Currently, the feature size of semiconductor transistors is gradually shrinking to the physical limit, and new calculation modes must be explored to meet the demand for higher performance. Quantum computing is a novel interdisciplinary of quantum mechanics and computer science, with the ability to surpass classical computers in the resolution of specific problems. Quantum computation is characterized by its computational power raised to a power of 2 with increasing number of quantum bits that can be supportednAnd (4) increasing. Quantum computing is expected to be commercially available in artificial intelligence applications such as new drugs, password cracking, searching and the like. At present, the quantum computer has various routes, including superconduction, an ion trap, semiconductor quantum dots, quantum optics and the like, wherein the ion trap quantum computer uses trapped ions as qubits, and has the advantages of high fidelity and long coherence time. Thanks to mature semiconductor processes, ion trap miniaturization (chipization) can meet the demand for manipulating more ion qubits. The ion trap chip has the function of trapping ions, is made of conductive materials and insulating materials, provides an electromagnetic field capable of controlling ions, and directly influences the distribution of the electromagnetic field of the chip by the structure of the chip, wherein the position of the trap in the center of the chip is particularly critical. The location of the well in the center of the chip involves etching and alignment processes of multiple layers of conductive and insulating materials.
Fig. 1 is a flowchart of a method for manufacturing an ion trap chip provided in the prior art, and referring to fig. 1, the method includes: and S1, etching the small hole. Fig. 2 to 3 are cross-sectional views of structures corresponding to step S1 in the method for manufacturing an ion trap chip provided in fig. 1, and referring to fig. 2 to 3, a stacked structure composed of a dielectric layer 110 and a conductive layer 120 is formed on a substrate 100, the stacked structure shown in fig. 2 to 3 only exemplarily shows one dielectric layer 110 and one conductive layer 120, and at least two small holes 130 are etched in the stacked structure. And S2, filling the small holes. Fig. 4 is a cross-sectional view of the structure corresponding to step S2 in the manufacturing method of the ion trap chip shown in fig. 1, and referring to fig. 4, the small hole 130 is filled with the upper filler 140. S3, forming a top layer. Fig. 5 is a cross-sectional view of the structure corresponding to step S3 in the method for manufacturing the ion trap chip shown in fig. 1, and referring to fig. 5, after the small hole 130 is filled with the filler 140, the stacked structure continues to grow. And S4, etching large holes. Fig. 6 is a cross-sectional view of the structure corresponding to step S4 in the method for manufacturing the ion trap chip shown in fig. 1, and referring to fig. 6, a large hole 150 is etched in the stacked structure, and the large hole 150 is etched until the filler 140 leaks out. And S5, removing the small hole filling to form an overlay structure. Fig. 7 is a cross-sectional view of a structure corresponding to step S5 in the method for manufacturing the ion trap chip of fig. 1, and referring to fig. 7, the filling material 140 in the small hole 130 is removed, so as to form an overlay structure. However, in the prior art, there is a problem of misalignment (for example, there is a positional deviation at the position 160 in fig. 7) in multiple times of alignment, which causes a positional deviation of the conductive layer 120 in the same hole in the horizontal direction, which affects the distribution of the electromagnetic field of the chip, thereby affecting the potential well of the trapped ions, and reducing the operating performance of the ion trap chip.
In view of this, an embodiment of the present invention provides a method for manufacturing an ion trap chip, and fig. 8 is a flowchart of the method for manufacturing an ion trap chip according to the embodiment of the present invention, and with reference to fig. 8, the method includes:
and S110, providing a substrate.
In particular, the substrate has a mechanical support and a heat sink for the chip, and the material of the substrate may include silicon.
S120, forming a laminated structure comprising a plurality of conducting layers and a plurality of dielectric layers on one side of the substrate; the conducting layers and the dielectric layers are alternately arranged.
Specifically, fig. 9 is a cross-sectional view of a structure corresponding to step S120 in the manufacturing method of the ion trap chip provided in fig. 8, and referring to fig. 9, a stacked structure including a plurality of conductive layers 22 and a plurality of dielectric layers 21 is formed on one side of the substrate 10, and the conductive layers 22 and the dielectric layers 21 are alternately arranged. In the stacked structure, the number of layers of the dielectric layer 21 and the conductive layer 22 is the same, the dielectric layer 21 is closest to the substrate 10, and the conductive layer 22 is farthest from the substrate 10, that is, the dielectric layer 21 and the conductive layer 22 are arranged in pairs. The material of the conductive layer 22 may include gold, silver, aluminum, copper, titanium, or tantalum, or may be a combination of any two metals. The materials of the different conductive layers 22 may be the same or different. The material of the dielectric layer 21 may include an insulating material such as silicon oxide or silicon nitride.
S130, etching the laminated structure to form at least two first openings.
Specifically, fig. 10 is a cross-sectional view of the structure corresponding to step S130 in the preparation method of the ion trap chip provided in fig. 8, and referring to fig. 10, the step of etching the stacked structure to form at least two first openings 30 may be performed by etching the stacked structure in a dry etching or wet etching manner based on a mask. The mask comprises a photoresist mask or a metal and photoresist combined mask. For example, when using photoresist as a mask for etching a laminated structure, it is necessary to prepare a photoresist mask on the side of the laminated structure away from the substrate 10. And coating a photoresist layer on the surface of one side of the laminated structure far away from the substrate 10, exposing and developing the photoresist layer, and patterning the photoresist layer to form a pattern to be etched. In the process of transferring the photoresist pattern obtained by photoetching to the laminated structure, the conductive layer 22 and the dielectric layer 21 are alternately etched by dry etching or wet etching by utilizing the covering and protecting functions of the photoresist mask to form at least two first openings 30. Two pairs of metal layers and oxide layers may be etched, or three or four pairs of layers may be etched. The embodiment of the invention etches to the substrate 10, so that the formed first opening 30 exposes the substrate 10, and then the surface photoresist or the hard mask is removed. Illustratively, the shape of the etch hole (first opening 30) may be circular, square, or other irregular shape; the first opening 30 has a depth of 1 micron to 20 microns; the pitch of adjacent first openings 30 ranges from 10 microns to 500 microns.
Wet etching is a chemical reaction process that utilizes chemical reagents to chemically react with the material to be etched to generate soluble or volatile substances. In the wet etching process, the etchant and the laminated structure exposed by the mask are subjected to chemical reaction, and then reaction products are removed. Different materials correspond to different etchants, for example, the material of the dielectric layer 21 is silicon oxide, and 49% of the etchant can be added into waterThe solution of HF acts as an etchant to etch the dielectric layer 21. If the material of the conductive layer 22 is Al, H can be added in a ratio of 16:2:1:13PO4、H2O、HNO3And CH3And etching the mixed solution consisting of COOH. Dry etching is a technique of etching using plasma. Plasma is referred to as a fourth form of matter and may be considered as a partially or fully discharged gas. The dry etching can realize anisotropic etching, ensure that the first opening 30 is etched along the direction vertical to the substrate 10, and has the advantage of better size control. Therefore, dry etching is preferable to wet etching.
S140, forming a sacrificial layer in the first opening.
Specifically, fig. 11 is a cross-sectional view of the structure corresponding to step S140 in the method for manufacturing the ion trap chip shown in fig. 8, and referring to fig. 11, after the stacked structure is etched to form at least two first openings 30, a sacrificial layer 40 is formed in the first openings 30. The material of the sacrificial layer 40 may include photoresist. Forming the sacrificial layer 40 in the first opening 30, forming a second photoresist layer on the side of the stacked structure away from the substrate 10 and in the first opening 30 by a doctor blade method or a spin coating method; wherein the second photoresist layer filled in the first opening 30 forms a sacrificial layer 40. After blade coating or spin coating is finished, curing the second photoresist layer; the second photoresist layer may be either a positive or negative photoresist. Preferably, the second photoresist layer is formed by means of doctor blading on the side of the laminated structure remote from the substrate 10 and in the first opening 30. Due to the deep depth of the first opening 30, it is possible to reach the depth of the entire laminated structure, and the first opening 30 can be efficiently and sufficiently filled by the doctor blade. The material of the sacrificial layer 40 may also include a material that is easily removed, such as amorphous silicon.
S150, forming a first photoresist layer on one side of the laminated structure far away from the substrate, and patterning the first photoresist layer; the patterned first photoresist layer comprises a second opening, and the second opening exposes the laminated structure to be etched between two adjacent first openings.
Specifically, after the sacrificial layer 40 is formed in the first opening 30, a step of removing the second photoresist layer on the metal surface of the side of the stacked structure away from the substrate 10 by oxygen plasma may be further included. So that a flat plane is provided for the formation of the first photoresist layer 50 prior to the process step of forming the first photoresist layer 50 on the side of the laminated structure remote from the substrate 10. Fig. 12 is a cross-sectional view of the structure corresponding to step S150 in the method for manufacturing an ion trap chip provided in fig. 8, and referring to fig. 12, after removing the second photoresist layer on the surface of the stacked structure away from the substrate 10 by oxygen plasma, a first photoresist layer 50 is formed on the side of the stacked structure away from the substrate 10, and the first photoresist layer 50 is patterned; the patterned first photoresist layer 50 includes a second opening 51, and the second opening 51 exposes the stacked structure to be etched between two adjacent first openings 30.
S160, etching the laminated structure to be etched between the two adjacent first openings to form a third opening; the depth of the first opening is greater than the depth of the third opening in a direction perpendicular to the substrate.
Specifically, fig. 13 is a cross-sectional view of the structure corresponding to step S160 in the method for manufacturing the ion trap chip provided in fig. 8, and referring to fig. 13, the patterned first photoresist layer 50 includes a second opening 51, and the second opening 51 exposes the stacked structure to be etched between two adjacent first openings 30. And etching the laminated structure to be etched between two adjacent first openings 30 and exposed by the second openings 51 by using the patterned first photoresist layer 50 as a mask, thereby forming third openings 60. The third opening 60 is formed to a depth smaller than that of the first opening 30 in a direction perpendicular to the substrate 10.
And S170, removing the sacrificial layer to form an ion well region trapping ions.
Specifically, fig. 14 is a cross-sectional view of the structure corresponding to step S170 in the method for manufacturing an ion trap chip provided in fig. 8, and referring to fig. 14, the sacrificial layer 40 located in the first opening 30 is removed to form an ion well region trapping ions. If the material of the sacrificial layer 40 includes photoresist, the first photoresist layer 50 on the stacked structure can be stripped off while the sacrificial layer 40 is stripped off by an organic solvent, so that the preparation efficiency of the ion trap chip can be improved. Because the depth of the first opening 30 is greater than that of the third opening 60, after the sacrificial layer 40 is removed, a large hole is formed in the part of the first opening 30 and the third opening 60 which are combined together with the same depth, and a small hole is formed in the part of the first opening 30 which is deeper than the third opening 60; the side walls of the first openings 30 are shared by the large holes and the small holes, so that the positions of the holes with different sizes in the laminated structure are accurate, namely, the position deviation of the multilayer metal in the holes formed by combining the openings with different sizes in the horizontal direction does not exist, the distribution of an electromagnetic field of the chip and the potential well trapping ions are ensured, and the working performance of the ion trap chip is improved.
The preparation method of the ion trap chip provided by the embodiment of the invention comprises the following steps: providing a substrate; forming a laminated structure comprising a plurality of conductive layers and a plurality of dielectric layers on one side of a substrate; the conducting layers and the dielectric layers are alternately arranged; etching the laminated structure to form at least two first openings, and forming a sacrificial layer in the first openings; forming a first photoresist layer on one side of the laminated structure far away from the substrate, and patterning the first photoresist layer; the patterned first photoresist layer comprises second openings, and the second openings expose the laminated structure to be etched between two adjacent first openings; etching the laminated structure to be etched between two adjacent first openings to form a third opening; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate; and removing the sacrificial layer to form an ion well region trapping ions. According to the technical scheme provided by the embodiment of the invention, by designing the redundant structure, a sacrificial layer is formed in at least two first openings formed by etching the laminated structure, and then a photoresist pattern formed on the basis of a first photoresist layer is used as a mask to etch the laminated structure to be etched between two adjacent first openings to form a third opening; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate, so that after the sacrificial layer is removed, the first opening and the third opening are combined to form a large hole, and a part of the first opening, which is deeper than the third opening, forms a small hole; the side walls of the first openings are shared by the large holes and the small holes, so that the positions of the holes with different sizes in the laminated structure are accurate, namely, the position deviation of the multilayer metal in the holes formed by combining the openings with different sizes in the horizontal direction does not exist, the distribution of an electromagnetic field of the chip and the potential well trapping ions are ensured, and the working performance of the ion trap chip is improved.
Fig. 15 is a flowchart of another method for manufacturing an ion trap chip according to an embodiment of the present invention, and referring to fig. 15, the method includes:
s210, providing a substrate.
S220, forming a laminated structure comprising a plurality of conductive layers and a plurality of dielectric layers on one side of the substrate; the conducting layers and the dielectric layers are alternately arranged.
S230, etching the laminated structure to form at least two first openings.
S240, forming a sacrificial layer in the first opening.
S250, forming a first photoresist layer on one side of the laminated structure far away from the substrate, and patterning the first photoresist layer; the first patterned photoresist layer comprises second openings, and the length of each second opening is smaller than the distance between every two adjacent first openings; the second opening exposes a portion of the laminated structure between two adjacent first openings.
Specifically, referring to fig. 12, all the stacked structure between two adjacent first openings 30 finally needs to be etched, and the length of the second opening 51 is smaller than the distance L between two adjacent first openings 30, so that the second opening 51 exposes a part of the stacked structure between two adjacent first openings 30, and the size of the stacked structure exposed by the second opening 51 is smaller than the size of the stacked structure needing to be etched.
S260, alternately etching the conducting layer and the dielectric layer in a dry etching or wet etching mode to form a third opening; the third opening exposes a conductive layer in the stacked structure, and the depth of the first opening is greater than that of the third opening along a direction perpendicular to the substrate.
Specifically, referring to fig. 13, since all the stacked structures between two adjacent first openings 30 need to be etched finally, the length of the second opening 51 is smaller than the distance L between two adjacent first openings 30, so that the size of the stacked structure exposed by the second opening 51 is smaller than the size of the stacked structure needing to be etched. Accordingly, the third opening 60 is formed by etching the laminated structure exposed by the second opening 51 based on the patterned first photoresist layer 50, so that the laminated structure has an unetched remaining portion between the formed third opening 60 and the first opening 30. The conductive layer 22 and the dielectric layer 21 may be etched alternately in a dry etching or wet etching manner to form a third opening 60; the third opening 60 exposes a conductive layer 22 in the stacked structure, that is, the last exposed layer in the etching process of the third opening 60 is a metal layer in the stacked structure.
And S270, removing the dielectric layer exposed by the third opening in the laminated structure.
Specifically, fig. 16 is a cross-sectional view of the structure corresponding to step S270 in the method for manufacturing an ion trap chip provided in fig. 15, and referring to fig. 16, the dielectric layer 21 exposed by the third opening 60 in the laminated structure may be etched by using a mixed gas containing hydrofluoric acid or a mixed solution containing hydrofluoric acid. After removing the dielectric layer 21 exposed by the third opening 60 in the stacked structure, the sacrificial layer 40 in the first opening 30 may be exposed from the sidewall of the third opening 60. Optionally, the distance d between the second opening 51 and the first opening 30 is smaller than the thickness of the dielectric layer 21 (refer to fig. 12), for example, the thickness of the dielectric layer is 6 micrometers; the spacing d between the second opening 51 and the first opening 30 is 3 micrometers. So that the width of the unetched remaining portion between the formed third opening 60 and the first opening 30 is short. In the process of etching the dielectric layer 21 layer by layer, the suspended conductive layer 22 is prevented from being bent due to too long, which affects the etching of the next dielectric layer 21, and further prevents the residual dielectric layer 21 from being arranged at the contact part of the dielectric layer 21 and the sacrificial layer 40, which affects the removal of the sacrificial layer 40 by organic solvent in the next process.
And S280, removing the sacrificial layer through an organic solvent, so that the suspended conductive layer exposed by the third opening is stripped along with the removal of the sacrificial layer, and forming an ion well region.
Specifically, referring to fig. 14 and 16, the sacrificial layer 40 in the first opening 30 and the first photoresist layer 50 on the side of the stacked structure away from the substrate 10 are stripped using an organic solvent. After the dielectric layer 21 exposed by the third opening 60 in the stacked structure is removed, the sacrificial layer 40 in the first opening 30 is exposed from the sidewall of the third opening 60, so that an organic solvent can contact with the exposed sacrificial layer 40 from the sidewall of the third opening 60 for reaction, thereby increasing the removal speed of removing the sacrificial layer 40. In addition, in the process of removing the sacrificial layer 40 by using the organic solvent, the suspended conductive layer 22 exposed by the third opening 60 can be stripped off along with the stripping of the sacrificial layer 40, so as to form a required overlay pattern. In step S270, in order to prevent the metal layer from being damaged by the etching process, the scheme of removing the conductive layer 22 exposed by the third opening 60 in the stacked structure and the scheme of removing the dielectric layer 21 exposed by the third opening 60 in the stacked structure are preferably adopted to remove the dielectric layer 21 exposed by the third opening 60 in the stacked structure.
In the technical scheme provided by the embodiment of the invention, the length of the second opening included in the first photoresist layer is smaller than the distance between two adjacent first openings; the second opening exposes the part of the laminated structure between two adjacent first openings, the laminated structure exposed by the second opening is etched to form a third opening based on the patterned first photoresist layer, so that an unetched reserved part is formed between the formed third opening and the first opening of the laminated structure, then the dielectric layer of the reserved part is removed by using HF atmosphere etching or wet etching, the sacrificial layer is exposed, so that an organic solvent can contact with the exposed sacrificial layer from the side wall of the third opening to react, and the removal speed of the sacrificial layer is accelerated. In addition, in the process of removing the sacrificial layer by the organic solvent, the suspended conductive layer exposed by the third opening can be stripped off along with the stripping of the sacrificial layer, and a required overlay pattern is formed. After the sacrificial layer is removed, the first opening and the third opening are combined to form a large hole, and a part of the first opening, which is deeper than the third opening, forms a small hole; the side walls of the first openings are shared by the large holes and the small holes, so that the positions of the holes with different sizes in the laminated structure are accurate, namely, the position deviation of the multilayer metal in the holes formed by combining the openings with different sizes in the horizontal direction does not exist, the distribution of an electromagnetic field of the chip and the potential well trapping ions are ensured, and the working performance of the ion trap chip is improved.
Fig. 17 is a flowchart of a method for manufacturing an ion trap chip according to another embodiment of the present invention, and referring to fig. 17, the method includes:
s310, providing a substrate.
S320, forming a laminated structure comprising a plurality of conducting layers and a plurality of dielectric layers on one side of the substrate; the conducting layers and the dielectric layers are alternately arranged.
S330, etching the laminated structure to form at least two first openings.
S340, forming a sacrificial layer in the first opening.
S350, forming a first photoresist layer on one side of the laminated structure far away from the substrate, and patterning the first photoresist layer; the first patterned photoresist layer comprises second openings, and the length of each second opening is greater than the distance between every two adjacent first openings; the second opening exposes a part of the first opening and the entire laminated structure between two adjacent first openings.
Specifically, fig. 18 is a cross-sectional view of the structure corresponding to step S350 in the manufacturing method of the ion trap chip provided in fig. 17, and referring to fig. 18, all the stacked structures between two adjacent first openings 30 are required to be etched finally, and the length of the second opening 51 is greater than the distance between two adjacent first openings 30, so that the second opening 51 can expose all the stacked structures between two adjacent first openings 30 and also expose a part of the sacrificial layer 40 in the first opening 30.
S360, alternately etching the conducting layer and the dielectric layer in a dry etching or wet etching mode, and etching the sacrificial layer exposed from the second opening in the first opening while alternately etching the conducting layer and the dielectric layer to form a third opening.
Specifically, since all the stacked structures between two adjacent first openings are required to be etched finally, the length of the second opening is greater than the distance between two adjacent first openings, so that the second opening can expose all the stacked structures between two adjacent first openings, and in addition, part of the sacrificial layer in the first opening is exposed. Therefore, when the laminated structure exposed by the second opening is etched based on the patterned first photoresist layer, a part of the sacrificial layer in the first opening is also etched, and the etched laminated structure and a part of the sacrificial layer form a third opening. I.e. the third opening has an overlap region with the first opening (see region 70 in fig. 18). And similarly, taking a conductive layer in the laminated structure as the film layer exposed after the etching of the third opening is stopped. Optionally, the etching rates of the sacrificial layer and the dielectric layer are both less than or equal to the etching rates of the conductive layer and the dielectric layer, so that the etching depth of the sacrificial layer is less than or equal to the etching depth of the etching laminated structure, damage to the substrate covered by the sacrificial layer in the overlapping region is avoided when the etching depth of the sacrificial layer is greater than the etching depth of the etching laminated structure, and the bottom of the overlapping region is protected from being etched.
And S370, removing the sacrificial layer through an organic solvent to form an ion well region.
Specifically, the remaining sacrificial layer and the first photoresist layer on the side, far away from the substrate, of the laminated structure are removed through an organic solvent, a large hole is formed in a part with the same depth formed by combining the first opening and the third opening, and a small hole is formed in a part, deeper than the third opening, of the first opening; the side walls of the first openings are shared by the large holes and the small holes, so that the positions of the holes with different sizes in the laminated structure are accurate, namely, the position deviation of the multilayer metal in the holes formed by combining the openings with different sizes in the horizontal direction does not exist, the distribution of an electromagnetic field of the chip and the potential well trapping ions are ensured, and the working performance of the ion trap chip is improved.
In the technical scheme provided by the embodiment of the invention, the length of the second opening included in the first photoresist layer is greater than the distance between two adjacent first openings; and the sacrificial layer in the first opening of the exposed part of the second opening and the whole laminated structure between two adjacent first openings are etched simultaneously on the basis of the patterned first photoresist layer to form a third opening. The etching rate of the sacrificial layer is less than or equal to the etching rate of the conducting layer and the dielectric layer, so that the etching depth of the sacrificial layer is less than or equal to the etching depth of the etching laminated structure, the damage to the substrate covered by the sacrificial layer of the etching part is avoided when the etching depth of the sacrificial layer is greater than the etching depth of the etching laminated structure, and the bottom of the overlapped area is protected from being etched. After removing the rest of the sacrificial layer, combining the first opening and the third opening to form a large hole, and forming a small hole in the part of the first opening deeper than the third opening; the side walls of the first openings are shared by the large holes and the small holes, so that the positions of the holes with different sizes in the laminated structure are accurate, namely, the position deviation of the multilayer metal in the holes formed by combining the openings with different sizes in the horizontal direction does not exist, the distribution of an electromagnetic field of the chip and the potential well trapping ions are ensured, and the working performance of the ion trap chip is improved.
An embodiment of the present invention further provides an ion trap chip, which is prepared by the method for preparing an ion trap chip according to any of the above embodiments, and referring to fig. 14, the ion trap chip includes:
a substrate 10 and a laminated structure on one side of the substrate 10;
the laminated structure comprises a plurality of conductive layers 120 and a plurality of dielectric layers 110, wherein the conductive layers 120 and the dielectric layers 110 are alternately arranged; the laminated structure further comprises at least two first openings and a third opening positioned between two adjacent first openings; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate; and the adjacent two first openings and the third opening positioned between the adjacent two first openings are combined to form an ion well region for trapping ions.
According to the technical scheme provided by the embodiment of the invention, by designing the redundant structure, a sacrificial layer is formed in at least two first openings formed by etching the laminated structure, and then a photoresist pattern formed on the basis of a first photoresist layer is used as a mask to etch the laminated structure to be etched between two adjacent first openings to form a third opening; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate, so that after the sacrificial layer is removed, the first opening and the third opening are combined to form a large hole, and a part of the first opening, which is deeper than the third opening, forms a small hole; the side walls of the first openings are shared by the large holes and the small holes, so that the positions of the holes with different sizes in the laminated structure are accurate, namely, the position deviation of the multilayer metal in the holes formed by combining the openings with different sizes in the horizontal direction does not exist, the distribution of an electromagnetic field of the chip and the potential well trapping ions are ensured, and the working performance of the ion trap chip is improved.
The embodiment of the invention also provides a quantum computer, which comprises the ion trap chip and has the same technical effects, and the details are not repeated.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (12)
1. A method for preparing an ion trap chip is characterized by comprising the following steps:
providing a substrate;
forming a laminated structure comprising a plurality of conductive layers and a plurality of dielectric layers on one side of a substrate; the conducting layers and the dielectric layers are alternately arranged;
etching the laminated structure to form at least two first openings;
forming a sacrificial layer in the first opening;
forming a first photoresist layer on one side of the laminated structure far away from the substrate, and patterning the first photoresist layer; the patterned first photoresist layer comprises a second opening, and the second opening exposes a laminated structure to be etched between two adjacent first openings;
etching the laminated structure to be etched between two adjacent first openings to form a third opening; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate;
removing the sacrificial layer to form an ion well region trapping ions; and the part of the first opening and the third opening, which is combined with the same depth, forms a large hole, the part of the first opening, which is deeper than the third opening, forms a small hole, and the large hole and the small hole share the side wall of the first opening.
2. The method of claim 1, wherein the etching the stacked structure to form the at least two first openings comprises:
on the basis of a mask, etching the laminated structure in a dry etching or wet etching mode to form at least two first openings; the first opening exposes the substrate, and the mask comprises a photoresist mask, a metal mask or a laminated mask of metal and photoresist.
3. The method of manufacturing an ion trap chip according to claim 1, wherein the material of the sacrificial layer comprises a photoresist;
the forming a sacrificial layer in the first opening includes:
forming a second photoresist layer on one side of the laminated structure far away from the substrate and in the first opening in a blade coating or spin coating mode; wherein the second photoresist layer filled in the first opening forms the sacrificial layer.
4. The method of claim 3, wherein in the stacked structure, the dielectric layer is closest to the substrate and the conductive layer is farthest from the substrate; before forming the first photoresist layer on the side of the laminated structure far away from the substrate, the method further comprises:
and removing the second photoresist layer on the surface of the conductive layer farthest from the substrate in the laminated structure by oxygen plasma.
5. The method for manufacturing the ion trap chip according to claim 1, wherein the length of the second opening is smaller than the distance between two adjacent first openings; the second opening exposes the part of the laminated structure between two adjacent first openings;
the etching is located between two adjacent first openings to form a third opening, and the third opening comprises:
alternately etching the conducting layer and the dielectric layer in a dry etching or wet etching mode to form a third opening; the third opening exposes a conductive layer in the stacked structure.
6. The method for preparing the ion trap chip according to claim 5, wherein the etching is performed on the laminated structure to be etched between two adjacent first openings, and after the third opening is formed, the method further comprises:
and etching the dielectric layer exposed by the third opening in the laminated structure through mixed gas containing hydrofluoric acid or mixed solution containing hydrofluoric acid.
7. The method of claim 6, wherein the removing the sacrificial layer to form an ion well region trapping ions comprises:
and removing the sacrificial layer through an organic solvent, so that the suspended conductive layer exposed by the third opening is stripped along with the removal of the sacrificial layer, and the ion well region is formed.
8. The method of claim 5, wherein a distance between the second opening and the first opening is less than a thickness of the dielectric layer.
9. The method of claim 1, wherein in the stacked structure, a dielectric layer is closest to the substrate and a conductive layer is farthest from the substrate; the length of the second opening is larger than the distance between two adjacent first openings; the second opening exposes part of the first opening and the whole laminated structure between two adjacent first openings;
the etching is located between two adjacent first openings to form a third opening, and the third opening comprises:
and alternately etching the conducting layer and the dielectric layer by a dry etching method or a wet etching method, and etching the sacrificial layer exposed from the second opening in the first opening while alternately etching the conducting layer and the dielectric layer to form the third opening.
10. The method of claim 9, wherein the etching rates of the sacrificial layer are less than or equal to the etching rates of the conductive layer and the dielectric layer.
11. An ion trap chip produced by the method for producing an ion trap chip according to any one of claims 1 to 10, comprising:
a substrate and a laminated structure on one side of the substrate;
the laminated structure comprises a plurality of conducting layers and a plurality of dielectric layers, wherein the conducting layers and the dielectric layers are alternately arranged; the laminated structure further comprises at least two first openings, and a third opening located between two adjacent first openings; the depth of the first opening is larger than that of the third opening along the direction vertical to the substrate; the two adjacent first openings and the third opening positioned between the two adjacent first openings are combined to form an ion well region for trapping ions; and the part of the first opening and the third opening, which is combined with the same depth, forms a large hole, the part of the first opening, which is deeper than the third opening, forms a small hole, and the large hole and the small hole share the side wall of the first opening.
12. A quantum computer comprising the ion trap chip of claim 11.
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