CN113539972B - Memory and manufacturing method thereof - Google Patents
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- CN113539972B CN113539972B CN202110790979.7A CN202110790979A CN113539972B CN 113539972 B CN113539972 B CN 113539972B CN 202110790979 A CN202110790979 A CN 202110790979A CN 113539972 B CN113539972 B CN 113539972B
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- 230000015654 memory Effects 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 184
- 230000002093 peripheral effect Effects 0.000 claims abstract description 155
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 67
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 40
- 230000000903 blocking effect Effects 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 354
- 238000010586 diagram Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
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- 150000002500 ions Chemical class 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
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Abstract
The application provides a memory and a manufacturing method thereof, relates to the technical field of memory, and aims to solve the technical problem of high substrate loss in the memory. The manufacturing method of the memory comprises the following steps: providing a substrate, wherein the substrate comprises a core area and a peripheral area; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the plurality of active regions; forming a plurality of word line trenches in each of the active region and the peripheral region; forming a conductive layer in each word line groove, wherein the distance from the upper surface of the conductive layer of the peripheral region to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer of the core region to the upper surface of the substrate; forming a polysilicon layer on the conductive layer; removing part of the polysilicon layer of the core region and all the polysilicon layer of the peripheral region; a barrier layer is formed in the word line trench of the core region and in the word line trench of the peripheral region. By reducing the depth of the contact hole exposing the conductive layer in the peripheral region, substrate loss caused by forming the contact hole is avoided, thereby improving the performance of devices such as transistors in the memory.
Description
Technical Field
The application relates to the technical field of storage equipment, in particular to a memory and a manufacturing method thereof.
Background
With the development of memory device technology, dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is increasingly used in various electronic devices with higher density and faster read/write speed. The dynamic random access memory is generally provided with a substrate and a dielectric layer arranged on the substrate, wherein a core area and a peripheral area arranged around the core area are arranged on the substrate, and embedded word lines are arranged in the core area and the peripheral area.
In the related art, the structure of the word line generally includes a conductive layer, a polysilicon layer and a blocking layer which are sequentially stacked from bottom to top, in general, a contact hole exposing the conductive layer in the word line is formed on a dielectric layer corresponding to the word line in the peripheral region, a plurality of contact holes exposing the substrate are also formed on a dielectric layer corresponding to the substrate in the peripheral region, and the contact holes exposing the conductive layer of the word line in the peripheral region are communicated with the top of a portion of the contact holes corresponding to the substrate, so that the word line is electrically conducted with other devices through the contact structure, and in order to save a processing process, each contact hole is generally integrally formed.
However, as the density of circuit patterns increases, the word line structure in the memory makes the depth of each contact hole larger, resulting in a large loss of the substrate when each contact hole is formed, thereby affecting the performance of devices such as transistors in the memory.
Disclosure of Invention
In view of the above, embodiments of the present application provide a memory and a method for manufacturing the same, which are used to reduce the loss of a substrate, thereby improving the performance of devices such as transistors in the memory.
In order to achieve the above object, the embodiment of the present application provides the following technical solutions:
in a first aspect, an embodiment of the present application provides a method for manufacturing a memory, including the steps of:
providing a substrate, wherein the substrate comprises a core area and a peripheral area positioned outside the core area; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the plurality of active regions; forming a plurality of word line trenches in each of the active region and the peripheral region; forming a conductive layer in each word line trench, wherein the distance from the upper surface of the conductive layer of the peripheral region to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer of the core region to the upper surface of the substrate; forming a polysilicon layer on the substrate and the conductive layer; removing part of the polysilicon layer of the core region and all of the polysilicon layer of the peripheral region, and reserving part of the polysilicon layer which is positioned in the core region and in the word line groove; and forming a blocking layer in the word line groove of the core region and the word line groove of the peripheral region, wherein the conducting layer, the polycrystalline silicon layer and the blocking layer in the core region form a first word line, and the conducting layer and the blocking layer in the peripheral region form a second word line.
The method for manufacturing the memory, as described above, includes the steps of forming a conductive layer in each of the word line trenches, wherein a distance from an upper surface of the conductive layer in the peripheral region to an upper surface of the substrate is smaller than a distance from an upper surface of the conductive layer in the core region to the upper surface of the substrate, and the steps include: forming the conductive layer with a preset thickness in each word line groove of the core area and each word line groove of the peripheral area; forming a first mask layer in the peripheral region, wherein the first mask layer covers the conductive layer of the peripheral region and the substrate of the peripheral region; removing part of the conductive layer which is positioned in the core region and the word line groove by taking the first mask layer as a mask, and reserving part of the conductive layer which is positioned in the core region and the word line groove; and removing the first mask layer.
The method for manufacturing the memory comprises the steps of forming the conductive layer with the preset thickness in each groove, wherein the steps comprise: forming a conductive layer in the substrate and each word line trench; and removing the substrate and part of the conductive layer in each word line groove to form the conductive layer with the preset thickness in each word line groove.
The method for manufacturing the memory as described above, the step of forming a plurality of word line trenches in each of the active region and the peripheral region includes: forming a second mask layer on the substrate; patterning the second mask layer to expose areas corresponding to the first word lines of the active region and the second word lines of the peripheral region; and removing part of the substrate by taking the patterned second mask layer as a mask, so as to form the word line groove in the active region and the word line groove in the peripheral region.
In the method for manufacturing the memory, the upper surface of the conductive layer in the formed second word line is higher than the upper surface of the part of the polysilicon layer which is finally remained in the formed first word line.
In the above method for manufacturing a memory, removing the portion of the conductive layer in the word line trench and the core region, and reserving the portion of the conductive layer in the word line trench and the core region specifically includes: and etching the part of the conductive layer which is positioned in the word line groove in the core area by adopting a wet method.
The method for manufacturing the memory, as described above, forms a first mask layer in the peripheral region, where the step of covering the conductive layer of the peripheral region and the substrate of the peripheral region by the first mask layer includes: and forming a photoresist layer on the conductive layer of the peripheral region and the substrate of the peripheral region, wherein the photoresist layer covers the conductive layer of the peripheral region and the substrate of the peripheral region, and the photoresist layer forms the first mask layer.
The manufacturing method of the memory comprises the steps that the conductive layer is a titanium nitride layer; the barrier layer is a silicon nitride layer.
In the method for manufacturing a memory as described above, after the step of forming the first word line by the conductive layer, the polysilicon layer and the barrier layer in the core region and forming the second word line by the conductive layer and the barrier layer in the peripheral region, the method for manufacturing a memory further includes: a first insulating layer is formed on the substrate.
The method for manufacturing the memory, after forming the first insulating layer on the substrate, further comprises: forming a third mask layer on the first insulating layer; patterning the third mask layer to form a mask pattern; removing the first insulating layer by taking the third mask layer as a mask to form a gate trench exposing the substrate, wherein the gate trench corresponds to a region for forming a transistor structure; forming a gate structure in the gate trench; a second insulating layer is formed over the substrate and the gate structure.
The method for manufacturing the memory, after the step of forming the second insulating layer on the substrate and the gate structure, further comprises: and forming a first contact hole exposing a part of the conductive layer in the second word line in the peripheral region, and simultaneously forming a second contact hole exposing a part of the substrate in the peripheral region.
In the method for manufacturing the memory, the step of forming the first contact hole exposing a portion of the conductive layer in the second word line in the peripheral region and simultaneously forming the second contact hole exposing a portion of the substrate in the peripheral region includes: forming a fourth mask layer on the second insulating layer; patterning the fourth mask layer to form a mask pattern; sequentially removing the second insulating layer, the first insulating layer and the blocking layer in the region corresponding to the second word line by taking the fourth mask layer as a mask, so as to form the first contact hole exposing part of the conductive layer; and synchronously and sequentially removing part of the second insulating layer and the first insulating layer in the corresponding area of the substrate to form a second contact hole exposing part of the substrate.
The manufacturing method of the memory comprises the steps that the first insulating layer is an oxide layer; the second insulating layer is a silicon nitride layer.
In a second aspect, embodiments of the present application also provide a memory, including: a substrate comprising a core region and a peripheral region located outside the core region; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the plurality of active regions; the first word line is positioned in the active area, is arranged in the substrate corresponding to the active area and comprises a conductive layer, a polycrystalline silicon layer and a blocking layer which are sequentially stacked; the second word line is positioned in the peripheral area and arranged in the substrate corresponding to the peripheral area, and comprises a conducting layer and a blocking layer which are arranged in a stacked mode; wherein a distance from an upper surface of the conductive layer of the peripheral region to an upper surface of the substrate is smaller than a distance from an upper surface of the conductive layer of the core region to an upper surface of the substrate.
Compared with the related art, the memory and the manufacturing method thereof provided by the embodiment of the application have at least the following advantages:
the manufacturing method of the memory provided by the embodiment of the application comprises the following steps: providing a substrate, wherein the substrate comprises a core area and a peripheral area positioned outside the core area; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the plurality of active regions; forming a plurality of word line trenches in each of the active region and the peripheral region; forming a conductive layer in each word line groove, wherein the distance from the upper surface of the conductive layer of the peripheral region to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer of the core region to the upper surface of the substrate; forming a polysilicon layer on the substrate and the conductive layer; removing part of the polysilicon layer of the core area and all the polysilicon layer of the peripheral area, and reserving part of the polysilicon layer which is positioned in the core area and in the word line groove; and forming a blocking layer in the word line groove of the core area and the word line groove of the peripheral area, wherein the conducting layer, the polysilicon layer and the blocking layer which are positioned in the core area form a first word line, and the conducting layer and the blocking layer which are positioned in the peripheral area form a second word line. By removing all the polysilicon layers on the conductive layer in the peripheral region, the distance from the upper surface of the conductive layer in the formed second word line to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer in the core region to the upper surface of the substrate, so that the depth of the contact hole for exposing the conductive layer in the second word line can be reduced, the depth of other contact holes in the substrate in the peripheral region, which are integrally formed with the contact hole, can be reduced, the loss of the substrate caused when each contact hole is formed can be avoided, and further, the performance of devices such as transistors in a memory can be improved.
In addition to the technical problems, technical features constituting the technical solutions, and beneficial effects caused by the technical features of the technical solutions described above, the memory and the manufacturing method thereof provided by the embodiments of the present application solve other technical problems, other technical features included in the technical solutions, and beneficial effects caused by the technical features, which are described in detail in the detailed description of the embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a related art memory;
FIG. 2 is a flowchart of a method for fabricating a memory according to an embodiment of the present application;
FIG. 3 is a flowchart of forming conductive layers in a first word line and a second word line, respectively, in a method for manufacturing a memory according to an embodiment of the present application;
Fig. 4 is a flowchart of forming a conductive layer with a predetermined thickness in a method for manufacturing a memory according to an embodiment of the present application;
FIG. 5 is a flowchart illustrating a method for forming word line trenches in a memory device according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a structure of a conductive layer formed in a memory according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of forming a conductive layer with a predetermined thickness in a memory according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a structure of a portion of a conductive layer in a memory according to an embodiment of the present application, in which a first mask layer is formed in a peripheral region and a core region is etched;
fig. 9 is a schematic structural diagram of forming a polysilicon layer in a memory according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a memory according to an embodiment of the present application, in which all polysilicon layers in a peripheral region and a portion of polysilicon layers in a core region are removed;
FIG. 11 is a schematic diagram of a structure of a memory device for forming a barrier layer according to an embodiment of the present application;
fig. 12 is a schematic diagram of a memory according to an embodiment of the present application.
Reference numerals:
10-a substrate; 11-a first word line;
12-a second word line; 13-a conductive layer;
14-a polysilicon layer; 15-a barrier layer;
16-a first mask layer; 17-a second mask layer;
18-a first insulating layer; a 19-gate structure;
191-a dielectric layer; 192-work function adjustment layer;
193-a first gate semiconductor layer; 194-a second gate semiconductor layer;
195-a first electrically conductive layer; 196-a second electrically conductive layer;
197-insulating capping layer; 20-a second insulating layer;
21-a first contact hole; 22-a second contact hole;
23-shallow trench isolation regions; 24-active region.
Detailed Description
Current dynamic random access memories include a plurality of repeating memory cells, each memory cell including a capacitor and a transistor having a gate connected to a Word Line (WL), a drain connected to a bit line, and a source connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line or writing the data information into the capacitor through the bit line for storage. The Word line is connected to a Word line driver (Word line driver) through a contact structure (Local interconnect contact, abbreviated as LICON) located at a peripheral region of the memory cell, thereby facilitating the Word line driver to input a voltage signal into the Word line. As shown in fig. 1, the memory is generally provided with a substrate, on which a core region (e.g., a in fig. 1) and a peripheral region (e.g., B in fig. 1) are disposed around the core region, the core region includes an active region arranged in an array and a shallow trench isolation region isolating a plurality of active regions, wherein the substrate includes a P-type substrate and an N-type doped layer on a surface of the P-type substrate, a plurality of word line trenches are formed in each of the active region and the peripheral region, the word line trenches formed in the active region divide the N-type doped layer into a source region and a drain region, and word lines are formed in each of the word line trenches, wherein the word lines include a conductive layer, and a polysilicon layer and a barrier layer disposed on the conductive layer.
The word line of the peripheral area needs to be connected with the word line driver through the contact structure, in order to reduce the resistance value, the blocking layer and the polysilicon layer of the corresponding parts of the word line and the contact structure in the peripheral area need to be removed, and a contact hole is formed to expose the conductive layer of the word line of the peripheral area, so that the contact structure is in contact connection with the conductive layer in the word line; in addition, if the word line of the peripheral region includes a polysilicon layer, the etching selectivity of the polysilicon layer and the substrate is relatively poor, when the polysilicon layer is etched, the substrate loss is relatively serious, and the more serious the substrate loss is, the more serious the N-type doped layer located on the surface layer of the substrate is lost, so that the source region and the drain region of the N-type doped layer on the substrate are difficult to form, and further the performance of devices such as transistors in the memory is affected.
In order to reduce the loss of the substrate and improve the performance of devices such as transistors in a memory, the embodiment of the application provides a manufacturing method of the memory, which is characterized in that the distance from the upper surface of the conductive layer in the formed second word line to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer in the core region to the upper surface of the substrate by removing all the polysilicon layers on the conductive layer in the peripheral region, so that the depth of a contact hole for exposing the conductive layer in the second word line can be reduced, the depth of other contact holes integrally formed with the contact hole in the substrate in the peripheral region can be reduced, the loss of the substrate caused when each contact hole is formed can be avoided, and the performance of the devices such as transistors in the memory can be improved.
In order to make the above objects, features and advantages of the embodiments of the present application more comprehensible, the technical solutions of the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Example 1
Referring to fig. 2, an embodiment of the present application provides a method for manufacturing a memory, including the following steps:
step S101, providing a substrate, wherein the substrate comprises a core area and a peripheral area positioned in the core area; the core region includes a plurality of active regions and shallow trench isolation regions isolating the plurality of active regions.
Referring to fig. 6 to 12, the substrate 10 provided in the embodiment of the present application includes a core region and a peripheral region located outside the core region, the core region is located at a shown in fig. 6 to 12, the peripheral region is located at B shown in fig. 6 to 12, a capacitor is subsequently formed above the core region of the substrate 10, and a peripheral circuit, for example, a transistor or the like is subsequently formed above the peripheral region of the substrate 10.
The core region includes a plurality of active regions 24 and shallow trench isolation regions 23 isolating the plurality of active regions 24, a shallow trench isolation structure may be disposed in the shallow trench isolation regions 23, the plurality of active regions 24 may be arranged in an array, the plurality of active regions 24 may be arranged in a region forming a core region, and a region of the core region, where the active regions 24 are not formed, may form a peripheral region, so that the peripheral region surrounds the periphery of the core region.
The substrate 10 may be a crystalline semiconductor material, such as a silicon (Si) substrate 10, and the substrate 10 may also be a germanium (Ge) substrate, a silicon-on-insulator (Silicon on Insulator, abbreviated as SOI), a silicon germanium (SiGe) substrate, a silicon carbide (SiC) or a gallium nitride (GaN) substrate, etc., which are not particularly limited in this regard.
Step S102: a plurality of word line trenches are formed in each of the active region and the peripheral region.
Referring to fig. 6, a plurality of word line trenches are formed in each of the active region 24 and the peripheral region.
Referring to fig. 5, the step of forming a plurality of word line trenches in each of the active region and the peripheral region includes the steps of:
step S1021: a second mask layer is formed over the substrate.
Step S1022: the second mask layer is patterned so that the patterned second mask layer exposes the first word line of the active region and the region corresponding to the second word line of the peripheral region.
Step S1023: and removing part of the substrate by taking the patterned second mask layer as a mask to form a word line groove in the active region and a word line groove in the peripheral region.
Referring to fig. 6, in particular, a semiconductor layer may be disposed in the substrate 10, for example, the substrate 10 includes a P-type substrate 10 and an N-type doped layer, and in particular, an ion doping process is performed on the surface of the P-type substrate 10, and an N-type doped layer having a certain thickness is formed on the surface of the P-type substrate 10. After forming an N-type doped layer with a certain thickness on the surface of the P-type substrate 10, forming a second mask layer 17 on the substrate 10, patterning the second mask layer 17 so that the patterned second mask layer 17 exposes the region corresponding to the word line of the active region 24 and the word line of the peripheral region, etching the second mask layer 17 and the substrate 10 by taking the second mask layer 17 as a mask according to the pattern of the second mask layer 17 to form a word line groove located in the active region 24 and a word line groove located in the peripheral region, wherein the word line groove formed in each active region 24 divides the N-type doped layer into a source region and a drain region.
The second mask layer 17 may be an oxide layer, which is not particularly limited in this embodiment.
Step S103: and forming a conductive layer in each word line groove, wherein the distance from the upper surface of the conductive layer of the peripheral region to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer of the core region to the upper surface of the substrate.
Referring to fig. 8, the conductive layer 13 is formed in each word line trench, and the distance from the upper surface of the conductive layer 13 in the peripheral region to the upper surface of the substrate 10 is smaller than the distance from the upper surface of the conductive layer 13 in the core region to the upper surface of the substrate 10, so that the distance from the upper surface of the conductive layer 13 in the peripheral region to the upper surface of the substrate 10 is relatively small, and thus, the loss of the substrate due to the exposure of the conductive layer in the peripheral region can be reduced in the subsequent process.
The conductive layer 13 may be a conductive layer 13 made of a conductive material such as titanium nitride, which is not particularly limited in this embodiment.
Referring to fig. 3, the step of forming a conductive layer in each word line trench, wherein the distance from the upper surface of the conductive layer in the peripheral region to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer in the core region to the upper surface of the substrate specifically includes:
step S1031: and forming conductive layers with preset thickness in each word line groove of the core area and each word line groove of the peripheral area.
Referring to fig. 7, a conductive layer 13 is formed in the substrate 10 and each word line trench; the substrate 10 and portions of the conductive layer 13 in each of the word line trenches are removed to form a predetermined thickness of the conductive layer 13 in each of the word line trenches.
Referring to fig. 4, the step of forming a conductive layer with a predetermined thickness in each word line trench of the core region and in the word line trench of the peripheral region specifically includes:
step S10311: a conductive layer is formed in the substrate and each of the word line trenches.
Referring to fig. 6, a conductive layer 13 is formed in the substrate 10 and each word line trench.
Step S10311: and removing the substrate and part of the conductive layer in each word line groove to form a conductive layer with a preset thickness in each word line groove.
Referring to fig. 7, the substrate 10 and a portion of the conductive layer 13 in each word line trench may be removed by etching or the like to form a conductive layer 13 of a predetermined thickness in each word line trench, wherein the etching may be dry etching or wet etching, for example, laser etching, chemical liquid etching, or the like, which is not particularly limited in this embodiment.
Step S1032: and forming a first mask layer in the peripheral region, wherein the first mask layer covers the conductive layer of the peripheral region and the substrate of the peripheral region.
Referring to fig. 8, a first mask layer 16 is formed in the peripheral region, the first mask layer 16 covers the conductive layer 13 in the peripheral region and the second mask layer 17 in the peripheral region, wherein the first mask layer 16 is a photoresist layer formed on the conductive layer 13 in the peripheral region and the second mask layer 17 in the peripheral region, and the photoresist layer covers the conductive layer 13 in the peripheral region and the second mask layer 17 in the peripheral region.
Step S1032: and removing part of the conductive layer which is positioned in the core region and positioned in the word line groove by taking the first mask layer as a mask, and reserving part of the conductive layer which is positioned in the core region and positioned in the word line groove.
Step S1032: and removing the first mask layer.
With continued reference to fig. 8, using the first mask layer 16 as a mask, a portion of the conductive layer 13 in the wordline trench and in the core region is removed, and a portion of the conductive layer 13 in the wordline trench and in the core region is left; the first mask layer 16 is removed to form the conductive layer 13 located in each word line trench in the peripheral region and the conductive layer 13 located in each word line trench in the core region, and the distance from the upper surface of the conductive layer 13 in the peripheral region to the upper surface of the substrate 10 is smaller than the distance from the upper surface of the conductive layer 13 in the core region to the upper surface of the substrate 10.
In addition, the part of the conductive layer 13 in the word line trench and the core region is removed, and the part of the conductive layer 13 in the word line trench and the core region is reserved, and specifically, the conductive layer 13 may be etched by wet etching or the like, for example, chemical liquid etching or the like, such as phosphoric acid wet etching the conductive layer 13, which is not particularly limited in this embodiment.
Step S104: a polysilicon layer is formed over the substrate and the conductive layer.
Referring to fig. 9, a polysilicon layer 14 is formed on the substrate 10 and the conductive layer 13. Wherein the polysilicon layer 14 may be formed on the conductive layer 13 by spin coating or chemical deposition.
Step S105: and removing part of the polysilicon layer of the core region and all the polysilicon layer of the peripheral region, and reserving part of the polysilicon layer which is positioned in the core region and in the word line groove.
Referring to fig. 10, a portion of the polysilicon layer 14 in the core region and the entire polysilicon layer 14 in the peripheral region are removed, leaving a portion of the polysilicon layer 14 in the core region and in the wordline trenches.
It should be noted that the polysilicon layer 14 and the barrier layer 15 in the core region mainly prevent the conductive layer 13 in the core region from being electrically connected with the source region and the drain region, so as to cause leakage current, and the polysilicon layer 13 in the first word line 11 is provided with polysilicon, so that the resistance value of the word line can be reduced while avoiding leakage current.
Illustratively, a wet etching manner such as chemical liquid etching is used to remove a portion of the polysilicon layer 14 in the core region and all of the polysilicon layer 14 in the peripheral region, and a portion of the polysilicon layer 14 in the core region and in the wordline trench remains.
Wet etching can provide different etch selectivity compared to dry etching, thereby reducing the loss to the substrate 10 when etching the polysilicon layer 14.
It is understood that the etching selectivity refers to the relative etching rate of one material to another material under the same etching conditions, i.e., the ratio of the etching rate of the etched material to the etching rate of the other material.
Step S106: and forming a blocking layer in the word line groove of the core area and the word line groove of the peripheral area, wherein the conducting layer, the polysilicon layer and the blocking layer which are positioned in the core area form a first word line, and the conducting layer and the blocking layer which are positioned in the peripheral area form a second word line.
Referring to fig. 11, a barrier layer 15 is formed in the word line trench of the core region and the word line trench of the peripheral region, a conductive layer 13, a polysilicon layer 14 and the barrier layer 15 located in the core region form a first word line 11, and the conductive layer 13 and the barrier layer 15 located in the peripheral region form a second word line 12. By providing the first word line 11 and the second word line 12 differently in structure, it is possible to reduce the loss of the substrate 10 in addition to the case of avoiding occurrence of leakage current between the conductive layer 13 in the first word line 11 and the source and drain regions, thereby improving the performance of devices such as transistors in a memory.
The barrier layer 15 may be a barrier layer 15 made of an insulating material such as silicon nitride or silicon oxynitride.
The embodiment of the application provides a manufacturing method of a memory, which is characterized in that by removing all polysilicon layers 14 on a conductive layer 13 in a peripheral area, the distance from the upper surface of the conductive layer 13 in a formed second word line 12 to the upper surface of a substrate 10 is smaller than the distance from the upper surface of the conductive layer 13 in a core area to the upper surface of the substrate 10, so that the depth of a contact hole for exposing the conductive layer 13 in the second word line 12 can be reduced, the depth of other contact holes integrally formed with the contact hole in the substrate 10 in the peripheral area can be reduced, and the loss of the substrate 10 caused by forming each contact hole can be avoided; in addition, the second word line 12 formed in the peripheral region has no polysilicon layer 14, so that the loss of the substrate 10 can be reduced, and the problem that the source region and the drain region cannot be formed in the N-type doped layer of the substrate 10 due to the loss of the surface layer of the substrate 10 can be avoided, so that the performance of devices such as transistors in a memory can be improved.
Further, in order to avoid forming polysilicon residues on the conductive layer 13 in the peripheral region, in the present embodiment, the upper surface of the conductive layer 13 formed in the second word line 12 is higher than the upper surface of the portion of the polysilicon layer 14 that finally remains in the formed first word line 11.
The conductive layer 13, the polysilicon layer 14 and the barrier layer 15 in the core region form the first word line 11, and after the conductive layer 13 and the barrier layer 15 in the peripheral region form the second word line 12, the method further comprises: a first insulating layer 18 is formed on the substrate 10. The first insulating layer 18 may be an oxide layer, such as silicon dioxide, among others.
Referring to fig. 12, after forming the first insulating layer 18 on the substrate 10, the memory fabrication method further includes: forming a third mask layer on the first insulating layer 18; patterning the third mask layer to form a mask pattern; removing part of the first insulating layer 18 by using the third mask layer as a mask to form a gate trench exposing the substrate 10, wherein the gate trench corresponds to a region where the transistor structure is formed; forming a gate structure 19 in the gate trench; the gate structure 19 of the peripheral region may include a dielectric layer 191, a metal-containing work function adjusting layer 192, a first gate semiconductor layer 193, a second gate semiconductor layer 194, a first electrically conductive layer 195, a second electrically conductive layer 196, and an insulating capping layer 197, which are sequentially stacked, the dielectric layer 191 being formed at the bottom of the gate trench, and thereafter, a second insulating layer 20 being formed on the substrate 10 and the gate structure 19.
The second insulating layer 20 may be a silicon nitride layer or the like.
Further, after forming the second insulating layer 20 on the substrate 10 and the gate structure 19, a first contact hole 21 exposing a portion of the conductive layer 13 in the second word line 12 is formed in the peripheral region, and a second contact hole 22 exposing a portion of the substrate 10 is simultaneously formed in the peripheral region.
Since the upper surface of the conductive layer 13 in the second word line 12 is closer to the upper surface of the substrate 10, the depth of the first contact hole 21 is shallower, so that the time of forming the first contact hole 21 by etching or the like can be reduced, thereby reducing the etching of the surface layer of the substrate 10, reducing the loss of the substrate 10, in addition, the distance between the conductive layer 13 in the second word line 12 and the upper surface of the substrate 10 is smaller, the thickness of the barrier layer 15 on the conductive layer 13 in the second word line 12 is smaller than the thickness of the conductive layer 13, thereby reducing the resistance when the contact structure is in contact connection with the second word line 12, and improving the reliability and stability of the electrical connection between the contact structure and the second word line 12.
Since the first contact hole 21 exposing a portion of the conductive layer 13 in the second word line 12 is formed simultaneously with the formation of the second contact hole 22 exposing a portion of the substrate 10 in the peripheral region, the depth of the first contact hole 21 is reduced, and the depth of the second contact hole 22 is also reduced, thereby avoiding the problem of greater loss of the substrate 10 due to the greater depths of the first contact hole 21 and the second contact hole 22.
It is understood that the simultaneous formation of the first contact hole 21 and the second contact hole 22 may be understood as the integral formation of the first contact hole 21 and the second contact hole 22, so that the processing procedures may be reduced and the processing cost may be reduced.
Specifically, forming the first contact hole 21 exposing a portion of the conductive layer 13 in the second word line 12 in the peripheral region, and simultaneously forming the second contact hole 22 exposing a portion of the substrate 10 in the peripheral region specifically includes: forming a fourth mask layer on the second insulating layer 20; patterning the fourth mask layer to form a mask pattern; sequentially removing the second insulating layer 20, the first insulating layer 18 and the barrier layer 15 in the corresponding region of the second word line 12 by using the fourth mask layer as a mask, so as to form a first contact hole 21 exposing a part of the conductive layer 13; the second insulating layer 20 and the first insulating layer 18 in the corresponding regions of the partial substrate 10 are removed simultaneously and sequentially to form the second contact hole 22 exposing the partial substrate 10.
A contact structure may be formed in the first contact hole 21 such that the second word line 12 is electrically connected with the gate structure 19 through the contact structure; the second contact hole 22 may also have a contact structure formed therein so that the semiconductor layer in the substrate 10 is electrically connected to other devices through the contact structure, which is not particularly limited in this embodiment.
The manufacturing method of the memory provided by the embodiment of the application comprises the following steps: providing a substrate 10, wherein the substrate 10 comprises a core region and a peripheral region positioned outside the core region; the core region includes a plurality of active regions 24 and shallow trench isolation regions 23 isolating the plurality of active regions 24; forming a plurality of word line trenches in each of the active region 24 and the peripheral region; forming a conductive layer 13 in each word line trench, wherein the distance from the upper surface of the conductive layer 13 in the peripheral region to the upper surface of the substrate 10 is smaller than the distance from the upper surface of the conductive layer 13 in the core region to the upper surface of the substrate 10; forming a polysilicon layer 14 on the substrate 10 and the conductive layer 13; removing part of the polysilicon layer 14 in the core region and all of the polysilicon layer 14 in the peripheral region, and retaining part of the polysilicon layer 14 in the wordline trench in the core region; a barrier layer 15 is formed in the word line trench of the core region and in the word line trench of the peripheral region, the conductive layer 13, the polysilicon layer 14 and the barrier layer 15 in the core region form a first word line 11, and the conductive layer 13 and the barrier layer 15 in the peripheral region form a second word line 12. By removing all the polysilicon layer 14 on the peripheral region conductive layer 13, the distance from the upper surface of the conductive layer 13 in the formed second word line 12 to the upper surface of the substrate 10 is made smaller than the distance from the upper surface of the conductive layer 13 in the core region to the upper surface of the substrate 10, so that the depth of the contact hole for exposing the conductive layer 13 in the second word line 12 can be reduced, the depth of other contact holes in the peripheral region substrate 10 integrally formed with the contact hole can be reduced, the loss of the substrate 10 due to etching of the first contact hole 21 and the second contact hole 22 can be reduced, and further, the performance of devices such as transistors in a memory can be improved.
Example two
Referring to fig. 12, on the basis of the first embodiment, an embodiment of the present application provides a memory.
The memory includes a substrate 10, the substrate 10 including a core region and a peripheral region located outside the core region; the core region includes a plurality of active regions 24 and shallow trench isolation regions 23 isolating the plurality of active regions 24; a first word line 11, the first word line 11 is located in the active area 24, the first word line 11 is disposed in the substrate 10 corresponding to the active area 24, and the first word line 11 includes a conductive layer 13, a polysilicon layer 14 and a barrier layer 15 which are sequentially stacked; the second word line 12, the second word line 12 is located in the peripheral area, and is disposed in the substrate 10 corresponding to the peripheral area, and the second word line 12 includes a conductive layer 13 and a barrier layer 15 that are stacked.
Wherein the distance from the upper surface of the conductive layer 13 in the second word line 12 to the upper surface of the substrate 10 is smaller than the distance from the upper surface of the conductive layer 13 in the first word line 11 to the upper surface of the substrate 10, thus, the depth of the first contact hole 21 exposing the conductive layer 13 in the first word line 11 can be reduced, thereby reducing the loss of the substrate 10 due to etching the first contact hole 21, and improving the performance of devices such as transistors in a memory.
The memory provided by the embodiment of the application comprises a substrate, wherein the substrate comprises a core area and a peripheral area positioned outside the core area; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the plurality of active regions; the first word line is positioned in the active area, is arranged in the substrate corresponding to the active area and comprises a conducting layer, a polycrystalline silicon layer and a blocking layer which are sequentially stacked; the second word line is located in the peripheral area and arranged in the substrate corresponding to the peripheral area, and the second word line comprises a conducting layer and a blocking layer which are arranged in a stacked mode. By making the distance from the upper surface of the conductive layer in the second word line to the upper surface of the substrate smaller than the distance from the upper surface of the conductive layer in the first word line to the upper surface of the substrate, the depth of the first contact hole exposing the conductive layer in the first word line can be reduced, thereby reducing the loss of the substrate due to etching the first contact hole, and improving the performance of devices such as transistors in a memory.
In the foregoing description, it should be understood that the terms "mounted," "connected," and "coupled" are to be construed broadly, as well as indirectly, through intermediaries, or in communication between two elements, or in interaction with each other, unless explicitly stated and limited otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used for convenience in describing and simplifying the description of the present application based on the orientation or positional relationship shown in the drawings, and do not denote or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application. In the description of the present application, the meaning of "a plurality" is two or more, unless specifically stated otherwise.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the essence of the corresponding technical solutions.
Claims (14)
1. A method of fabricating a memory, comprising the steps of:
providing a substrate, wherein the substrate comprises a core area and a peripheral area positioned outside the core area; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the plurality of active regions;
forming a plurality of word line trenches in each of the active region and the peripheral region;
forming a conductive layer in each word line trench, wherein the distance from the upper surface of the conductive layer of the peripheral region to the upper surface of the substrate is smaller than the distance from the upper surface of the conductive layer of the core region to the upper surface of the substrate;
forming a polysilicon layer on the substrate and the conductive layer;
removing part of the polysilicon layer of the core region and all of the polysilicon layer of the peripheral region, and reserving part of the polysilicon layer which is positioned in the core region and in the word line groove;
and forming a blocking layer in the word line groove of the core region and the word line groove of the peripheral region, wherein the conducting layer, the polycrystalline silicon layer and the blocking layer in the core region form a first word line, and the conducting layer and the blocking layer in the peripheral region form a second word line.
2. The method of manufacturing a memory device according to claim 1, wherein forming a conductive layer in each of the word line trenches, a distance from an upper surface of the conductive layer of the peripheral region to an upper surface of the substrate being smaller than a distance from an upper surface of the conductive layer of the core region to an upper surface of the substrate, comprises:
forming the conductive layer with a preset thickness in each word line groove of the core area and each word line groove of the peripheral area;
forming a first mask layer in the peripheral region, wherein the first mask layer covers the conductive layer of the peripheral region and the substrate of the peripheral region;
removing part of the conductive layer which is positioned in the core region and the word line groove by taking the first mask layer as a mask, and reserving part of the conductive layer which is positioned in the core region and the word line groove;
and removing the first mask layer.
3. The method of claim 2, wherein the step of forming a conductive layer of a predetermined thickness in each of the word line trenches comprises:
forming a conductive layer in the substrate and each word line trench;
and removing the substrate and part of the conductive layer in each word line groove to form the conductive layer with the preset thickness in each word line groove.
4. The method of claim 1, wherein forming a plurality of word line trenches in each of the active region and the peripheral region comprises:
forming a second mask layer on the substrate;
patterning the second mask layer to expose areas corresponding to the first word lines of the active region and the second word lines of the peripheral region;
and removing part of the substrate by taking the patterned second mask layer as a mask, so as to form the word line groove in the active region and the word line groove in the peripheral region.
5. The method of any one of claims 1 to 4, wherein an upper surface of the conductive layer in the second word line formed is higher than an upper surface of a portion of the polysilicon layer that finally remains in the first word line formed.
6. The method of claim 2, wherein removing the portion of the conductive layer in the word line trench and the core region, and leaving the portion of the conductive layer in the word line trench and the core region, comprises:
And etching the part of the conductive layer which is positioned in the word line groove in the core area by adopting a wet method.
7. The method of manufacturing a memory according to claim 2, wherein forming a first mask layer in the peripheral region, the first mask layer covering the conductive layer of the peripheral region and the substrate of the peripheral region, comprises:
and forming a photoresist layer on the conductive layer of the peripheral area and the substrate of the peripheral area, wherein the photoresist layer covers the conductive layer of the peripheral area and the substrate of the peripheral area, and the photoresist layer forms the first mask layer.
8. The method of any one of claims 1 to 4, wherein the conductive layer is a titanium nitride layer; the barrier layer is a silicon nitride layer.
9. The method of any one of claims 1 to 4, wherein the conductive layer, the polysilicon layer, and the barrier layer in the core region form a first word line, and the conductive layer and the barrier layer in the peripheral region form a second word line, the method further comprising:
A first insulating layer is formed on the substrate.
10. The method of manufacturing a memory device according to claim 9, wherein after forming the first insulating layer over the substrate, the memory device manufacturing method further comprises:
forming a third mask layer on the first insulating layer;
patterning the third mask layer to form a mask pattern;
removing the first insulating layer by taking the third mask layer as a mask to form a gate trench exposing the substrate, wherein the gate trench corresponds to a region for forming a transistor structure;
forming a gate structure in the gate trench;
a second insulating layer is formed over the substrate and the gate structure.
11. The method of claim 10, further comprising, after the step of forming a second insulating layer over the substrate and the gate structure:
and forming a first contact hole exposing a part of the conductive layer in the second word line in the peripheral region, and simultaneously forming a second contact hole exposing a part of the substrate in the peripheral region.
12. The method of claim 11, wherein forming a first contact hole exposing a portion of the conductive layer in the second word line in the peripheral region, and simultaneously forming a second contact hole exposing a portion of the substrate in the peripheral region, comprises:
Forming a fourth mask layer on the second insulating layer;
patterning the fourth mask layer to form a mask pattern;
sequentially removing the second insulating layer, the first insulating layer and the blocking layer in the region corresponding to the second word line by taking the fourth mask layer as a mask, so as to form the first contact hole exposing part of the conductive layer; and synchronously and sequentially removing part of the second insulating layer and the first insulating layer in the corresponding area of the substrate to form a second contact hole exposing part of the substrate.
13. The method of claim 12, wherein the first insulating layer is an oxide layer; the second insulating layer is a silicon nitride layer.
14. A memory, comprising:
a substrate comprising a core region and a peripheral region located outside the core region; the core region comprises a plurality of active regions and shallow trench isolation regions for isolating the plurality of active regions;
the first word line is positioned in the active area, is arranged in the substrate corresponding to the active area and comprises a conductive layer, a polycrystalline silicon layer and a blocking layer which are sequentially stacked;
The second word line is positioned in the peripheral area and arranged in the substrate corresponding to the peripheral area, and comprises a conducting layer and a blocking layer which are arranged in a stacked mode;
wherein a distance from an upper surface of the conductive layer of the peripheral region to an upper surface of the substrate is smaller than a distance from an upper surface of the conductive layer of the core region to an upper surface of the substrate.
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| CN117529084A (en) * | 2022-07-28 | 2024-02-06 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
| CN117677178A (en) * | 2022-08-09 | 2024-03-08 | 长鑫存储技术有限公司 | Semiconductor structure and method of forming same, memory |
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