CN113536868B - Circuit board fault identification method and related equipment - Google Patents
Circuit board fault identification method and related equipmentInfo
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- CN113536868B CN113536868B CN202010324236.6A CN202010324236A CN113536868B CN 113536868 B CN113536868 B CN 113536868B CN 202010324236 A CN202010324236 A CN 202010324236A CN 113536868 B CN113536868 B CN 113536868B
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- G06F18/24—Classification techniques
- G06F18/241—Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches
- G06F18/2411—Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches based on the proximity to a decision surface, e.g. support vector machines
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Abstract
The invention provides a circuit board fault identification method, a circuit board fault identification device, electronic equipment and a storage medium. The circuit board fault identification method comprises the steps of obtaining a circuit board image to be tested of a circuit board to be tested, wherein the circuit board to be tested comprises a plurality of elements to be tested, conducting image marking on the elements to be tested in the circuit board image to obtain candidate images of all the elements to be tested, obtaining position information of all the elements to be tested according to the candidate images of all the elements to be tested, extracting element characteristics of all the candidate images based on an aggregation channel characteristic method to obtain first characteristic vectors of all the candidate images, identifying element types of all the elements to be tested according to the first characteristic vectors of all the candidate images, judging whether the circuit board to be tested has faults according to the element types and the position information of all the elements to be tested, and outputting fault information when the circuit board to be tested has faults. The invention can improve the fault recognition efficiency of the circuit board.
Description
Technical Field
The present invention relates to the field of computer vision, and in particular, to a method and apparatus for identifying a fault of a circuit board, an electronic device, and a storage medium.
Background
Electronic product manufacturers often need to perform fault detection on the produced circuit boards. If the positions of the electronic components in the circuit board are normal, the appearance of each electronic component is normal.
At present, fault detection is carried out on electronic elements in a circuit board through manual spot check, so that the efficiency is low, and missing detection or false detection is easy to occur.
How to improve the detection efficiency and accuracy is a problem to be solved.
Disclosure of Invention
In view of the foregoing, it is necessary to provide a circuit board fault recognition method, apparatus, electronic device, and storage medium that can not only improve the fault recognition efficiency of a circuit board, but also improve the accuracy of recognizing a circuit board fault.
The circuit board fault identification method is applied to electronic equipment and comprises the following steps:
acquiring a circuit board image to be tested of a circuit board to be tested, wherein the circuit board to be tested comprises a plurality of elements to be tested;
Image labeling is carried out on the plurality of elements to be tested in the circuit board image to be tested, and candidate images of the elements to be tested are obtained;
Acquiring the position information of each element to be detected according to the candidate image of each element to be detected;
Extracting element features of each candidate image based on an aggregation channel feature method to obtain a first feature vector of each candidate image;
identifying the element type of each element to be detected according to the first feature vector of each candidate image;
Judging whether the circuit board to be tested has faults according to the element types and the position information of each element to be tested, and outputting fault information when the circuit board to be tested has faults.
A circuit board fault identification device operating in an electronic device, the circuit board fault identification device comprising:
The first acquisition module is used for acquiring a circuit board image to be detected of a circuit board to be detected, and the circuit board to be detected comprises a plurality of elements to be detected;
the labeling module is used for labeling the images of the plurality of elements to be tested in the image of the circuit board to be tested to obtain candidate images of the elements to be tested;
The second acquisition module is used for acquiring the position information of each element to be detected according to the candidate images of each element to be detected;
The extraction module is used for extracting element features of each candidate image based on the aggregation channel feature method to obtain a first feature vector of each candidate image;
the first identification module is used for identifying the element type of each element to be detected according to the first feature vector of each candidate image;
the judging module is used for judging whether the circuit board to be tested has faults according to the element types and the position information of each element to be tested, and outputting fault information when the circuit board to be tested has faults.
An electronic device, the electronic device comprising:
a memory storing at least one instruction, and
And the processor acquires the instructions stored in the memory to realize the circuit board fault identification method.
A computer readable storage medium having stored therein at least one instruction that is fetched by a processor in an electronic device to implement the circuit board fault identification method.
According to the technical scheme, whether the circuit board to be tested has faults or not is judged according to the element types of the elements to be tested and the position information of the elements to be tested, and the fault identification efficiency of the circuit board to be tested can be improved.
Drawings
FIG. 1 is a flow chart of a circuit board fault identification method according to a preferred embodiment of the present invention.
FIG. 2 is a functional block diagram of a preferred embodiment of the circuit board fault identification device of the present invention.
Fig. 3 is a schematic structural diagram of an electronic device according to a preferred embodiment of the present invention for implementing a circuit board fault recognition method.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a flowchart of a circuit board fault recognition method according to a preferred embodiment of the present invention. The order of the steps in the flowchart may be changed and some steps may be omitted according to various needs.
The Circuit board fault recognition method is applied to an electronic device, wherein the electronic device is a device capable of automatically performing numerical calculation and/or information processing according to a preset or stored instruction, and hardware of the electronic device comprises, but is not limited to, a microprocessor, an Application SPECIFIC INTEGRATED Circuit (ASIC), a Programmable gate array (Field-Programmable GATE ARRAY, FPGA), a digital Processor (DIGITAL SIGNAL Processor, DSP), an embedded device and the like.
The electronic device may be any electronic product that can interact with a user, such as a Personal computer, tablet computer, smart phone, personal digital assistant (Personal DIGITAL ASSISTANT, PDA), etc.
The electronic device may also include a network device and/or a user device. Wherein the network device includes, but is not limited to, a single network server, a server group composed of a plurality of network servers, or a Cloud based Cloud Computing (Cloud Computing) composed of a large number of hosts or network servers.
The network in which the electronic device is located includes, but is not limited to, the internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (Virtual Private Network, VPN), and the like.
S10, obtaining a circuit board image to be tested of a circuit board to be tested, wherein the circuit board to be tested comprises a plurality of elements to be tested.
In at least one embodiment of the present invention, the circuit board under test image includes an image of an entire circuit board under test of the electronic device, or an image of a portion of the circuit board under test of the electronic device.
In at least one embodiment of the invention, the circuit board image to be tested is acquired by an industrial camera.
For example, an image of the entire circuit board to be tested may be captured by an industrial camera to obtain the circuit board image to be tested.
In at least one embodiment of the invention, the industrial camera can be controlled by the motion control system to carry out block shooting on the whole circuit board to be tested of the electronic equipment, so as to obtain an image of part of the circuit board to be tested of the electronic equipment.
In at least one embodiment of the invention, the front and the back of the whole circuit board to be tested of the electronic equipment are photographed in blocks through the industrial camera, so that the image of part of the circuit board to be tested of the electronic equipment is obtained.
S11, image labeling is carried out on the plurality of to-be-tested elements in the to-be-tested circuit board image, and candidate images of the to-be-tested elements are obtained.
In at least one embodiment of the present invention, the image labeling the plurality of components under test in the circuit board image under test includes:
sliding on the circuit board image to be detected by sliding windows with different sizes so as to intercept a plurality of sliding images;
Identifying each element to be tested from the plurality of sliding images by using the trained element identification model;
Labeling each identified element to be detected in the image of the circuit board to be detected to obtain candidate images of each element to be detected, wherein the element identification model is a two-class neural network.
In at least one embodiment of the invention, the circuit board fault recognition method further comprises training the component recognition model before the trained component recognition model recognizes each component under test from the plurality of sliding images.
The training the element identification model includes:
Acquiring an element image sample, wherein the element image sample is provided with a corresponding element image label;
taking the element image sample as input, and calculating a recognition result of the element image sample through the element recognition model;
And optimizing the element identification model based on a back propagation algorithm according to the identification result and the element image label to obtain a trained element identification model.
When the element image sample is a complete element, the element image label corresponding to the element image sample is 1 (indicating that the element image sample is an image of a complete element), and when the element image sample is not a complete element, the element image label corresponding to the element image sample is 0 (indicating that the element image sample is not an image of a complete element, or that the element image sample is not an image of an element).
In at least one embodiment of the present invention, before the image labeling of the plurality of components to be tested in the image of the circuit board to be tested, the circuit board fault recognition method further includes:
And preprocessing and calibrating the image of the circuit board to be tested.
S12, acquiring the position information of each element to be detected according to the candidate images of each element to be detected.
In at least one embodiment of the present invention, the obtaining the positional information of each element to be measured according to the candidate image of each element to be measured includes:
Acquiring a first pixel point of the upper left corner of each candidate image;
Determining a first coordinate of the first pixel point in the circuit board image to be detected;
and determining the first coordinates as position information of the element to be detected corresponding to the candidate image.
In at least one embodiment of the present invention, the obtaining the positional information of each element to be measured according to the candidate image of each element to be measured includes:
Acquiring a second pixel point of the center of each candidate image;
determining a second coordinate of the second pixel point in the circuit board image to be detected;
And determining the second coordinates as position information of the element to be detected corresponding to the candidate image.
And S13, extracting element features of each candidate image based on the aggregation channel feature method to obtain a first feature vector of each candidate image.
In at least one embodiment of the present invention, the aggregate channel feature method may superimpose a plurality of different features (e.g., color features, gradient features, and edge features) of each candidate image to form a unified feature.
In at least one embodiment of the present invention, the extracting the element features of each candidate image based on the aggregate channel feature method includes:
Transforming the candidate image to a YUV color space;
determining Y-channel features of the candidate image as first channel features;
Respectively shrinking the feature graphs of the Y, U, V channels of the candidate image by half, taking the feature graphs as the upper left corner, the upper right corner and the lower left corner of the second channel feature, and filling the lower right corner of the second channel feature with 0;
and converting feature images of Y, U, V channels of the candidate image by Sobel operator and performing size scaling to obtain three edge images, wherein the three edge images are used as an upper left corner, an upper right corner and a lower left corner of the features of the second channel, and each position in the three edge images is used as a lower right corner by taking a pixel value with the largest amplitude value.
The element features of each candidate image may efficiently describe the element features corresponding to the candidate image.
S14, identifying the element type of each element to be tested according to the first feature vector of each candidate image.
In at least one embodiment of the present invention, an AdaBoost classifier may be trained, through which the element type of each element to be tested is identified according to the first feature vector of each candidate image.
A first candidate image sample and a first tag of the first candidate image sample may be acquired;
Extracting element features of the first candidate image sample based on an aggregation channel feature method to obtain a first feature vector sample of the first candidate image sample;
taking a decision tree as a weak classifier, taking a first feature vector sample of the first candidate image sample as an input, and carrying out combined training on a plurality of weak classifiers according to the first label;
the weak classifiers are weighted and combined to obtain a strong classifier applied to element type classification;
And identifying the element type of each element to be detected according to the first feature vector of each candidate image through the strong classifier.
In at least one embodiment of the invention, the element types include chip elements, resistive elements, capacitive elements, and the like.
S15, judging whether the circuit board to be tested has faults according to the element types and the position information of each element to be tested, and outputting fault information when the circuit board to be tested has faults.
In at least one embodiment of the present invention, the determining whether the circuit board to be tested has a fault according to the component type and the position information of each component to be tested includes:
Determining the element number of each element type of the circuit board to be tested according to the element type of each element to be tested;
acquiring the element number of each element type of a standard circuit board and the standard position of each element to be tested;
judging whether the number of the elements of each given element type of the circuit board to be tested is smaller than the number of the elements of the given element type of the standard circuit board;
If the number of the components of the given component type of the circuit board to be tested is smaller than the number of the components of the given component type of the standard circuit board, determining that the circuit board to be tested has a component dropping fault;
Judging whether the position information of each given element to be tested of the circuit board to be tested is consistent with the standard position of the given element to be tested of the standard circuit board;
And if the position information of the given element to be tested of the circuit board to be tested is inconsistent with the standard position of the given element to be tested of the standard circuit board, the circuit board to be tested has a collision piece fault.
In at least one embodiment of the present invention, if the number of components of the given component type of the circuit board under test is equal to the number of components of the given component type of the standard circuit board, and the positional information of the given component under test of the circuit board under test is identical to the standard position of the given component under test of the standard circuit board, it is determined that the circuit board under test is free from a fault.
In at least one embodiment of the present invention, the circuit board fault recognition method further includes:
and identifying the fault element in each element to be detected according to each candidate image through a support vector machine.
In at least one embodiment of the present invention, the identifying, by the support vector machine, the faulty component among the components to be tested according to the candidate images includes:
acquiring a plurality of second candidate image samples and second labels of the second candidate image samples;
extracting second feature vectors of each second candidate image by adopting a local binary pattern algorithm;
Training the support vector machine classifier according to the second feature vector of each second candidate image and the second label of each second candidate image sample to obtain a trained support vector machine classifier;
and identifying the fault element in each element to be tested through the trained support vector machine classifier.
Before the trained support vector machine classifier identifies the fault element in each element to be tested, the circuit board fault identification method further comprises the following steps:
Generating a type vector of each second candidate image sample according to the element type of each second candidate image sample;
Connecting the second feature vector and the type vector of each second candidate image sample to obtain a third feature vector of each second candidate image;
And training the support vector machine classifier according to the third feature vector of each second candidate image and the second label of each second candidate image sample to obtain a trained support vector machine classifier.
The support vector machine classifier can be trained through small samples, so that the problem of difficult sample collection is solved, and the support vector machine classifier has good robustness and high accuracy.
In at least one embodiment of the present invention, the classification types of the trained support vector machine classifier may include normal elements, damaged elements, blank-welded elements, residual glue elements, and the like.
In at least one embodiment of the present invention, the classification type of the trained support vector machine classifier may include normal elements and fault elements.
The average fault recognition time of the method for a circuit board image with the resolution of 2448 x 2048 is 2.51 seconds, so that the fault recognition efficiency is improved.
According to the technical scheme, the method judges whether the circuit board to be tested has faults or not according to the element types of the elements to be tested and the position information of the elements to be tested, and can improve the fault identification efficiency of the circuit board to be tested. In addition, the method can identify the fault element in each element to be detected according to each candidate image through the support vector machine, can accurately identify the fault element in the circuit board to be detected, and improves the accuracy of identifying the fault of the circuit board to be detected.
Fig. 2 is a functional block diagram of a circuit board fault recognition device according to a preferred embodiment of the present invention. The circuit board fault recognition device operates in the electronic equipment. The circuit board fault recognition device 11 includes a first acquisition module 110, a labeling module 111, a second acquisition module 112, an extraction module 113, a recognition module 114, and a judgment module 115. The module referred to in the present invention refers to a series of computer program segments, which are stored in a memory, that can be fetched by a processor and that can fulfill a fixed function. In the present embodiment, the functions of the respective modules will be described in detail in the following embodiments.
The first obtaining module 110 is configured to obtain an image of a circuit board to be tested of the circuit board to be tested, where the circuit board to be tested includes a plurality of components to be tested.
In at least one embodiment of the present invention, the circuit board under test image includes an image of an entire circuit board under test of the electronic device, or an image of a portion of the circuit board under test of the electronic device.
In at least one embodiment of the invention, the circuit board image to be tested is acquired by an industrial camera.
For example, an image of the entire circuit board to be tested may be captured by an industrial camera to obtain the circuit board image to be tested.
In at least one embodiment of the invention, the industrial camera can be controlled by the motion control system to carry out block shooting on the whole circuit board to be tested of the electronic equipment, so as to obtain an image of part of the circuit board to be tested of the electronic equipment.
In at least one embodiment of the invention, the front and the back of the whole circuit board to be tested of the electronic equipment are photographed in blocks through the industrial camera, so that the image of part of the circuit board to be tested of the electronic equipment is obtained.
The labeling module 111 is configured to label the images of the plurality of to-be-tested elements in the to-be-tested circuit board image, so as to obtain candidate images of each to-be-tested element.
In at least one embodiment of the present invention, the image labeling the plurality of components under test in the circuit board image under test includes:
sliding on the circuit board image to be detected by sliding windows with different sizes so as to intercept a plurality of sliding images;
Identifying each element to be tested from the plurality of sliding images by using the trained element identification model;
Labeling each identified element to be detected in the image of the circuit board to be detected to obtain candidate images of each element to be detected, wherein the element identification model is a two-class neural network.
In at least one embodiment of the present invention, the circuit board fault recognition device 11 further includes a training module 116 for training the component recognition model after the trained component recognition model is used to recognize each component under test from the plurality of sliding images.
The training the element identification model includes:
Acquiring an element image sample, wherein the element image sample is provided with a corresponding element image label;
taking the element image sample as input, and calculating a recognition result of the element image sample through the element recognition model;
And optimizing the element identification model based on a back propagation algorithm according to the identification result and the element image label to obtain a trained element identification model.
When the element image sample is a complete element, the element image label corresponding to the element image sample is 1 (indicating that the element image sample is an image of a complete element), and when the element image sample is not a complete element, the element image label corresponding to the element image sample is 0 (indicating that the element image sample is not an image of a complete element, or that the element image sample is not an image of an element).
In at least one embodiment of the present invention, the circuit board fault recognition device 11 further includes a preprocessing module 117 for preprocessing and calibrating the circuit board image to be tested before the image labeling of the plurality of components to be tested in the circuit board image to be tested.
The second obtaining module 112 is configured to obtain the position information of each element to be tested according to the candidate image of each element to be tested.
In at least one embodiment of the present invention, the obtaining the positional information of each element to be measured according to the candidate image of each element to be measured includes:
Acquiring a first pixel point of the upper left corner of each candidate image;
Determining a first coordinate of the first pixel point in the circuit board image to be detected;
and determining the first coordinates as position information of the element to be detected corresponding to the candidate image.
In at least one embodiment of the present invention, the obtaining the positional information of each element to be measured according to the candidate image of each element to be measured includes:
Acquiring a second pixel point of the center of each candidate image;
determining a second coordinate of the second pixel point in the circuit board image to be detected;
And determining the second coordinates as position information of the element to be detected corresponding to the candidate image.
The extracting module 113 is configured to extract element features of each candidate image based on the aggregate channel feature method, so as to obtain a first feature vector of each candidate image.
In at least one embodiment of the present invention, the aggregate channel feature method may superimpose a plurality of different features (e.g., color features, gradient features, and edge features) of each candidate image to form a unified feature.
In at least one embodiment of the present invention, the extracting the element features of each candidate image based on the aggregate channel feature method includes:
Transforming the candidate image to a YUV color space;
determining Y-channel features of the candidate image as first channel features;
Respectively shrinking the feature graphs of the Y, U, V channels of the candidate image by half, taking the feature graphs as the upper left corner, the upper right corner and the lower left corner of the second channel feature, and filling the lower right corner of the second channel feature with 0;
and converting feature images of Y, U, V channels of the candidate image by Sobel operator and performing size scaling to obtain three edge images, wherein the three edge images are used as an upper left corner, an upper right corner and a lower left corner of the features of the second channel, and each position in the three edge images is used as a lower right corner by taking a pixel value with the largest amplitude value.
The element features of each candidate image may efficiently describe the element features corresponding to the candidate image.
The identifying module 114 is configured to identify a component type of each component to be tested according to the first feature vector of each candidate image.
In at least one embodiment of the present invention, an AdaBoost classifier may be trained, through which the element type of each element to be tested is identified according to the first feature vector of each candidate image.
A first candidate image sample and a first tag of the first candidate image sample may be acquired;
Extracting element features of the first candidate image sample based on an aggregation channel feature method to obtain a first feature vector sample of the first candidate image sample;
taking a decision tree as a weak classifier, taking a first feature vector sample of the first candidate image sample as an input, and carrying out combined training on a plurality of weak classifiers according to the first label;
the weak classifiers are weighted and combined to obtain a strong classifier applied to element type classification;
And identifying the element type of each element to be detected according to the first feature vector of each candidate image through the strong classifier.
In at least one embodiment of the invention, the element types include chip elements, resistive elements, capacitive elements, and the like.
The judging module 115 is configured to judge whether the circuit board to be tested has a fault according to the element type and the position information of each element to be tested, and output fault information when the circuit board to be tested has a fault.
In at least one embodiment of the present invention, the determining whether the circuit board to be tested has a fault according to the component type and the position information of each component to be tested includes:
Determining the element number of each element type of the circuit board to be tested according to the element type of each element to be tested;
acquiring the element number of each element type of a standard circuit board and the standard position of each element to be tested;
judging whether the number of the elements of each given element type of the circuit board to be tested is smaller than the number of the elements of the given element type of the standard circuit board;
If the number of the components of the given component type of the circuit board to be tested is smaller than the number of the components of the given component type of the standard circuit board, determining that the circuit board to be tested has a component dropping fault;
Judging whether the position information of each given element to be tested of the circuit board to be tested is consistent with the standard position of the given element to be tested of the standard circuit board;
And if the position information of the given element to be tested of the circuit board to be tested is inconsistent with the standard position of the given element to be tested of the standard circuit board, the circuit board to be tested has a collision piece fault.
In at least one embodiment of the present invention, if the number of components of the given component type of the circuit board under test is equal to the number of components of the given component type of the standard circuit board, and the positional information of the given component under test of the circuit board under test is identical to the standard position of the given component under test of the standard circuit board, it is determined that the circuit board under test is free from a fault.
In at least one embodiment of the present invention, the identifying module 114 is further configured to identify, by means of a support vector machine, a faulty component in each component under test according to each candidate image.
In at least one embodiment of the present invention, the identifying, by the support vector machine, the faulty component among the components to be tested according to the candidate images includes:
acquiring a plurality of second candidate image samples and second labels of the second candidate image samples;
extracting second feature vectors of each second candidate image by adopting a local binary pattern algorithm;
Training the support vector machine classifier according to the second feature vector of each second candidate image and the second label of each second candidate image sample to obtain a trained support vector machine classifier;
and identifying the fault element in each element to be tested through the trained support vector machine classifier.
The training module is further used for generating a type vector of each second candidate image sample according to the element type of each second candidate image sample before the trained support vector machine classifier identifies the fault element in each element to be tested;
Connecting the second feature vector and the type vector of each second candidate image sample to obtain a third feature vector of each second candidate image;
And training the support vector machine classifier according to the third feature vector of each second candidate image and the second label of each second candidate image sample to obtain a trained support vector machine classifier.
The support vector machine classifier can be trained through small samples, so that the problem of difficult sample collection is solved, and the support vector machine classifier has good robustness and high accuracy.
In at least one embodiment of the present invention, the classification types of the trained support vector machine classifier may include normal elements, damaged elements, blank-welded elements, residual glue elements, and the like.
In at least one embodiment of the present invention, the classification type of the trained support vector machine classifier may include normal elements and fault elements.
The device has the advantages that the average fault recognition time of the device for a circuit board image with the resolution of 2448 x 2048 is 2.51 seconds, and the fault recognition efficiency is improved.
According to the technical scheme, the device judges whether the circuit board has faults or not according to the element types of the elements to be detected and the position information of the elements to be detected, and can improve the fault identification efficiency of the circuit board. In addition, the device can identify the fault element in each element to be detected according to each candidate image through the support vector machine, so that the fault element in the circuit board can be accurately identified, and the accuracy of identifying the fault of the circuit board is improved.
Fig. 3 is a schematic structural diagram of an electronic device according to a preferred embodiment of the present invention for implementing the method for identifying a circuit board fault.
In one embodiment of the invention, the electronic device 1 includes, but is not limited to, a memory 12, a processor 13, and a computer program, such as a circuit board fault identification program, stored in the memory 12 and executable on the processor 13.
It will be appreciated by those skilled in the art that the schematic diagram is merely an example of the electronic device 1 and does not constitute a limitation of the electronic device 1, and may include more or less components than illustrated, or may combine certain components, or different components, e.g. the electronic device 1 may further include input-output devices, network access devices, buses, etc.
The Processor 13 may be a central processing module (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc., and the processor 13 is an operation core and a control center of the electronic device 1, connects various parts of the entire electronic device 1 by using various interfaces and lines, and obtains an operating system of the electronic device 1 and various installed application programs, program codes, etc.
The processor 13 obtains an operating system of the electronic device 1 and various applications installed. The processor 13 obtains the application program to implement the steps in the embodiments of the method for identifying a fault of a circuit board described above, for example, the steps shown in fig. 1.
Illustratively, the computer program may be split into one or more modules that are stored in the memory 12 and retrieved by the processor 13 to complete the present invention. The one or more modules may be a series of computer program instruction segments capable of performing a specific function for describing the acquisition process of the computer program in the electronic device 1. For example, the computer program may be divided into a first acquisition module 110, a labeling module 111, a second acquisition module 112, an extraction module 113, an identification module 114, a judgment module 115.
The memory 12 may be used to store the computer program and/or module, and the processor 13 may implement various functions of the electronic device 1 by running or retrieving the computer program and/or module stored in the memory 12 and invoking data stored in the memory 12. The memory 12 may mainly include a storage program area that may store an operating system, application programs required for at least one function (such as a sound playing function, an image playing function, etc.), etc., and a storage data area that may store data created according to the use of the electronic device, etc. In addition, the memory 12 may include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart memory card (SMARTMEDIA CARD, SMC), secure Digital (SD) card, flash memory card (FLASH CARD), at least one disk storage device, flash memory device, or other non-volatile solid-state storage device.
The memory 12 may be an external memory and/or an internal memory of the electronic device 1. Further, the memory 12 may be a physical memory, such as a memory bank, a TF card (Trans-FLASH CARD), or the like.
The modules integrated in the electronic device 1 may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand alone product. Based on such understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, where the computer program, when acquired by a processor, may implement the steps of each of the method embodiments described above.
Wherein the computer program comprises computer program code which may be in the form of source code, object code, an available file or some intermediate form, etc. The computer readable medium may include any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM).
In combination with fig. 1, the memory 12 in the electronic device 1 stores a plurality of instructions to implement a circuit board fault identification method, and the processor 13 may acquire the plurality of instructions to implement that MAC values of a plurality of machine nodes are acquired, ID addresses are allocated to the plurality of machine nodes according to the MAC values of the plurality of machine nodes, a machine node state table is generated according to the MAC values of the plurality of machine nodes and the ID addresses, a heartbeat instruction is sent to the plurality of machine nodes according to the machine node state table, a heartbeat packet returned by the plurality of machine nodes in response to the heartbeat instruction is received, and states of the plurality of machine nodes are determined according to the heartbeat packet and the machine node state table.
Specifically, the specific implementation method of the above instructions by the processor 13 may refer to the description of the relevant steps in the corresponding embodiment of fig. 1, which is not repeated herein.
In the several embodiments provided in the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be other manners of division when actually implemented.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in hardware plus software functional modules.
The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference signs in the claims shall not be construed as limiting the claim concerned.
Furthermore, it is evident that the word "comprising" does not exclude other modules or steps, and that the singular does not exclude a plurality. A plurality of modules or means recited in the system claims can also be implemented by means of one module or means in software or hardware. The terms second, etc. are used to denote a name, but not any particular order.
Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
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| CN115205575A (en) * | 2022-05-07 | 2022-10-18 | 奥蒂玛光学科技（深圳）有限公司 | Circuit element labeling method, related method, equipment, terminal and storage medium |
| CN115937170A (en) * | 2022-12-23 | 2023-04-07 | 正泰集团研发中心(上海)有限公司 | Circuit board detection method, device, computer equipment and storage medium |
| CN116664491A (en) * | 2023-04-23 | 2023-08-29 | 深圳市世宗自动化设备有限公司 | Soft film circuit board defect detection method and related device |
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