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CN113517270A - Preparation method of low-thickness packaging structure of embedded chip of large-board-level fan-out substrate - Google Patents

Preparation method of low-thickness packaging structure of embedded chip of large-board-level fan-out substrate Download PDF

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Publication number
CN113517270A
CN113517270A CN202110608800.1A CN202110608800A CN113517270A CN 113517270 A CN113517270 A CN 113517270A CN 202110608800 A CN202110608800 A CN 202110608800A CN 113517270 A CN113517270 A CN 113517270A
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layer
chip
dielectric layer
capacitor
dry film
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Inventor
崔成强
成海涛
杨斌
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Xinhua Microelectronics Technology Co ltd
Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Priority to CN202110608800.1A priority Critical patent/CN113517270A/en
Publication of CN113517270A publication Critical patent/CN113517270A/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention discloses a preparation method of a low-thickness packaging structure of a pre-embedded chip of a large board-level fan-out substrate, which comprises the following steps: packaging the ASIC chip and the capacitor on one surface of the carrier plate by adopting a plastic packaging layer; removing the carrier plate, manufacturing a first dielectric layer on the first surface of the plastic packaging layer, and sticking the resistor on the first dielectric layer; opening holes in the plastic packaging layer and the first dielectric layer, manufacturing a first rewiring layer on the first dielectric layer, and manufacturing a second rewiring layer on the second surface of the plastic packaging layer; manufacturing a second dielectric layer on the first rewiring layer; opening the second dielectric layer, and manufacturing a third rewiring layer on the second dielectric layer; and placing the sensor chip on the second redistribution layer and electrically connecting the sensor chip with the second redistribution layer. The ASIC chip is packaged into the substrate through the fan-out technology, the thickness of the packaging structure is reduced, the chip leakage is prevented, meanwhile, the capacitor and the resistor are embedded into the substrate, the thickness of the packaging structure is further reduced, and the compactness of the whole packaging structure is improved.

Description

Preparation method of low-thickness packaging structure of embedded chip of large-board-level fan-out substrate
Technical Field
The invention relates to the technical field of packaging, in particular to a preparation method of a low-thickness packaging structure of a pre-embedded chip of a large-board-level fan-out substrate.
Background
Micro-Electro-Mechanical Systems (MEMS for short) is a process technology that combines Micro-electronic technology and Mechanical engineering, and its operating range is in the micrometer range. Application Specific Integrated Circuits (ASICs) are considered to be a special purpose designed Integrated Circuit in the Integrated Circuit community.
The packaging structure of the sensor chip and the ASIC chip opens up a brand new technical field and industry, and the microsensor and the like manufactured based on the packaging structure have very wide application prospects in all fields which people can contact.
Among the prior art, the sensor chip among the general sensor module and the packaging structure of ASIC chip are directly relatively fixed or welded fastening on the PCB board through the glue film laminating with the two, so, sensor module in the use, the sealed condition of revealing of chip appears easily to this kind of packaging method will lead to the whole packaging structure thickness thickening of PCB, to some packaging structure thickness application scenes that require height, prior art obviously can't satisfy the demand.
Disclosure of Invention
The invention aims to provide a preparation method of a low-thickness packaging structure of a pre-embedded chip of a large board-level fan-out substrate, which reduces the thickness of the packaging structure, prevents the chip from leaking and improves the compactness of the whole packaging structure.
In order to achieve the purpose, the invention adopts the following technical scheme:
the preparation method of the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate comprises the following steps:
s10, providing a carrier plate, an ASIC chip and a capacitor, packaging the ASIC chip and the capacitor on one surface of the carrier plate at intervals by adopting a plastic package layer, and enabling an I/O interface of the ASIC chip to face to one side adjacent to the carrier plate;
s20, removing the carrier plate, providing a resistor, manufacturing a first dielectric layer on the first surface of the plastic packaging layer, and adhering the resistor on the first dielectric layer;
s30, performing hole opening processing on the plastic package layer and the first dielectric layer, manufacturing a first rewiring layer on the first dielectric layer, wherein the first rewiring layer is electrically connected with an I/O interface of the ASIC chip, one side of the capacitor and two ends of the resistor respectively, and manufacturing a second rewiring layer on the second surface of the plastic package layer, and the second rewiring layer is electrically connected with the first rewiring layer and the other side of the capacitor respectively;
s40, forming a second dielectric layer on the first redistribution layer, the second dielectric layer covering the first redistribution layer and the first dielectric layer exposed from the first redistribution layer;
s50, carrying out opening processing on the second dielectric layer, and manufacturing a third rewiring layer connected with the first rewiring layer on the second dielectric layer;
and S60, providing a sensor chip, and electrically connecting the I/O interface of the sensor chip with the second rewiring layer.
As an optimal scheme of the preparation method of the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate, the step S30 specifically includes:
s30a, opening holes in the plastic package layer and the first dielectric layer to form a first hole site penetrating through the plastic package layer and the first dielectric layer, a second hole site exposing one side of the capacitor and a third hole site exposing the I/O interface of the ASIC chip and the other side of the capacitor;
s30b, forming a first seed layer on the first dielectric layer through vacuum sputtering, and forming a second seed layer on the second surface of the plastic packaging layer;
s30c, providing a first photosensitive dry film and a second photosensitive dry film, and attaching the first photosensitive dry film to the first seed layer and the second photosensitive dry film to the second seed layer;
s30d, forming a first via hole and a first patterned hole exposing the first seed layer to the first via hole on the first photosensitive dry film, and forming a second via hole and a second patterned hole exposing the second seed layer to the second via hole on the second photosensitive dry film through exposure and development processes;
and S30e, performing electroplating treatment, forming a first conductive column in the first hole site, forming a second conductive column electrically connected with the capacitor in the second hole site, forming a third conductive column in the third hole site, forming a first redistribution layer electrically connected with the I/O interface of the ASIC chip, one side of the capacitor, two ends of the resistor and one end of the first conductive column in the first patterned hole, and forming a second redistribution layer electrically connected with the other end of the first conductive column and the other side of the capacitor in the second patterned hole.
As a preferable scheme of the preparation method of the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate, the method between the step S30 and the step S40 further comprises the following steps:
s30f, removing the residual first photosensitive dry film and the second photosensitive dry film;
and S30g, providing an etching solution, and performing etching treatment on the exposed first seed layer after the first photosensitive dry film is removed and the exposed second seed layer after the second photosensitive dry film is removed by using the etching solution to remove the first seed layer and the second seed layer.
As an optimal scheme of the preparation method of the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate, the step S50 specifically includes:
s50a, carrying out opening processing on the second dielectric layer to form a fourth hole position for exposing the first rewiring layer;
s50b, forming a third sub-layer on the second dielectric layer through vacuum sputtering;
s50c, providing a third photosensitive dry film, and attaching the third photosensitive dry film to the third sublayer;
s50d, forming a third through hole and a third patterned hole exposing the third sub-layer to the third through hole on the third photosensitive dry film through exposure and development;
and S50e, performing electroplating treatment, forming a fourth conductive pillar in the fourth hole, and forming a third redistribution layer electrically connected with the fourth conductive pillar in the third patterned hole.
As a preferable scheme of the preparation method of the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate, the method between the step S50 and the step S60 further comprises the following steps:
s50f, removing the residual third photosensitive dry film;
and S50g, providing an etching solution, and etching the exposed third sub-layer after the third photosensitive dry film is removed by using the etching solution to remove the third sub-layer.
As an optimal scheme of the preparation method of the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate, the step S10 specifically includes:
s10a, providing a carrier plate and bonding glue, and attaching the bonding glue to one surface of the carrier plate;
s10b, providing an ASIC chip and a capacitor, attaching the ASIC chip and the capacitor on the bonding glue at intervals, and enabling an I/O interface of the ASIC chip to face to one side adjacent to the bonding glue;
s10c, carrying out plastic package on the ASIC chip and the capacitor to form a plastic package layer for coating the ASIC chip and the capacitor.
As a preferable scheme of the preparation method of the low-thickness packaging structure of the embedded chip of the large-board-level fan-out substrate, in step S50, the method further includes opening holes in the plastic package layer, the first dielectric layer and the second dielectric layer, and forming a sound hole for transmitting sound below the sensor chip.
As a preferable scheme of the preparation method of the low-thickness packaging structure of the embedded chip of the large-board-level fan-out substrate, in step S60, the sensor chip forms a metal bump at an I/O interface by using tin solder, silver solder or gold-tin alloy solder, and the metal bump is electrically connected with the third redistribution layer.
As a preferable scheme of the preparation method of the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate, in step S60, a metal frame is further provided, the metal frame is adhered to the second dielectric layer, and the sensor chip and the third redistribution layer are both located in the metal frame.
As a preferable scheme of the preparation method of the low-thickness packaging structure of the embedded chip of the large-board-level fan-out substrate, the etching solution is selected from inorganic acid, organic acid or a mixed solution of organic acid and hydrogen peroxide.
The invention has the beneficial effects that: the ASIC chip is packaged into the substrate through the fan-out technology, and the substrate can replace an organic PCB board to realize the functions of bearing the sensor chip, electrically connecting and transmitting sound; compared with the prior art that the ASIC chip and the IPD chip are fixed on the PCB in a bonding mode through the glue layer, the ASIC chip is directly packaged in the substrate, the thickness of the packaging structure is smaller, the chip leakage condition cannot occur, meanwhile, the capacitor and the resistor are embedded in the substrate to form the filter circuit, compared with the IPD chip, the thickness of the packaging structure of the embedded capacitor and the embedded resistor can be further reduced, the installation position of the embedded capacitor and the embedded resistor is more flexible, and the compactness of the whole packaging structure can be effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below. It is obvious that the drawings described below are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a process flow diagram of a manufacturing method of a low-thickness package structure of a large board-level fan-out substrate embedded chip according to a first embodiment of the present invention.
Fig. 2 is a flowchart illustrating a specific process of step S10 according to a first embodiment of the present invention.
Fig. 3 is a flowchart illustrating a specific process of step S30 according to a first embodiment of the present invention.
Fig. 4 is a flowchart illustrating a specific process of step S50 according to a first embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of an intermediate product after the ASIC chip and the capacitor are attached to the carrier board according to a first embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of an intermediate product after a molding layer is manufactured according to a first embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of an intermediate product after removing the carrier according to a first embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of an intermediate product after the first dielectric layer and the resistor are formed according to a first embodiment of the invention.
Fig. 9 is a schematic cross-sectional view of an intermediate product after punching the first dielectric layer and the molding layer according to the first embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of an intermediate product after a first seed layer, a first dry film, a second seed layer, and a second dry film are manufactured according to a first embodiment of the disclosure.
Fig. 11 is a schematic cross-sectional view of an intermediate product after a first redistribution layer and a second redistribution layer are fabricated according to a first embodiment of the present invention.
Fig. 12 is a schematic cross-sectional view of an intermediate product after a second dielectric layer is formed according to a first embodiment of the invention.
Fig. 13 is a schematic cross-sectional view of an intermediate product after punching the molding layer, the first dielectric layer and the second dielectric layer according to the first embodiment of the present invention.
Fig. 14 is a schematic cross-sectional view of an intermediate product after a third sub-layer and a third photosensitive dry film are manufactured according to a first embodiment of the present invention.
Fig. 15 is a schematic cross-sectional view of an intermediate product after a third redistribution layer is formed according to a first embodiment of the present invention.
Fig. 16 is a schematic cross-sectional view of an intermediate product after the sensor chip is connected to the third redistribution layer according to the first embodiment of the present invention.
Fig. 17 is a schematic cross-sectional view of a low-thickness package structure of a pre-embedded chip of a large board-level fan-out substrate according to a first embodiment of the invention.
Fig. 18 is a schematic cross-sectional view of a low-thickness package structure of a large board-level fan-out substrate embedded chip according to a second embodiment of the invention.
In fig. 1 to 18:
1. a carrier plate; 2. an ASIC chip; 3. a capacitor;
4. a plastic packaging layer; 41. a first side; 42. a second face;
5. a resistance;
61. a first dielectric layer; 62. a second dielectric layer;
71. a first rewiring layer; 72. a first seed layer; 73. a first photosensitive dry film;
81. a second rewiring layer; 82. a second seed layer; 83. a second photosensitive dry film;
91. a third triple wiring layer; 92. a third sub-layer; 93. a third photosensitive dry film;
10. a sensor chip; 11. bonding glue; 12. a metal frame;
101. a first hole site; 102. a second hole site; 103. a third hole site; 104. a fourth hole site; 105. a sound hole;
201. a first conductive post; 202. a second conductive post; 203. a third conductive pillar; 204. and a fourth conductive pillar.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Wherein the showings are for the purpose of illustration only and are shown by way of illustration only and not in actual form, and are not to be construed as limiting the present patent; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not indicated or implied that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and are not to be construed as limitations of the present patent, and the specific meanings of the terms may be understood by those skilled in the art according to specific situations.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" or the like, if appearing to indicate a connection relationship between the components, is to be understood broadly, for example, as being fixed or detachable or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through one or more other components or may be in an interactive relationship with one another. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The first embodiment is as follows:
as shown in fig. 1, the invention provides a method for preparing a low-thickness packaging structure of a pre-embedded chip of a large board-level fan-out substrate, which comprises the following steps:
s10, providing a carrier board 1, an ASIC chip 2 and a capacitor 3, packaging the ASIC chip 2 and the capacitor 3 on one surface of the carrier board 1 at intervals by using a molding layer 4, and making an I/O interface of the ASIC chip 2 face to one side adjacent to the carrier board 1, referring to fig. 5-6;
s20, removing the carrier board 1, providing the resistor 5, forming a first dielectric layer 61 on the first surface 41 of the molding layer 4, and attaching the resistor 5 to the first dielectric layer 61, referring to fig. 7-8;
s30, forming holes in the molding compound layer 4 and the first dielectric layer 61, forming a first redistribution layer 71 on the first dielectric layer 61 and electrically connected to the I/O interface of the ASIC chip 2, one side of the capacitor 3, and both ends of the resistor 5, and forming a second redistribution layer 81 on the second surface 42 of the molding compound layer 4 and electrically connected to the first redistribution layer 71 and the other side of the capacitor 3, as shown in fig. 9-11;
s40, fabricating a second dielectric layer 62 on the first redistribution layer 71, wherein the second dielectric layer 62 covers the first redistribution layer 71 and the first dielectric layer 61 exposed from the first redistribution layer 71, as shown in fig. 12;
s50, opening the second dielectric layer 62, and forming a third redistribution layer 91 on the second dielectric layer 62, the third redistribution layer being connected to the first redistribution layer 71, as shown in fig. 13-15;
s60, providing the sensor chip 10, and electrically connecting the I/O interface of the sensor chip 10 with the second redistribution layer 81, referring to fig. 16.
The ASIC chip 2 is packaged into the substrate through the fan-out technology, and the substrate can replace an organic PCB board to realize the functions of bearing the sensor chip 10, electrically connecting and transmitting sound; compared with the prior art that the ASIC chip 2 and the IPD chip are fixed on the PCB in a bonding mode through the glue layer, the ASIC chip 2 is directly packaged in the substrate, the thickness of the packaging structure is smaller, the chip leakage condition cannot occur, meanwhile, the capacitor 3 and the resistor 5 are embedded in the substrate to form the filter circuit, compared with the IPD chip, the thickness of the packaging structure of the embedded capacitor and the embedded resistor can be further reduced, the installation position of the embedded capacitor and the embedded resistor is more flexible, and the compactness of the whole packaging structure can be effectively improved.
As shown in fig. 2, step S10 specifically includes:
s10a, providing a carrier plate 1 and bonding glue 11, and attaching the bonding glue 11 to one surface of the carrier plate 1;
s10b, providing the ASIC chip 2 and the capacitor 3, attaching the ASIC chip 2 and the capacitor 3 to the bonding adhesive 11 at an interval, and making the I/O interface of the ASIC chip 2 face to a side adjacent to the bonding adhesive 11, referring to fig. 5;
s10c, plastic-packaging the ASIC chip 2 and the capacitor 3 to form a plastic-packaging layer 4 covering the ASIC chip 2 and the capacitor 3, referring to fig. 6.
As shown in fig. 3, step S30 specifically includes:
s30a, opening holes in the molding compound layer 4 and the first dielectric layer 61 to form a first hole 101 penetrating through the molding compound layer 4 and the first dielectric layer 61, a second hole 102 exposing one side of the capacitor 3, and a third hole 103 exposing the I/O interface of the ASIC chip 2 and the other side of the capacitor 3, as shown in fig. 9;
s30b, forming a first seed layer 72 on the first dielectric layer 61 by vacuum sputtering, and forming a second seed layer 82 on the second surface 42 of the molding layer 4;
s30c, providing a first photosensitive dry film 73 and a second photosensitive dry film 83, attaching the first photosensitive dry film 73 to the first seed layer 72, and attaching the second photosensitive dry film 83 to the second seed layer 82, referring to fig. 10;
s30d, forming a first through hole and a first patterned hole exposing the first seed layer 72 to the first through hole on the first photosensitive dry film 73, and forming a second through hole and a second patterned hole exposing the second seed layer 82 to the second through hole on the second photosensitive dry film 83 by exposure and development processes;
s30e, performing electroplating, forming a first conductive pillar 201 in the first hole 101, a second conductive pillar 202 in the second hole 102 and electrically connected to the capacitor 3, a third conductive pillar 203 in the third hole 103, a first redistribution layer 71 in the first patterned hole and electrically connected to the I/O interface of the ASIC chip 2, one side of the capacitor 3, two ends of the resistor 5 and one end of the first conductive pillar 201, and a second redistribution layer 81 in the second patterned hole and electrically connected to the other end of the first conductive pillar 201 and the other side of the capacitor 3, respectively;
s30f, removing the residual first photosensitive dry film 73 and the second photosensitive dry film 83;
s30g, providing an etching solution, and performing an etching process on the exposed first seed layer 72 after the first photosensitive dry film 73 is removed and the exposed second seed layer 82 after the second photosensitive dry film 83 is removed by using the etching solution to remove the first seed layer 72 and the second seed layer 82, referring to fig. 11.
As shown in fig. 4, step S50 specifically includes:
s50a, opening the second dielectric layer 62 to form a fourth hole 104 exposing the first redistribution layer 71, as shown in fig. 13;
s50b, forming a third seed layer 92 on the second dielectric layer 62 by vacuum sputtering;
s50c, providing a third photosensitive dry film 93, and attaching the third photosensitive dry film 93 to the third sub-layer 92, referring to fig. 14;
s50d, forming a third through hole and a third patterned hole exposing the third sub-layer 92 to the third through hole on the third photosensitive dry film 93 through exposure and development;
s50e, performing electroplating process, forming fourth conductive pillars 204 in fourth holes 104, and forming third redistribution layer 91 electrically connected to fourth conductive pillars 204 in third patterned holes;
s50f, removing the residual third photosensitive dry film 93;
s50g, providing an etching solution, and performing an etching process on the exposed third sub-layer 92 after the third photosensitive dry film 93 is removed by using the etching solution to remove the third sub-layer 92, referring to fig. 15.
The first seed layer 72, the second seed layer 82 and the third seed layer 92 all include a titanium metal layer and a copper metal layer on the titanium metal layer, the titanium metal layer has high adhesion, excellent conductivity and uniform thickness, and the copper metal layer can be stably adhered to the surfaces of the first dielectric layer 61, the second dielectric layer 62 and the plastic package layer 4 through the titanium metal layer.
Of course, the first seed layer 72, the second seed layer 82, and the third seed layer 92 in this embodiment are not limited to a two-layer structure (titanium metal layer, copper metal layer), and may be a single-layer structure, a two-layer structure, or a multilayer structure having two or more layers. The materials of the first seed layer 72, the second seed layer 82, and the third seed layer 92 are not limited to two single metal materials, and may also be a single metal material or an alloy material, so that the redistribution layer can be stably attached to the corresponding dielectric layer or plastic package layer 4, and details are not repeated.
The first redistribution layer 71 and the third redistribution layer 91 in this embodiment are used for connecting an I/O interface of the ASIC chip 2 to one ends of the first conductive pillar 201 and the resistor 5 through the third conductive pillar 203 and the first redistribution layer 71, respectively, the other end of the resistor 5 is connected to one side of the capacitor 3 through the first redistribution layer 71 and the third conductive pillar 203, the other side of the capacitor 3 is connected to the second conductive pillar 202, and the sensor chip 10 is connected to the ASIC chip 2 through the third redistribution layer 91, the fourth conductive pillar 204, the first redistribution layer 71, and the third conductive pillar 203.
Specifically, step S50 further includes a process of opening the plastic layer 4, the first dielectric layer 61, and the second dielectric layer 62 to form a sound hole 105 for transmitting sound below the sensor chip 10.
Specifically, in step S60, a metal frame 12 is further provided, the metal frame 12 is pasted on the second dielectric layer 62, and the sensor chip 10 and the third redistribution layer 91 are both located in the metal frame 12, referring to fig. 17.
Preferably, the capacitor 3 in this embodiment is a thick film capacitor, and the resistor 5 is a thin film resistor.
Optionally, the first dielectric layer 61 and the second dielectric layer 62 in this embodiment are both made of ABF (Ajinomoto structured-up Film), PI, EMC, photoresist, or PP (Polypropylene), and are attached to the first surface 41 of the plastic package layer 4 to play a role of insulation.
Specifically, the first hole site 101, the second hole site 102, the third hole site 103 and the fourth hole site 104 are formed by communicating tapered holes with adjacent upper and lower small hole ends.
Optionally, the material of the first conductive pillar 201, the second conductive pillar 202, the third conductive pillar 203, and the fourth conductive pillar 204 in this embodiment is Cu, Ag, or Au.
Alternatively, the first rewiring layer 71, the second rewiring layer 81, and the third rewiring layer 91 of the present embodiment may be a multilayer structure of one layer, two layers, or more than two layers, as necessary.
Optionally, the etching solution is selected from inorganic acid, organic acid, or a mixed solution of organic acid and hydrogen peroxide.
Preferably, the etching solution is a combination of an organic acid, an inorganic acid and hydrogen peroxide.
Specifically, as shown in fig. 17, the I/O interface of the sensor chip 10 in this embodiment is disposed upward, and a metal bump is formed at the I/O interface of the sensor chip 10 by using a tin solder, a silver solder, or a gold-tin alloy solder, and the metal bump is electrically connected to the third redistribution layer 91 by a welding method, which has high stability and reliability.
Alternatively, the sensor chip 10 in this embodiment may employ a MEMS chip or a radio frequency chip.
Example two:
the manufacturing method of the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate in the embodiment is basically the same as that of the embodiment, and the difference is the connection mode of the sensor chip 10 and the third redistribution layer 91.
As shown in fig. 18, the sensor chip 10 in the present embodiment is directly adhered to the second dielectric layer 62, and the I/O interface of the sensor chip 10 is disposed upward and electrically connected to the third redistribution layer 91 through a wire.
It should be understood that the above-described embodiments are merely preferred embodiments of the invention and the technical principles applied thereto. It will be understood by those skilled in the art that various modifications, equivalents, changes, and the like can be made to the present invention. However, such variations are within the scope of the invention as long as they do not depart from the spirit of the invention. In addition, certain terms used in the specification and claims of the present application are not limiting, but are used merely for convenience of description.

Claims (10)

1. A preparation method of a low-thickness packaging structure of a pre-embedded chip of a large board-level fan-out substrate is characterized by comprising the following steps:
s10, providing a carrier plate, an ASIC chip and a capacitor, packaging the ASIC chip and the capacitor on one surface of the carrier plate at intervals by adopting a plastic package layer, and enabling an I/O interface of the ASIC chip to face to one side adjacent to the carrier plate;
s20, removing the carrier plate, providing a resistor, manufacturing a first dielectric layer on the first surface of the plastic packaging layer, and adhering the resistor on the first dielectric layer;
s30, performing hole opening processing on the plastic package layer and the first dielectric layer, manufacturing a first rewiring layer on the first dielectric layer, wherein the first rewiring layer is electrically connected with an I/O interface of the ASIC chip, one side of the capacitor and two ends of the resistor respectively, and manufacturing a second rewiring layer on the second surface of the plastic package layer, and the second rewiring layer is electrically connected with the first rewiring layer and the other side of the capacitor respectively;
s40, forming a second dielectric layer on the first redistribution layer, the second dielectric layer covering the first redistribution layer and the first dielectric layer exposed from the first redistribution layer;
s50, carrying out opening processing on the second dielectric layer, and manufacturing a third rewiring layer connected with the first rewiring layer on the second dielectric layer;
and S60, providing a sensor chip, and electrically connecting the I/O interface of the sensor chip with the second rewiring layer.
2. The method for preparing the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate according to claim 1, wherein the step S30 specifically comprises:
s30a, opening holes in the plastic package layer and the first dielectric layer to form a first hole site penetrating through the plastic package layer and the first dielectric layer, a second hole site exposing one side of the capacitor and a third hole site exposing the I/O interface of the ASIC chip and the other side of the capacitor;
s30b, forming a first seed layer on the first dielectric layer through vacuum sputtering, and forming a second seed layer on the second surface of the plastic packaging layer;
s30c, providing a first photosensitive dry film and a second photosensitive dry film, and attaching the first photosensitive dry film to the first seed layer and the second photosensitive dry film to the second seed layer;
s30d, forming a first via hole and a first patterned hole exposing the first seed layer to the first via hole on the first photosensitive dry film, and forming a second via hole and a second patterned hole exposing the second seed layer to the second via hole on the second photosensitive dry film through exposure and development processes;
and S30e, performing electroplating treatment, forming a first conductive column in the first hole site, forming a second conductive column electrically connected with the capacitor in the second hole site, forming a third conductive column in the third hole site, forming a first redistribution layer electrically connected with the I/O interface of the ASIC chip, one side of the capacitor, two ends of the resistor and one end of the first conductive column in the first patterned hole, and forming a second redistribution layer electrically connected with the other end of the first conductive column and the other side of the capacitor in the second patterned hole.
3. The method for preparing the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate as claimed in claim 2, wherein the step between the step S30 and the step S40 further comprises the following steps:
s30f, removing the residual first photosensitive dry film and the second photosensitive dry film;
and S30g, providing an etching solution, and performing etching treatment on the exposed first seed layer after the first photosensitive dry film is removed and the exposed second seed layer after the second photosensitive dry film is removed by using the etching solution to remove the first seed layer and the second seed layer.
4. The method for preparing the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate according to claim 3, wherein the step S50 specifically comprises:
s50a, carrying out opening processing on the second dielectric layer to form a fourth hole position for exposing the first rewiring layer;
s50b, forming a third sub-layer on the second dielectric layer through vacuum sputtering;
s50c, providing a third photosensitive dry film, and attaching the third photosensitive dry film to the third sublayer;
s50d, forming a third through hole and a third patterned hole exposing the third sub-layer to the third through hole on the third photosensitive dry film through exposure and development;
and S50e, performing electroplating treatment, forming a fourth conductive pillar in the fourth hole, and forming a third redistribution layer electrically connected with the fourth conductive pillar in the third patterned hole.
5. The method for preparing the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate as claimed in claim 4, wherein the step between the step S50 and the step S60 further comprises the following steps:
s50f, removing the residual third photosensitive dry film;
and S50g, providing an etching solution, and etching the exposed third sub-layer after the third photosensitive dry film is removed by using the etching solution to remove the third sub-layer.
6. The method for preparing the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate according to claim 5, wherein the step S10 specifically comprises:
s10a, providing a carrier plate and bonding glue, and attaching the bonding glue to one surface of the carrier plate;
s10b, providing an ASIC chip and a capacitor, attaching the ASIC chip and the capacitor on the bonding glue at intervals, and enabling an I/O interface of the ASIC chip to face to one side adjacent to the bonding glue;
s10c, carrying out plastic package on the ASIC chip and the capacitor to form a plastic package layer for coating the ASIC chip and the capacitor.
7. The method for manufacturing the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate as claimed in any one of claims 1 to 6, wherein the step S50 further comprises a step of opening holes in the plastic packaging layer, the first dielectric layer and the second dielectric layer to form sound holes for transmitting sound below the sensor chip.
8. The method for manufacturing the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate according to any one of claims 1 to 6, wherein in the step S60, the sensor chip uses tin solder, silver solder or gold-tin alloy solder to form a metal bump at an I/O interface, and the metal bump is electrically connected with the third redistribution layer.
9. The method for manufacturing the low-thickness packaging structure of the embedded chip of the large board-level fan-out substrate as claimed in any one of claims 1 to 6, wherein in step S60, a metal frame is further provided, the metal frame is adhered to the second dielectric layer, and the sensor chip and the third redistribution layer are both located in the metal frame.
10. The preparation method of the low-thickness packaging structure of the embedded chip of the large-board-level fan-out substrate as claimed in claim 3 or 5, wherein the etching solution is selected from inorganic acid, organic acid or a mixed solution of organic acid and hydrogen peroxide.
CN202110608800.1A 2021-06-01 2021-06-01 Preparation method of low-thickness packaging structure of embedded chip of large-board-level fan-out substrate Withdrawn CN113517270A (en)

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CN114334947A (en) * 2021-12-09 2022-04-12 江苏长电科技股份有限公司 A kind of packaging structure and preparation method thereof
CN114664771A (en) * 2022-02-14 2022-06-24 致瞻科技(上海)有限公司 Novel semiconductor capacitor packaging structure and packaging method thereof
CN114695130A (en) * 2022-03-24 2022-07-01 广东佛智芯微电子技术研究有限公司 Fan-out type packaging substrate structure based on separable copper foil carrier plate and preparation method thereof
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Publication number Priority date Publication date Assignee Title
CN114334947A (en) * 2021-12-09 2022-04-12 江苏长电科技股份有限公司 A kind of packaging structure and preparation method thereof
CN114664771A (en) * 2022-02-14 2022-06-24 致瞻科技(上海)有限公司 Novel semiconductor capacitor packaging structure and packaging method thereof
CN114695130A (en) * 2022-03-24 2022-07-01 广东佛智芯微电子技术研究有限公司 Fan-out type packaging substrate structure based on separable copper foil carrier plate and preparation method thereof
CN115458511A (en) * 2022-09-07 2022-12-09 安徽安努奇科技有限公司 Filter circuit packaging structure and manufacturing method thereof
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CN117116871A (en) * 2023-10-24 2023-11-24 华进半导体封装先导技术研发中心有限公司 Fan-out packaging structure and forming method thereof
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