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CN113517198A - 半导体器件及其制备方法 - Google Patents

半导体器件及其制备方法 Download PDF

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Publication number
CN113517198A
CN113517198A CN202010279566.8A CN202010279566A CN113517198A CN 113517198 A CN113517198 A CN 113517198A CN 202010279566 A CN202010279566 A CN 202010279566A CN 113517198 A CN113517198 A CN 113517198A
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Prior art keywords
dummy
protective layer
layer
opening
semiconductor device
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CN202010279566.8A
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范增焰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202010279566.8A priority Critical patent/CN113517198A/zh
Priority to US17/430,856 priority patent/US12132022B2/en
Priority to PCT/CN2021/079567 priority patent/WO2021203887A1/zh
Publication of CN113517198A publication Critical patent/CN113517198A/zh
Pending legal-status Critical Current

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Abstract

该发明涉及一种半导体器件及其制备方法，所述半导体器件包括：半导体衬底；钝化层，所述钝化层设在所述半导体衬底的上表面；保护层，所述保护层设在所述钝化层的上表面，所述保护层设有虚设开口；虚设凸块，所述虚设凸块部分位于所述虚设开口内且与所述保护层紧密贴合。根据本发明实施例的半导体器件，能够固定虚设凸块，防止虚设凸块脱落。

Description

半导体器件及其制备方法
技术领域
本发明涉及半导体封装领域，具体涉及一种半导体器件以及半导体器件的制备方法。
背景技术
现有技术的半导体封装领域中，尤其是涉及铜柱凸块(Copper pillar bump)在倒装封装(Flip chip)技术领域的应用，在倒装封装工艺之前通常会在待封装芯片的保护层上形成虚设凸块(dummy bump)。其中虚设凸块通过现有工艺特别成型在保护层上，相关技术中虚设凸块由于不具有电连接作用，一般形成在保护层的表面，但由于保护层与虚设凸块的材料不同，比如虚设凸块与保护层的基础为金属与高分子材料之间的结合，结合力不是很强，比较容易出现虚设凸块脱落的问题，而且由于虚设凸块与高分子材料之间的结合力较差，也容易发生断裂，导致半导体器件的结构不牢固。
发明内容
为解决上述技术问题，本发明提供了一种半导体器件，所述半导体器件的结构稳定，虚设凸块不易脱落。
根据本发明实施例的半导体器件包括半导体衬底；钝化层，所述钝化层设在所述半导体衬底的上表面；保护层，所述保护层设在所述钝化层的上表面，所述保护层设有虚设开口；虚设凸块，所述虚设凸块部分位于所述虚设开口内且与所述保护层紧密贴合。
根据本发明实施例的半导体器件，通过在保护层内形成虚设开口，虚设凸块至少部分位于虚设开口内且与保护层紧密贴合，不仅可以增加虚设凸块与保护层的接触面积以提高结合力，而且通过虚设开口也可固定虚设凸块，增强虚设凸块与保护层之间固定连接强度，提高虚设凸块与保护层之间的结合强度，降低虚设凸块脱落的风险。
根据本发明的一些实施例，还包括：至少一个导电凸块，所述半导体衬底上设有导电焊盘，所述钝化层部分覆盖所述导电焊盘，所述导电凸块穿过所述保护层和所述钝化层与所述导电焊盘连接。
根据本发明的一些实施例，所述虚设凸块电镀成型。
根据本发明的一些实施例，所述保护层内形成有与所述虚设开口相通的阻断槽，所述虚设凸块设有阻断部，所述阻断部位于所述阻断槽内。
可选地，所述阻断槽由形成所述虚设开口的部分侧壁朝向远离所述虚设开口的方向凹陷形成。
可选地，所述阻断槽形成为沿所述虚设开口的周向延伸的环形槽。
可选地，所述虚设开口沿上下方向贯穿所述保护层，所述阻断槽形成在所述虚设开口的下端且延伸至所述保护层的下表面。
根据本发明的一些实施例，所述虚设开口贯穿所述保护层，且所述虚设开口的上表面具有第一宽度，所述第一宽度小于所述虚设开口的最大宽度。
根据本发明的一些实施例，所述保护层还覆盖所述钝化层暴露的侧面以及部分覆盖所述导电焊盘。
根据本发明的一些实施例，所述半导体器件还包括：种子层，所述种子层通过溅射形成在所述虚设开口的底部，且位于所述虚设凸块和所述钝化层之间。
本发明还提出了一种半导体器件的制备方法，所述半导体制备方法可用于制备上述实施例的半导体器件。
根据本发明实施例的半导体器件的制备方法，包括以下步骤：提供半导体衬底，所述半导体衬底上表面形成有钝化层；在所述钝化层上形成保护层；对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口；在所述保护层上形成掩膜层，对所述掩膜与所述虚设开口对应的区域进行曝光显影，以形成与虚设开口连通的电镀开口；在所述电镀开口和虚设开口内形成虚设凸块，去除所述掩膜层以显露所述虚设凸块。
可选地，在去除部分所述保护层形成所述虚设开口后，在所述保护层形成所述掩膜层之前，执行以下步骤：在所述保护层的上表面和虚设开口的底部溅射形成种子层，在去除所述掩膜层以显露所述虚设凸块后，执行以下步骤：去除所述保护层上表面形成的种子层。
可选地，所述对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口，包括：采用直射光曝光以形成虚设开口，采用增加侧光曝光以形成阻断槽，所述阻断槽与所述虚设开口相通。
可选地，所述对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口，包括：采用预设掩膜版对所述保护层进行曝光，所述预设掩膜版包括第一区域部和第二区域部，所述第二区域部的透光度大于所述第一区域部的透光度；去除所述第一区域部对应的保护层以形成虚设开口；去除所述第二区域部对应的所述保护层的底部以形成阻断槽，所述阻断槽与所述虚设开口相通。
进一步地，在所述电镀开口和虚设开口内形成虚设凸块，还包括：在所述阻断槽内形成所述虚设凸块的阻断部。
附图说明
图1是根据本发明一个实施例的半导体器件的结构示意图；
图2-图11是根据本发明实施例的半导体器件的制备方法的各步骤的局部剖视图，其中图3是根据本发明一个实施例的半导体器件的制备方法中对保护层进行曝光显影的部分结构的剖视图，图4是根据本发明另一个实施例的半导体器件的制备方法中对保护层进行曝光显影的部分结构的剖视图；
图12是根据发明另一个实施例的半导体器件的结构示意图；
图13是根据发明又一个实施例的半导体器件的结构示意图；
图14是根据本发明一个实施例的半导体器件的制备方法的流程图；
图15是根据本发明另一个实施例的半导体器件的制备方法的流程图。
附图标记：
100：半导体器件；
1：半导体衬底，11：钝化层，12：导电焊盘；
2：保护层，21：虚设开口，22：阻断槽；
3：虚设凸块，31：阻断部；
4：种子层；
5：掩膜版，51：第一区域部:52：第二区域部；
6：导电凸块；
7：掩膜层；71：电镀开口，72：铜柱，73：焊锡接头。
具体实施方式
以下结合附图和具体实施方式对本发明提出的一种半导体器件作进一步详细说明。
如图1所示，根据本发明实施例的半导体器件100可以包括半导体衬底1、钝化层11、保护层2和虚设凸块3。
如图1所示，钝化层11设在半导体衬底1的上表面，具体地，如图1-图11所示，钝化层11形成在半导体衬底1的上方且覆盖半导体衬底1的上表面，保护层2设在钝化层11的上表面且覆盖钝化层11的上表面，保护层2形成有虚设开口21，其中虚设凸块3能够用于与其它部件连接支撑；虚设凸块3部分位于虚设开口21内且与保护层2紧密贴合，即虚设凸块3部分通过虚设开口21伸入保护层2内且虚设开口21的侧壁紧密连接。如图1以及图10-图13所示，虚设凸块3的下端位于虚设开口21内且与虚设开口21的侧壁相连。
由此相比现有技术中虚设凸块3仅设在保护层2的上表面，虚设凸块3与保护层2之间通过金属和高分子材料的结合力连接，本发明中通过将虚设凸块3至少部分位于虚设开口21内且虚设开口21的侧壁紧密连接，不仅可以增加虚设凸块3与保护层2的接触面积以提高结合力，而且通过虚设开口21也可固定虚设凸块3，增强虚设凸块3与保护层2之间固定连接强度，提高虚设凸块3与保护层2之间的结合强度，降低虚设凸块3脱落的风险。
可选地，如图1所示，半导体器件100还包括至少一个导电凸块6，具体地，半导体衬底1上可设有导电焊盘12，导电焊盘12形成在半导体衬底1的上方，其中，导电焊盘12为金属焊盘，例如可以为铝焊盘或者铝铜焊盘，也可以为其它金属材料。半导体衬底1可以是体硅衬底或者绝缘体上硅衬底，也可以使用其它半导体材料，例如，可以是玻璃衬底或者陶瓷衬底等，对此本发明不做特殊限定。
钝化层11部分覆盖导电焊盘12，具体地，如图1-图11所示，钝化层11形成有开口以暴露出导电焊盘12，钝化层11的一部分可以覆盖导电焊盘12的边缘部分。其中对于钝化层11的材料而言，钝化层11可采用氧化硅、氮化硅中的一种或者多种制成，例如，钝化层11可以为单层的氧化硅层，或者钝化层11也可以采用氮化硅层和氮化硅层层叠设置形成。
保护层2上设有开口且暴露出导电焊盘12，其中保护层2可覆盖钝化层11暴露的侧面以及部分覆盖导电焊盘12，如图1所示，保护层2和钝化层11内形成有适于导电凸块6穿过且露出导电焊盘12的开口，保护层2形成开口的一部分覆盖导电焊盘12的边缘。或者，保护层2可覆盖钝化层11的上表面，且保护层2形成开口的边缘侧面与钝化层11形成开口的边缘侧面相平齐。
可选地，保护层2可以由光刻胶形成，例如保护层2可以采用负性光刻胶形成也可以采用正性光刻胶形成，进一步地，保护层2可以为由聚酰亚胺形成的PI层，还可以是聚苯并恶唑(polybenzoxazole，PBO)层、苯并环丁烯(benzocyclobutene，BCB)或由其它合适的聚合物形成。具体地，在钝化层11的上表面可涂布光刻胶以形成保护层2，并采用光刻法通过曝光显影刻蚀等工艺形成开口以露出导电焊盘12。
导电凸块6和虚设凸块3均可以为一个或者多个，优选地，导电凸块6和虚设凸块3分别可以为多个，其中导电凸块6可用于与其它部件电连接，多个导电凸块6间隔开设置，每个导电凸块6依次穿过保护层2的开口和钝化层11的开口与导电焊盘12连接。
多个虚设凸块3间隔开设置，虚设凸块3能够用于与其它部件连接支撑，不具有电连接至其它部件的作用，对于虚设凸块3的设置而言，虚设凸块3可以设在半导体器件100与其它部件连接时应力集中的部位，从而有利于半导体器件100与其它部件的连接结合以提高组合后元件的结构性能。
可选地，虚设凸块3电镀成型，换言之，虚设凸块3通过电镀工艺形成在虚设开口21内，从而使得虚设凸块3与保护层2连接更加紧密，能够进一步地增强虚设凸块3和保护层2连接的稳定性，也有利于虚设凸块3的形成。具体地，可通过光刻法在保护层2上曝光显影形成虚设开口21，并通过在保护层2的上方涂胶形成掩膜层7，然后通过再次曝光显影工艺在掩膜层7形成与虚设开口21对应连通的电镀开口71，通过在电镀开口71和虚设开口21内电镀材料以形成虚设凸块3，电镀工艺后进行去胶工艺露出虚设凸块3以形成半导体器件100。传统方式中导电凸块6和虚设凸块3通常是一步电镀同时形成的，由于虚设凸块6形成的水平位置较高，造成导电凸块6和虚设凸块3两者的高度差较大，与其他部件连接的时候会不平衡，而通过形成阻断部31还能够降低导电凸块6和虚设凸块3的高度差。
可选地，结合图5-图13所示，保护层2内形成有与虚设开口21连通的阻断槽22，虚设凸块3设有阻断部31，阻断部31位于阻断槽22内，通过阻断槽22和阻断部31的配合可在上下方向上固定虚设凸块3，增强虚设凸块3与保护层2之间的上下方向的结合力，防止虚设凸块3从保护层2脱离。具体地，如图3和图4所示，在形成虚设开口21的光刻过程中，可调整光源的强度和方向以在保护层2内形成阻断槽22，在电镀成型虚设凸块3的过程中采用电镀工艺在阻断槽22内形成阻断部31。
在如图1以及图5-图13所示的示例中，阻断槽22可以由形成虚设开口21的部分侧壁朝向远离虚设开口21的方向凹陷形成，具体地，阻断槽22形成在虚设开口21的侧部且与虚设开口21的侧部相连通，虚设凸块3的侧部设有与阻断槽22对应的阻断部31，阻断部31通过电镀成型形成在阻断槽22内，通过阻断槽22和阻断部31的配合可在上下方向上固定虚设凸块3，防止虚设凸块3从保护层2脱离。
进一步地，阻断槽22可以为沿虚设开口21周向延伸的环形槽，阻断部31形成位于环形槽结构匹配的环形形状，如此通过环形的阻断槽22和阻断部31可进一步地提高保护层2和虚设凸块3的结合强度，以进一步地防止虚设凸块3脱落。
可选地，结合图5-图13所示，虚设开口21沿上下方向贯穿保护层2，由此，使得虚设凸块3能够露出保护层2与其它部件连接，也能够进一步地增强虚设凸块3形成在虚设开口21内也能够增强虚设凸块3固定强度。而且结合图3所示，可以在形成在虚设开口21的过程中，通过增加侧光形成阻断槽22，其中侧光接触保护层2底部的钝化层11时发生发射，导致保护层2对应形成阻断槽22的部位被光照射显影后去除，有利于控制光源在光刻过程中形成阻断槽22，形成阻断槽22的方式不限于此。阻断槽22形成在虚设开口21的下端且延伸至保护层2的下表面，即阻断槽22的下端延伸至钝化层11的上表面，这样，阻断部31形成在阻断槽22内，阻断部31位于保护层2的下方，通过保护层2可防止虚设凸块3脱落。
在本发明的一些示例中，如图13所示，虚设开口21贯穿保护层2，且虚设开口21的上表面具有第一宽度，第一宽度小于虚设开口21的最大宽度，也就是说，虚设开口21沿上下方向的纵截面的宽度不同，虚设开口21的上表面在纵截面上的宽度为第一宽度，其中虚设开口21具有最大宽度的位置低于虚设开口21的上表面，由此虚设开口21可形成上窄下宽的结构，从而可防止虚设凸块3从虚设开口21脱落。例如，虚设开口21可形成为圆台状，虚设开口21沿上下方向的纵截面形成为梯形，虚设开口21的宽度在从上至下的方向上逐渐增大。
在本发明的一些示例中，保护层2还覆盖钝化层11暴露的侧面以及部分覆盖导电焊盘12，在本发明的另一些示例中，保护层2可覆盖钝化层11的上表面且与钝化层11暴露出导电焊盘12的侧面相平齐。
可选地，半导体器件100还可以包括种子层4，如图6所示，种子层4通过溅射形成在虚设开口21的底部，且如图11所示最终形成的半导体器件100中种子层4位于虚设凸块3和钝化层11之间，由此，虚设凸块3的底部至少部分可通过种子层4与钝化层11连接，通过种子层4从而可进一步地增强虚设凸块3底部与钝化层11的结合强度，降低脱落风险。
本发明还提出了一种半导体器件100的制备方法，根据本发明实施例的半导体的制备方法可用于制备上述实施例的半导体器件100。
如图2-图15所示，根据本发明实施例的半导体器件100的制备方法，可以包括以下步骤：
S1：提供半导体衬底1，半导体衬底1上表面形成有钝化层11，其中半导体衬底1的上表面还设有导电焊盘12，钝化层11设在导电焊盘12的上方且钝化层11的一部分覆盖导电焊盘12的边缘，钝化层11上形成有开口以露出导电焊盘12，导电凸块6穿过钝化层11与导电焊盘12连接。
S2：如图2所示，在钝化层11上形成保护层2，具体地可在钝化层11的上表面涂布光刻胶以形成保护层2，例如可以采用光刻胶旋涂机在钝化层11上涂布光刻胶。其中对于光刻胶而言，光刻胶可以为正性光刻胶，例如可以为聚酰亚胺光刻胶，聚酰亚胺光刻胶具有突出的耐热性、良好的力学性能、绝缘性和抗蚀性，在钝化层11的上方涂布聚酰亚胺光刻胶，可以起到绝缘、抗蚀、缓冲应力及平坦化的作用，同时PI(聚酰亚胺)层本身具有的防护功能和应力缓冲功能很大程度的提高了产品的结构可靠性，也能够保护芯片表面不受应力破坏，并使芯片表面更加平坦，有利于提高后续电镀工艺的均匀性和结合力。保护层2也可以采用负性光刻胶，根据不同的光刻胶可采用不同的掩膜版5进行图形化工艺。
S3：对保护层2进行曝光显影，去除部分保护层2以形成虚设开口21，具体地，可对保护层2进行曝光显影，去除保护层2对应形成所述虚设开口21的区域的部分以形成虚设开口21。如图3-图5所示，可以在保护层2的上方设置掩膜版5，通过掩膜版5对保护层2进行曝光，并通过显影液对光刻胶进行溶解，以去除保护层2形成虚设开口21部位的部分，从而可在保护层2内形成虚设开口21。
如图5所示，虚设开口21可沿上下方向延伸且贯穿保护层2，如图3所示，在进行曝光过程中，光源对准照射掩膜版5，其中光源发出的光可以包括直射光，即光沿上下方向垂直照射，通过显影后从而可在保护层2形成沿上下方向延伸的虚设开口21。在虚设开口21内可形成虚设凸块3，虚设凸块3通过虚设开口21部分位于保护层2内，从而通过保护层2可固定虚设凸块3，防止虚设凸块3脱落。
可选地，保护层2内还可以形成有阻断槽22，阻断槽22与虚设开口21连通，虚设凸块3形成在阻断槽22和虚设开口21内，虚设凸块3在阻断槽22内设有阻断部31。由此，通过阻断部31和阻断槽22的配合可在上下方向固定虚设凸块3，以进一步地防止虚设凸块3脱落。
对于阻断槽22的形成，可选地，在如图3所示的示例中，在执行对保护层2曝光显影，去除部分保护层2以形成虚设开口21中，可采用正性光刻法进行曝光显影，在曝光时，采用直射光曝光以形成虚设开口21，采用侧光曝光以形成阻断槽22，即在曝光过程中，可通过调整光源(例如UV灯)照射的方向以使得显影后形成虚设开口21和阻断槽22。具体地，如图3所示，照射光可以包括直射光(如图3所示的沿上下方向的光)和侧光，侧光照射在接触底部钝化层11时发生反射，由此使得保护层2的底部形成阻断槽22的部分被光照射，这样在显影后，保护层2形成虚设开口21和阻断槽22的部分通过显影液去胶掏空，从而形成虚设开口21和阻断槽22。
在本发明的另一些示例中，如图4所示，在执行对保护层2曝光显影，去除部分保护层2以形成虚设开口21的步骤中，可采用负性光刻法，在负性光刻中使用的掩膜版5的透光度不同，掩膜版5的与形成虚设开口21位置对应的区域和掩膜版5的形成阻断槽22位置对应的区域的透光度不同，具体地，包括：采用预设掩膜版5对保护层2进行曝光，预设掩膜版5包括第一区域部51和第二区域部52，第二区域部52的透光度大于第二区域部52的透光度，去除第一区域部51对应的保护层2以形成虚设开口21，去除第二区域部52对应的保护层2的底部以形成阻断槽22，阻断槽22与虚设开口21相通。
如图4和图5所示，第一区域部51与形成虚设开口21的位置对应，第二区域部52与形成阻断槽22的位置对应，其中第二区域部52的透光度大于第一区域部51的透光度，这样，在曝光过程中，在到达形成虚设开口21位置和在形成阻断槽22位置的光的强度不同，光通过第二区域部52照射在保护层2上，这样光照在形成阻断槽22的保护层2的部分的强度，相对于掩膜版5未覆盖的保护层2的强度较弱，从而使得到达保护层2形成阻断槽22的部分的光不足以交联，由此在显影后，保护层2形成虚设开口21和阻断槽22位置处被掏空。进一步地在负性光刻法中采用的掩膜版5可使用mesh技术设计，比多将掩模版5的第二区域部52设置为网格状且可由至少两层材料构成。
S4：在所述保护层2上形成掩膜层7，对所述掩膜层7与所述虚设开口21对应的区域进行曝光显影，以形成与虚设开口21连通的电镀开口71；具体地如图7-图9所示，在保护层2内形成虚设开口21后，进行再次涂胶在保护层2的上表面形成掩膜层7，掩膜层7覆盖保护层2的上表面且覆盖虚设开口21，然后通过再次曝光显影在掩膜层7内形成电镀开口71，电镀开口71形成在虚设开口21的上方且与虚设开口21相对应，电镀开口71的横截面与虚设开口21上部的横截面相同，由此电镀开口71和虚设开口21在上下方向上对应连通。
S5：在所述电镀开口71和虚设开口21内形成虚设凸块3；如图9所示，具体地可通过在电镀开口71和虚设开口21内电镀材料以形成与电镀开口71和虚设开口21形状匹配的虚设凸块3。例如，可在电镀开口71和虚设开口21内电镀铜材料以形成铜柱72，并可在铜柱72的上方电镀锡材料以形成焊锡接头73，铜柱72和焊锡接头73共同构成虚设凸块3。进一步地，曝光显影后在形成虚设开口21的侧部可形成阻断槽22，电镀后在阻断槽22内可形成阻断部31，阻断部31形成为虚设凸块3的一部分，通过虚设凸块3与保护层2的结合能够进一步地提高结合强度，防止脱落。
S6：去除掩膜层7以显露所述虚设凸块3；具体地，电镀完成后，采用去交工艺通过去胶液去除保护层2上方用来限定电镀位置的掩膜层7，使得虚设凸块3部分露出，方便与其它部件连接。进一步地，在进行去胶工艺后还可以对虚设凸块3的焊锡接头73进行回流，使得虚设凸块3结构更加稳定，也可以先对虚设凸块3的焊锡接头73进行回流之后再进行去胶工艺。
在本发明的一些具体实施例中，在去除部分保护层2以形成虚设开口21后，在所述保护层2上形成掩膜层7之前，执行以下步骤：S31：在保护层2的上表面和虚设开口21的底部溅射形成种子层4，如图10-图11所示，在去除所述掩膜层以显露所述虚设凸块后，执行以下步骤：S7：去除保护层2上表面形成的种子层4。如图6所示，虚设开口21的底部形成种子层4，种子层4位于虚设凸块3和钝化层11之间，通过形成种子层4从而可加强虚设凸块3和钝化层11的连接强度。其中在去除保护层2上表面形成的种子层4时可采用刻蚀法刻蚀去除种子层4，例如可以采用干法刻蚀也可以采用湿法刻蚀。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (15)

1.一种半导体器件，其特征在于，包括：
半导体衬底；
钝化层，所述钝化层设在所述半导体衬底的上表面；
保护层，所述保护层设在所述钝化层的上表面，所述保护层设有虚设开口；
虚设凸块，所述虚设凸块部分位于所述虚设开口内且与所述保护层紧密贴合。
2.根据权利要求1所述的半导体器件，其特征在于，还包括：至少一个导电凸块，所述半导体衬底上设有导电焊盘，所述钝化层部分覆盖所述导电焊盘，所述导电凸块穿过所述保护层和所述钝化层与所述导电焊盘连接。
3.根据权利要求1所述的半导体器件，其特征在于，所述虚设凸块电镀成型。
4.根据权利要求1所述的半导体器件，其特征在于，所述保护层内形成有与所述虚设开口相通的阻断槽，所述虚设凸块设有阻断部，所述阻断部位于所述阻断槽内。
5.根据权利要求4所述的半导体器件，其特征在于，所述阻断槽由形成所述虚设开口的部分侧壁朝向远离所述虚设开口的方向凹陷形成。
6.根据权利要求4所述的半导体器件，其特征在于，所述阻断槽形成为沿所述虚设开口的周向延伸的环形槽。
7.根据权利要求4所述的半导体器件，其特征在于，所述虚设开口沿上下方向贯穿所述保护层，所述阻断槽形成在所述虚设开口的下端且延伸至所述保护层的下表面。
8.根据权利要求1所述的半导体器件，其特征在于，所述虚设开口贯穿所述保护层，且所述虚设开口的上表面具有第一宽度，所述第一宽度小于所述虚设开口的最大宽度。
9.根据权利要求2所述的半导体器件，其特征在于，所述保护层还覆盖所述钝化层暴露的侧面以及部分覆盖所述导电焊盘。
10.根据权利要求1所述的半导体器件，其特征在于，还包括：种子层，所述种子层溅射形成在所述虚设开口的底部，且位于所述虚设凸块和所述钝化层之间。
11.一种半导体器件的制备方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底上表面形成有钝化层；
在所述钝化层上形成保护层；
对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口；
在所述保护层上形成掩膜层，对所述掩膜层与所述虚设开口对应的区域进行曝光显影，以形成与虚设开口连通的电镀开口；
在所述电镀开口和虚设开口内形成虚设凸块；
去除所述掩膜层以显露所述虚设凸块。
12.根据权利要求11所述的半导体器件的制备方法，其特征在于，在去除部分所述保护层以形成所述虚设开口后，在所述保护层上形成所述掩膜层之前，执行以下步骤：在所述保护层的上表面和所述虚设开口的底部溅射形成种子层；
在去除所述掩膜层以显露所述虚设凸块之后，执行以下步骤：
去除所述保护层上表面形成的种子层。
13.根据权利要求11所述的半导体器件的制备方法，其特征在于，所述对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口，包括：
采用直射光曝光以形成虚设开口，采用增加侧光曝光以形成阻断槽，所述阻断槽与所述虚设开口相通。
14.根据权利要求11所述的半导体器件的制备方法，其特征在于，所述对所述保护层进行曝光显影，去除部分所述保护层以形成虚设开口，包括：
采用预设掩膜版对所述保护层进行曝光，所述预设掩膜版包括第一区域部和第二区域部，所述第二区域部的透光度大于所述第一区域部的透光度；
去除所述第一区域部对应的保护层以形成虚设开口；
去除所述第二区域部对应的所述保护层的底部以形成阻断槽，所述阻断槽与所述虚设开口相通。
15.根据权利要求13或14所述的半导体器件的制备方法，其特征在于，在所述电镀开口和虚设开口内形成虚设凸块，还包括：
在所述阻断槽内形成所述虚设凸块的阻断部。
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