CN113514753A - Method and device for determining relation of wafer failure functions - Google Patents
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Abstract
The embodiment of the invention provides a method and a device for determining the relation of wafer failure functions. The method comprises the steps of obtaining failure functions and positions of a plurality of failure units in a wafer according to a wafer test result of a function test of the wafer; respectively converting the failure functions of the failure units into a plurality of first vectors; determining first data corresponding to the failure units according to the first vectors and the positions of the failure units; and acquiring a first result by utilizing a clustering algorithm according to the plurality of first data, wherein the first result is used for indicating the relation between the wafer failure functions.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a method and a device for determining the relation of wafer failure functions.
Background
In the field of semiconductor integrated circuit manufacturing, the yield of chips is of great importance, and when yield problems occur on a production line, the root cause of the problems needs to be investigated as soon as possible and solved in time so as to protect the 7x24 hours of normal operation of the production line.
Yield analysis engineers (YA: Yield analysis) usually conduct classification investigation based on past experience and subjective judgment when a product has Yield problems, and the past experience often cannot be directly and quickly applied to new on-line products. In the conventional investigation method, yield problems are often investigated by yield analysts in a team, and analysis of causes of different failure functions needs to be performed through a large amount of data analysis and conference discussion, which is time-consuming and labor-consuming.
Disclosure of Invention
Embodiments of the present invention provide a method and an apparatus for determining a relationship between wafer failure functions, which can reduce the time for investigating the cause of a yield accident and the workload required by the analysis work of an analysis engineer, and further improve the efficiency of investigating the cause of a large number of failure functions, compared with the conventional method that relies solely on the deep investigation of yield analysis engineers based on individual failure functions. On the other hand, the subjective experience of an analysis engineer is less relied on, so that the influence of subjective judgment errors and limitations on the investigation result is reduced.
In order to solve the above technical problems, the present invention provides a method for determining a relationship between wafer failure functions, the method including:
according to a test result of the functional test of the wafer, acquiring failure functions and positions of a plurality of failure units in the wafer;
respectively converting the failure functions of the failure units into a plurality of first vectors;
determining first data corresponding to the multiple failure units according to the multiple first vectors and the positions of the multiple failure units;
and acquiring a first result by utilizing a clustering algorithm according to the plurality of first data, wherein the first result is used for indicating the relation between the wafer failure functions.
Preferably, the method further comprises determining a first recommended cause of the number of failed functions based at least on the first result.
Preferably, the method further comprises, based at least on the first result, merging several of the failed functions into a first failed function, which may or may not be included within the several of the failed functions.
Preferably, the obtaining the failure functions and the positions of the plurality of failure units in the wafer according to the test result of the functional test on the wafer includes:
obtaining a wafer map according to a test result of the functional test of the wafer; the wafer diagram shows the failure functions and positions of a plurality of failure units in the wafer, and the failure functions have corresponding failure function numbers;
and acquiring the number of the failure function corresponding to the failure function of the failure units and the positions of the failure units.
Specifically, the converting the failure functions of the failure units into a plurality of first vectors respectively includes converting failure function numbers corresponding to the failure functions of the failure units into a plurality of first vectors respectively based on one-hot coding.
Preferably, the clustering algorithm comprises a k-means clustering algorithm.
Preferably, the failure function includes one of a high frequency failure, a short circuit failure, an I/O pin open failure, or a protection diode circuit open failure.
Preferably, the obtaining the failure functions and the locations of the plurality of failure units in the wafer according to the test results of the functional tests performed on the wafer comprises obtaining the failure functions and the locations of the plurality of failure units in the plurality of wafers according to the test results of the functional tests performed on the plurality of wafers in a plurality of periods and/or batches.
In a second aspect, there is provided an apparatus for determining a relationship of a wafer disabling function, the apparatus comprising:
the failure function acquisition unit is configured to acquire failure functions and positions of a plurality of failure units in the wafer according to a wafer test result of the functional test on the wafer;
a vector conversion unit configured to convert the failure functions of the plurality of failure units into a plurality of first vectors, respectively;
the first data acquisition unit is configured to determine first data corresponding to each of the plurality of failure units according to the plurality of first vectors and the positions of the plurality of failure units;
and the result determining unit is configured to obtain a first result by utilizing a clustering algorithm according to the plurality of first data, wherein the first result is used for indicating the relationship between the wafer failure functions.
In a third aspect, there is provided a computer readable medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform the method of the first, second aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for determining a relationship between wafer failure functions according to an embodiment of the present invention;
FIG. 2 is a schematic view of a wafer provided in accordance with an embodiment of the present invention;
fig. 3 is a structural diagram of an apparatus for determining a relationship between wafer failure functions according to an embodiment of the present invention;
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described above, yield analysis engineers in the field of semiconductor integrated circuit manufacturing analyze yield problems of products, and therefore, there are problems that they rely on past experience and subjective judgment to perform classification and investigation, and that such investigation methods are also time-consuming and labor-consuming.
After the inventor researches the problems, the problems respectively investigated by different yield analysts can be finally determined to be the same problem through a large amount of data analysis and conference discussion, and if the problems can be found to be a problem in an early stage, a large amount of time and labor consumption can be saved. In addition, the yield analyst relies on human eyes to distinguish the yield defect problem (such as small Area Failure GFA) on the wafer (wafer) which has the limitation of being not sensitive enough, and some problems of discontinuity and small Failure Area are discovered to possibly contain the yield Failure problem which is repeated for a long time in a statistical sense afterwards.
In order to solve the above technical problem, the inventors propose a method for determining a relationship between wafer failure functions. Fig. 1 is a flowchart of a method for determining a relationship between wafer failure functions according to an embodiment of the present invention, as shown in fig. 1, the method includes at least:
and 11, acquiring failure functions and positions of a plurality of failure units in the wafer according to a test result of the function test of the wafer.
In the semiconductor integrated circuit manufacturing process, high purity silicon is generally made into cylindrical rods (e.g., 6 inch, 8 inch or 12 inch in diameter), and the silicon rods are cut into extremely thin silicon wafer circles by the integrated circuit manufacturing enterprise by laser, and then circuits and electronic components are formed on the silicon wafer circles by optical and chemical etching methods, so that a large number of semiconductor chips are formed on each silicon wafer, and the processed circular silicon wafers are wafer wafers.
The functional test is performed on the wafer, that is, the functional (mainly electrical) test is performed on all the chips in the wafer. In different embodiments, a number of different functional tests may be performed, for example, one functional test may be to test whether a pad/pad or pin/pin is shorted, and to test whether a short is in the protection diode circuit. The test method may be to apply a current to the circuit and measure the voltage, if it is too low, indicating a short circuit. Another functional test may be to test the I/O pin and open circuit of the protection diode circuit. The test method may be to apply a current to the circuit and measure the voltage, and if the voltage is too high, it indicates an open circuit. The specification is not limited to what kind of functional test is specifically adopted and the specific test mode thereof.
In one embodiment, a wafer map (wafer map) may be obtained according to a test result of a functional test performed on a wafer; the wafer diagram shows the failure functions and positions of a plurality of failure units (chips) in the wafer, and the failure functions have corresponding failure function numbers; and acquiring the number of the failure function corresponding to the failure function of the failure units and the positions of the failure units.
Fig. 2 shows a schematic view of a wafer provided by an embodiment of the present invention. As previously mentioned, semiconductor chips are simply manufactured by various complex physicochemical processes to form circuits on a wafer. Usually, different electrical function tests are performed at the final stage of production to ensure the functionality of the product, and the pattern generated by combining the test results and the shape of the Wafer is the Wafer Map (Wafer Map). In the wafer map, the test results are marked on the positions of the chips by different colors, shapes or codes in units of chips. Therefore, the wafer map provides an important clue for tracing the cause of the abnormal product, and the spatial distribution of the wafer map and the model analysis thereof can be used to find out the cause of the low yield (such as the production machine with problems or the abnormal process steps), and the analysis of the cause of the low yield at present mainly depends on the subjective experience and judgment of the yield analysis engineer, mainly because the conditions for manufacturing the chip are strict and the cost is very high, the cost is too high if the cause of the yield is inferred to be wrong. The present specification does not limit the specific manner of generating the wafer map as long as the failure function and the position of each failure unit (chip) are shown therein.
Generally, a failure unit in a wafer map refers to a chip that fails a functional test, and generally, a failure unit only marks a failure function, which may be, for example, a main failure function or, for example, a failure function that occurs first in a series of functional tests according to a certain flow in different examples. The disabling function may also be of many specific types in different embodiments. For example, in one embodiment, the failure function may include a high frequency failure, a short circuit failure, an I/O pin open failure, or a protection diode circuit open failure.
In the wafer map, the various disabling functions also have their own numbers. For example, in one example, the high frequency failure may be numbered as Bin2, the short circuit failure may be numbered as Bin3, and the I/O pin open failure or protection diode circuit open failure may be numbered as Bin 4. It is understood that different embodiments may have different failure function types and different failure function numbering manners, and the specific types and numbering manners of the failure functions are not limited in this specification.
For production lot chips produced at different times (e.g., production cycles) where yield problems with commonality may also occur, such cross-production cycle/lot problems are often not considered in existing analyses. In order to find possible common problems, the information of the failure functions in the chip generation of different periods and batches can be gathered for analysis. Therefore, in one embodiment, the obtaining of the failure functions and the locations of the plurality of failed units in the wafer may further be performed according to the test results of the functional tests performed on the wafer, including obtaining the failure functions and the locations of the plurality of failed units in the plurality of wafers according to the test results of the functional tests performed on the plurality of wafers in a plurality of periods and/or lots.
And 12, respectively converting the failure functions of the failure units into a plurality of first vectors.
In this step, the first vector may be obtained based on different encoding modes, and in one embodiment, the failure function numbers corresponding to the failure functions of the multiple failure units may be converted into multiple first vectors respectively based on one-hot encoding.
One-Hot coding (One-Hot coding), also known as One-bit-efficient coding, mainly uses an n-bit state register to encode n states, each state being represented by its own independent register bit and only One bit being active at any time. For example, 4 states are encoded, and the one-hot code is 0001,0010,0100,1000.
And step 13, determining first data corresponding to the failure units according to the first vectors and the positions of the failure units.
In this step, the first data includes a first vector indicating the failure function of the failed unit and elements of the position information of the failed unit. In one embodiment, the first data may be represented as:
A＝{F，px，py}
where A is the first data, F is the first vector, and px, py are the location coordinates of the failed unit.
And 14, acquiring a first result by utilizing a clustering algorithm according to the plurality of first data, wherein the first result is used for indicating the relationship among the failure functions of the wafer.
In this step, a cluster calculation is performed on the plurality of first data, and the obtained first results can be used to reveal potential relations among wafer failure functions, which may include various failure functions of chips included in a wafer function test. The clustering algorithm utilized in this step is not limited in this specification. In different embodiments, different clustering algorithms may be employed. For example, in one embodiment, the clustering algorithm may be a k-means clustering algorithm. In another embodiment, it may also be one of a BIRCH algorithm, a cancel algorithm.
As mentioned above, the conventional yield analysis by an analyst (e.g., yield engineer) usually performs a trace analysis according to the failure function itself, so that it often performs a deep analysis on a single function, but such a result may take a lot of time to find out that different failures have similar or identical causes. Through the method provided by the embodiment of the specification, on one hand, an engineer can be helped to find potential relations among a plurality of failure functions at the first time, so that the failure functions can be analyzed together when the failure reasons are analyzed, and the time for finding the reasons of the failure functions can be greatly saved. Thus, according to an embodiment, the method may further comprise determining a first recommended cause of a number of said failed functions based at least on said first result.
The obtained recommended reason is less dependent on the subjective experience of an analysis engineer, so that the negative influence of subjective judgment errors is reduced. Also, in instances such as those described above where failure functions and locations are obtained from wafer maps from multiple production cycles/lots, it is easier to find commonalities in long-term yield issues, helping analysis engineers break through the limitation that recent yield issues are generally easily perceived and long-term yield commonalities are not easily perceived.
In addition, after the potential relationship of each failure function is obtained, a plurality of failure functions which are very close to each other (such as occurrence probability or generation reason) can be combined, so that the number of the failure functions which need to be analyzed by an analysis engineer is reduced, and the efficiency of the analysis work is improved. Thus, according to yet another embodiment, the method may further comprise, based at least on the first result, consolidating a number of the failed functions into a first failed function, which may or may not be included within the number of failed functions. In the example of representing the vector of the failed functions (the first vector) by using the one-hot coding as described above, since the vector dimension of the one-hot coding is equal to the number of categories of the failed functions, after the plurality of failed functions are combined, it can be understood that the total number of categories of the failed functions is reduced, and therefore the dimension of each failed function vector is also reduced.
According to an embodiment of another aspect, a device for determining a relationship between wafer disabling functions is provided, and fig. 3 is a block diagram of the device for determining a relationship between wafer disabling functions according to the embodiment of the present invention. As shown in fig. 3, the apparatus 300 includes:
a failure function acquiring unit 31 configured to acquire failure functions and positions of a plurality of failure units in a wafer according to a wafer test result of a function test performed on the wafer;
a vector conversion unit 32 configured to convert the failure functions of the plurality of failure units into a plurality of first vectors, respectively;
a first data obtaining unit 33 configured to determine, according to the plurality of first vectors and the positions of the plurality of failure units, first data corresponding to each of the plurality of failure units;
the result determining unit 34 is configured to obtain a first result by using a clustering algorithm according to the plurality of first data, where the first result is used for indicating a relationship between wafer failure functions.
According to an embodiment of yet another aspect, there is also provided a computer readable medium comprising a computer program stored thereon, which computer when executed performs the method described above.
The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of determining a relationship of wafer failure functions, the method comprising:
according to a test result of the functional test of the wafer, acquiring failure functions and positions of a plurality of failure units in the wafer;
respectively converting the failure functions of the failure units into a plurality of first vectors;
determining first data corresponding to the multiple failure units according to the multiple first vectors and the positions of the multiple failure units;
and acquiring a first result by utilizing a clustering algorithm according to the plurality of first data, wherein the first result is used for indicating the relation between the failure functions of the wafer.
2. The method of claim 1, further comprising determining a first recommended cause of the number of failed functions based at least on the first result.
3. The method of claim 1, further comprising, based at least on the first result, consolidating a number of the failed functions into a first failed function, which may or may not be included within the number of failed functions.
4. The method of claim 1, wherein obtaining the failure functions and locations of the plurality of failure units in the wafer according to the test results of the functional tests performed on the wafer comprises:
obtaining a wafer map according to a test result of the functional test of the wafer; the wafer diagram shows the failure functions and positions of a plurality of failure units in the wafer, and the failure functions have corresponding failure function numbers;
and acquiring the number of the failure function corresponding to the failure function of the failure units and the positions of the failure units.
5. The method of claim 4, wherein converting the failure functions of the failure units into a plurality of first vectors respectively comprises converting failure function numbers corresponding to the failure functions of the failure units into a plurality of first vectors respectively based on one-hot coding.
6. The method of claim 1, wherein the clustering algorithm comprises a k-means clustering algorithm.
7. The method of claim 1, wherein the failure function comprises a high frequency failure, a short circuit failure, an I/O pin open failure, or a protection diode circuit open failure.
8. The method of claim 1, wherein obtaining the failing functions and locations of the failing units in the wafer based on the results of the functional tests performed on the wafer comprises obtaining the failing functions and locations of the failing units in the plurality of wafers based on the results of the functional tests performed on the plurality of wafers over a plurality of time periods and/or lots.
9. An apparatus for determining a relationship of a wafer failure function, the apparatus comprising:
the failure function acquisition unit is configured to acquire failure functions and positions of a plurality of failure units in the wafer according to a wafer test result of the functional test on the wafer;
a vector conversion unit configured to convert the failure functions of the plurality of failure units into a plurality of first vectors, respectively;
the first data acquisition unit is configured to determine first data corresponding to each of the plurality of failure units according to the plurality of first vectors and the positions of the plurality of failure units;
and the result determining unit is configured to obtain a first result by utilizing a clustering algorithm according to the plurality of first data, wherein the first result is used for indicating the relationship between the wafer failure functions.
10. A computer-readable storage medium, on which a computer program is stored which, when executed in a computer, causes the computer to carry out the method of any one of claims 1-8.
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