CN113506829A - Step gate dielectric layer structure and manufacturing method thereof - Google Patents
Step gate dielectric layer structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 84
- 238000000034 method Methods 0.000 claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000002347 injection Methods 0.000 claims description 19
- 239000007924 injection Substances 0.000 claims description 19
- 238000001459 lithography Methods 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 8
- 230000004913 activation Effects 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229910000070 arsenic hydride Inorganic materials 0.000 claims description 4
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 2
- 239000002245 particle Substances 0.000 abstract description 18
- 230000035515 penetration Effects 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 238000010330 laser marking Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
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Abstract
一种阶梯栅介质层结构及其制造方法，包括N+衬底、N‑外延层、P‑body扩散窗口、N+JFET扩散窗口、栅介质层、栅极多晶硅和栅源隔离层；本发明涉及一种提高MOSFET抗单粒子栅穿能力的阶梯栅介质层结构和制造方法，在单元结构中增加N+JFET区，利用硅中掺杂浓度越高则硅表面热氧生长越快这一理论，按栅介质层
A stepped gate dielectric layer structure and a manufacturing method thereof, comprising an N+ substrate, an N-epitaxial layer, a P-body diffusion window, an N +JFET diffusion window, a gate dielectric layer, a gate polysilicon and a gate-source isolation layer; the invention relates to a gate-source isolation layer. A stepped gate dielectric layer structure and a manufacturing method for improving the resistance to single-particle gate penetration of MOSFET, adding N+JFET region in the unit structure, using the theory that the higher the doping concentration in silicon, the faster the growth of thermal oxygen on the silicon surface, By gate dielectric layer
Description
Technical Field
The invention belongs to the technical field of semiconductor discrete devices, and relates to a step gate dielectric layer structure and a manufacturing method thereof.
Background
The aerospace-grade MOSFET is applied to a space radiation environment, a total dose effect and a Single Event effect can be generated, the Single Event effect mainly comprises two failure mechanisms, namely Single Event Burnout (SEB) and Single Event Gate penetration (SEGR), and the two mechanisms can cause irreversible failure of a device and influence the normal work of the whole system. The main failure mechanism of the single-particle gate penetration is as follows: taking an N-channel MOSFET as an example, when high-energy particles are incident into a device from a gate region of the device, a large number of electron-hole pairs are generated in a gate dielectric and a semiconductor material along a track after the particles are incident, electrons are collected by a drain electrode under the action of an external electric field, holes drift toward a Si/SiO2 interface, charges accumulated at the Si/SiO2 interface induce opposite charges on a gate, an electric field formed by the charges and the induced charges can increase an electric field of the gate dielectric, and when a breakdown voltage of the gate dielectric is reached, a single-particle gate tunneling (SEGR) effect can be initiated.
The commonly adopted single-particle gate penetration reinforcing technology mainly improves the growth quality of a gate dielectric layer and increases the thickness of the gate dielectric layer. The increase of the thickness of the gate dielectric layer can improve the breakdown voltage of the gate dielectric, thereby effectively improving the single-particle gate-through effect of the device, but the increase of the thickness of the gate dielectric is not beneficial to the total dose resistance of the device and is generally controlled in
In the MOSFET deviceEnergy is also limited as a result.
Disclosure of Invention
The present invention is directed to a step gate dielectric structure and a method for fabricating the same to solve the above-mentioned problems.
In order to achieve the purpose, the invention adopts the following technical scheme:
a step gate dielectric layer structure comprises an N + substrate, an N-epitaxial layer, a P-body diffusion window, and an N+JFETThe gate source isolation layer is arranged on the diffusion window; the N-epitaxial layer is arranged on the N + substrate, P-body diffusion windows are respectively arranged on two sides of the N-epitaxial layer, an N + JFET diffusion window is arranged between the two P-body diffusion windows, gate dielectric layers are arranged in the longitudinal direction of the P-body diffusion window and the N + JFET diffusion window, and gate polycrystalline silicon and a gate source isolation layer are sequentially arranged on the gate dielectric layers from bottom to top; the gate dielectric layer is of a stepped structure.
Furthermore, the gate dielectric layer is provided with an active N + diffusion window and a source P + diffusion window, the source N + diffusion window, the source P + diffusion window and the source metal are connected to form a source electrode, the gate metal is connected with the gate polysilicon to form a gate, and the drain metal is connected with the N + substrate to form a drain electrode.
Further, the gate dielectric layer is a gate dielectric layer
Growth process condition, the thickness of the gate dielectric layer is divided into two parts, N+JFETThe thickness of the gate dielectric layer on the diffusion window is
And the thickness of the gate dielectric layer on the P-body diffusion window is
Furthermore, the length of the gate dielectric layer is 4-5 μm.
Further, N+JFETThe diffusion window is arranged between the two P-body diffusion windows, and the length of the diffusion window is 1.2-1.6 mu m; the length of the grid polysilicon is 4-5 mu m, and the thickness is
Furthermore, the length of the source N + diffusion window is 1.2-1.5 μm; the length of the source P + diffusion window is 2-3 mu m; the length of the gate-source isolation layer is 6-7 μm, and the thickness is 0.8-1.2 μm; the size of the N + substrate is 8-10 mu m; the length of the P-body diffusion window is 3.6-4 μm.
Further, a manufacturing method of the step gate dielectric layer structure comprises the following steps:
after P-body injection and diffusion and before gate dielectric layer growth, N+JFETThe injection and annealing process comprises the following specific process manufacturing flows: sacrificial oxide growth → P-body region lithography → P-body implantation → photoresist removal → P-body diffusion → N+JFETArea lithography → N+JFETInject → strip → N+JFETActivating → removing the sacrificial oxide layer; the process manufacturing flow before the growth of the sacrifice oxide layer and after the removal of the sacrifice oxide layer is consistent with the prior flow.
Further, N+JFETThe diffusion window process parameters are as follows: injecting AsH3 as an injection material, with the injection dosage of 1e 15-1.5 e15, the injection energy of 80 Kev-90 Kev, the activation temperature of 850-900 ℃ and the activation time of 10-15 min.
Compared with the prior art, the invention has the following technical effects:
the invention relates to a stepped gate dielectric layer structure for improving the single-particle gate penetration resistance of a MOSFET (metal-oxide-semiconductor field effect transistor) and a manufacturing method thereof
The thickness of the gate dielectric layer on the N + JFET area can be grown to
The thickness of the gate dielectric layer in the P-body channel region is set to
The channel region of the gate dielectric layer with the stepped structure is thin oxygen, so that the total dose performance of the device is not affected; the JFET area is made of thick oxygen, the breakdown voltage of a gate dielectric is improved, and the single-particle-resistant gate penetration capability of the device is further improved.
In actual design and production, aiming at products with different single particle requirements, the gate dielectric layer in the channel region is controlled to be
The gate dielectric layer of the JFET region is controlled at
By adopting the stepped gate dielectric layer structure and the manufacturing method, for the MOSFET with high voltage of 500V, when the gate bias is zero, the single-particle safe voltage can be increased from the previous 45% VDS (225V) to 65% VDS (325V).
Drawings
FIG. 1 is a schematic diagram of a unit cell of the structure of the present invention;
FIG. 2 is a schematic representation of a cell of a prior art structure.
Wherein, 1, N + substrate; an N-epitaxial layer; a P-body diffusion window; an N + JFET diffusion window; 5. a gate dielectric layer; 6. grid polysilicon; 7. a source N + diffusion window; 8. a source P + diffusion window; 9. a gate source isolation layer.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, the present invention discloses a step gate dielectric layer structure for improving the single particle penetration resistance of a MOSFET and a method for manufacturing the same. The basic unit structure of the device is strip-shaped and comprises an N + substrate 1, an N-epitaxial layer 2, a P-body diffusion window 3 and N +JFET A diffusion window 4, a gate dielectric layer 5, a gate polysilicon 6, a source N + diffusion window 7, a source P + diffusion window 8 and a gate source isolation layer 9, wherein an N-epitaxial layer 2 is arranged on an N + substrate 1, the left side and the right side of the N-epitaxial layer 2 are provided with a single cell main junction P-body diffusion window 3 of a device, and the two are arrangedN + is arranged between P-body diffusion windows 3JFET Diffusion window 4, P-body diffusion window 3 and N +JFETA gate dielectric layer 5 is arranged in the longitudinal direction of the diffusion window 4, a gate polycrystalline silicon 6 and a gate source isolation layer 9 are sequentially arranged on the gate dielectric layer 5, an active N + diffusion window 6 and a source P + diffusion window 7 are arranged on the gate dielectric layer, the source N + diffusion window 6, the source P + diffusion window 7 and a source metal are connected to form a source electrode, a gate metal is connected with the gate polycrystalline silicon 6 to form a gate, and a drain metal is connected with the N + substrate 1 to form a drain electrode.
N+JFETThe process manufacturing method of the diffusion window 5 comprises the following steps: adding a step of N + after P-body injection and diffusion and before gate dielectric layer growthJFETThe injection and annealing process comprises the following specific process manufacturing flows: sacrificial oxide growth → P-body region lithography → P-body implantation → photoresist removal → P-body diffusion → N +JFETRegion lithography → N +JFETInject → remove glue → N +JFETAnd the process manufacturing flow before the growth of the sacrifice oxide layer and after the removal of the sacrifice oxide layer is consistent with the conventional flow.
The complete manufacturing process flow comprises the following steps: epitaxial wafer → laser marking → growth of sacrificial oxide layer → field limiting ring lithography → injection of field limiting ring → photoresist removal → annealing of field limiting ring → removal of oxide layer → growth of field oxide → field oxide lithography + etching → photoresist removal → growth of sacrificial oxide layer → P-body region lithography → P-body implantation → photoresist removal → P-body diffusion → N-body implantation+JFETArea lithography → N+JFETInject → strip → N+JFETActivation → removal of sacrificial oxide layer → growth of gate oxide layer → polysilicon deposition → polysilicon doping → polysilicon lithography + etching → photoresist removal → NSD lithography → NSD injection → photoresist removal → PSD lithography → PSD injection → photoresist removal → DP + lithography → DP + injection → photoresist removal → isolation layer deposition → reflow → lead hole lithography + etching → photoresist removal → front side metal aluminum sputtering → aluminum lithography + etching → photoresist removal → deposition of passivation layer → PAD lithography + etching → photoresist removal → alloy → back side thinning → back side metallization → CP testing → warehousing.
N+JFETThe diffusion window 4 is arranged between the two P-body diffusion windows 3, the length is 1.2-1.6 μm, and the technological parameters are as follows: implant material AsH3The implantation dose is 1e 15-1.5 e15,the injection energy is 80 Kev-90 Kev, the activation temperature is 850-900 ℃, and the activation time is 10-15 min.
The gate dielectric layer 5 is of a stepped structure, has a length of 4-5 μm, and is provided with a gate dielectric layer
The growth process condition is that the thickness of the gate dielectric layer 5 is divided into two parts, N +JFETThe thickness of the gate dielectric layer on the diffusion window 4 is
And the thickness of the gate dielectric layer on the P-body diffusion window 3 is
The length of the grid polysilicon 6 is 4-5 mu m, and the thickness is
The source N + diffusion window 7 has a length of 1.2 μm to 1.5. mu.m.
The length of the source P + diffusion window 8 is 2 μm to 3 μm.
The length of the gate-source isolation layer 9 is 6-7 μm, and the thickness is 0.8-1.2 μm.
The cell size, i.e., the size of the N + substrate 1 in fig. 1, is 8 μm to 10 μm.
The length of the P-body diffusion window 3 is 3.6 to 4 μm.
The technical scheme takes an N-channel MOSFET as an example and is suitable for a P-channel MOFET. In order to achieve the above purpose, compared with the prior unit cell structure schematic diagram shown in FIG. 2, the unit cell structure of the present invention has the advantage that N + is added between two P-body diffusion windows 3JFET Diffusion window 4, N +JFETThe implantation material is AsH3And is heavily doped. In the growth process of the gate dielectric layer, N +JFETThe oxidation growth rate on the diffusion window 4 is faster, the P-body area is lightly doped, and the oxidation growth on the P-body diffusion window 3 is normal, so that a step gate dielectric layer structure is formed. N + CJFETA thick gate dielectric layer on the diffusion window 4, and a gate dielectric layerThe breakdown voltage is improved, the single particle resistance of the device is enhanced, and N +JFETThe gate dielectric layer on the P-body channel region between the diffusion window 4 and the source N + diffusion window 7 is of normal process growth thickness, and the total dose resistance of the device is not affected.
FIG. 1 is compared with the prior art, N +JFETThe thickness of the gate dielectric layer on the diffusion window 4 is the same as that of the original structure
Is increased to
The breakdown voltage of the gate dielectric is improved, and the single-particle-resistant gate penetration capability is improved. Taking 200V and 500V products as examples, the statistics of the single-particle-resistant gate penetration test data in the technical scheme compared with the existing scheme are shown in the following table 1.
TABLE 1 comparison of Single particle resistance to Gate punch through
The structure of the invention is realized without additionally adding process equipment, is compatible with the plane process of the prior anti-radiation MOSFET, and only needs to add a step of N after P-body injection and diffusion and before gate dielectric layer growth in the process of manufacturing the process+JFETAnd (5) performing implantation and annealing processes. In the design process, the size and doping concentration of an injection window of the N + JFET are mainly considered to form N+JFETThe diffusion window should just abut the P-body diffusion window. The stepped gate dielectric layer structure obtained by the scheme can effectively improve the single-particle gate penetration resistance of the MOSFET.
Claims (8)
1. A step gate dielectric layer structure is characterized by comprising an N + substrate (1), an N-epitaxial layer (2), a P-body diffusion window (3) and N+JFETThe gate structure comprises a diffusion window (4), a gate dielectric layer (5), gate polysilicon (6) and a gate source isolation layer (9); an N-epitaxial layer (2) is arranged on an N + substrate (1), two sides of the N-epitaxial layer (2) are respectively provided with a P-body diffusion window (3), and the two P-body diffusion windowsAn N + JFET diffusion window (4) is arranged between the diffusion windows (3), a gate dielectric layer (5) is arranged on the P-body diffusion window (3) and the N + JFET diffusion window (4) in the longitudinal direction, and a gate polysilicon (6) and a gate source isolation layer (9) are sequentially arranged on the gate dielectric layer (5) from bottom to top; the gate dielectric layer (5) is of a stepped structure.
2. The step gate dielectric layer structure of claim 1, wherein the gate dielectric layer (5) is provided with an active N + diffusion window (7) and a source P + diffusion window (8), the source N + diffusion window (7), the source P + diffusion window (8) and a source metal are connected to form a source, a gate metal is connected to the gate polysilicon (6) to form a gate, and a drain metal is connected to the N + substrate (1) to form a drain.
3. The step gate dielectric layer structure of claim 1, wherein the gate dielectric layer (5) is a gate dielectric layer
The growth process condition is that the thickness of the gate dielectric layer (5) is divided into two parts, N+JFETThe thickness of the gate dielectric layer on the diffusion window (4) is as follows
And the thickness of the gate dielectric layer on the P-body diffusion window (3) is equal to
4. The step gate dielectric layer structure of claim 1, wherein the gate dielectric layer (5) has a length of 4 μm to 5 μm.
5. The step gate dielectric layer structure of claim 1, wherein N is+JFETThe diffusion window (4) is expanded in two P-bodiesThe length between the scattered windows (3) is 1.2-1.6 mu m; the length of the grid polysilicon (6) is 4-5 mu m, and the thickness is
6. The step gate dielectric layer structure of claim 2, wherein the length of the source N + diffusion window (7) is 1.2 μm to 1.5 μm; the length of the source P + diffusion window (8) is 2-3 mu m; the length of the gate-source isolation layer (9) is 6-7 μm, and the thickness is 0.8-1.2 μm; the size of the N + substrate (1) is 8-10 mu m; the length of the P-body diffusion window (3) is 3.6-4 μm.
7. A method for manufacturing a step gate dielectric layer structure, which is based on any one of claims 1 to 6, and comprises the following steps:
after P-body injection and diffusion and before gate dielectric layer growth, N+JFETThe injection and annealing process comprises the following specific process manufacturing flows: sacrificial oxide growth → P-body region lithography → P-body implantation → photoresist removal → P-body diffusion → N+JFETArea lithography → N+JFETInject → strip → N+JFETActivate → remove the sacrificial oxide layer.
8. The method of claim 7, wherein N is N+JFETThe diffusion window process parameters are as follows: injecting AsH3 as an injection material, with the injection dosage of 1e 15-1.5 e15, the injection energy of 80 Kev-90 Kev, the activation temperature of 850-900 ℃ and the activation time of 10-15 min.
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| CN115148819A (en) * | 2022-06-22 | 2022-10-04 | 中国电子科技集团公司第五十五研究所 | Power MOSFET gate structure and preparation method for resisting single-event gate damage |
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Application publication date: 20211015 |