CN113506801A - Novel metal grid structure and manufacturing method thereof - Google Patents
Novel metal grid structure and manufacturing method thereof Download PDFInfo
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- CN113506801A CN113506801A CN202110718743.2A CN202110718743A CN113506801A CN 113506801 A CN113506801 A CN 113506801A CN 202110718743 A CN202110718743 A CN 202110718743A CN 113506801 A CN113506801 A CN 113506801A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 143
- 239000002184 metal Substances 0.000 title claims abstract description 143
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 105
- 238000000034 method Methods 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 28
- 238000005240 physical vapour deposition Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 24
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 229910010038 TiAl Inorganic materials 0.000 claims description 12
- 238000000231 atomic layer deposition Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 186
- 230000000903 blocking effect Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000008570 general process Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明涉及一种新型金属栅的结构及其制造方法。PMOS具有第一栅极结构，NMOS具有第二栅极结构；第一栅极结构包括第一阻挡层、第一金属层、第二阻挡层、第二金属层、第三阻挡层和金属栅；第二栅极结构包括第一阻挡层、第二阻挡层、第二金属层、第三阻挡层和金属栅；第一栅极结构的第一金属层作为PMOS的第一功函数层；第二栅极结构的第二金属层作为NMOS的第二功函数层；第一功函数层和第二功函数层被第二阻挡层分隔开。本发明通过第二阻挡层分隔开第一功函数层和第二功函数层，从而隔离金属栅以及NMOS的第二金属层对PMOS的第一金属层的影响，进而提高了PMOS阀值电压(Vt)面内均匀性，提高良率。
The invention relates to a structure of a novel metal grid and a manufacturing method thereof. PMOS has a first gate structure, and NMOS has a second gate structure; the first gate structure includes a first barrier layer, a first metal layer, a second barrier layer, a second metal layer, a third barrier layer and a metal gate; The second gate structure includes a first barrier layer, a second barrier layer, a second metal layer, a third barrier layer and a metal gate; the first metal layer of the first gate structure serves as the first work function layer of the PMOS; the second The second metal layer of the gate structure serves as the second work function layer of the NMOS; the first work function layer and the second work function layer are separated by a second barrier layer. In the present invention, the first work function layer and the second work function layer are separated by the second barrier layer, thereby isolating the influence of the metal gate and the second metal layer of the NMOS on the first metal layer of the PMOS, thereby increasing the threshold voltage of the PMOS (Vt) In-plane uniformity for improved yield.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a novel metal gate structure and a manufacturing method thereof.
Background
The HKMG has a High-k insulating layer with a High dielectric constant and a metal gate. The high-k insulating layer manufactured in the HKMG manufacturing process is significant in improving the performance of the transistor regardless of a Gate-first process or a Gate-last process. The High-k technology not only can greatly reduce the leakage current of the grid electrode, but also improves the capacitance of the grid electrode because the equivalent oxide thickness of the High-k insulating layer is thinner. The HKMG contributes to further reducing the critical dimension of the transistor and effectively improving the driving capability of the transistor.
In the conventional HKMG process, the NRG process is used to adjust and control the work functions of the gate metal layers of NMOS and PMOS. In the prior art, the metal material of the work function layer of the NMOS is TiAl, the metal material of the work function layer of the PMOS is TiN, after the NRG process is adopted, TiAl is also formed on TiN, the work function layers of the NMOS and the PMOS are in contact with each other, and the work function layer of the PMOS is a stacked structure of TiN and TiAl. The metal material in the work function layer of the PMOS is removed in the N region by an NRG process to be TiN, so that the PMOS is greatly influenced by TiAl which is a metal material of the work function layer of the NMOS, the barrier layer at the bottom of the metal gate is poor in coverage and even broken due to the difference of the metal height of the work function layer of the NMOS and the metal height of the work function layer of the PMOS, and the aluminum of the metal gate is diffused into the metal of the work function layer of the NMOS, so that the threshold voltage (Vt) of the PMOS is unstable, and the yield is lost.
Disclosure of Invention
The invention provides a novel metal gate structure, wherein a PMOS (P-channel metal oxide semiconductor) has a first gate structure, and an NMOS (N-channel metal oxide semiconductor) has a second gate structure;
the first grid structure comprises a first barrier layer, a first metal layer, a second barrier layer, a second metal layer, a third barrier layer and a metal grid;
the second grid structure comprises a first barrier layer, a second metal layer, a third barrier layer and a metal grid;
the first metal layer of the first grid structure is used as a first work function layer of the PMOS;
the second metal layer of the second grid structure is used as a second work function layer of the NMOS;
the first work function layer and the second work function layer are separated by a second barrier layer.
Furthermore, the first barrier layer is made of TaN, the first metal layer is made of TiN, the second barrier layer is made of TaN, the second metal layer is made of TiAl, and the metal gate is made of aluminum.
Further, the material of the third barrier layer includes TiN and Ti.
The application also provides a manufacturing method of the novel metal gate, which comprises the following steps of forming a first gate structure of a PMOS and a second gate structure of an NMOS:
step one, forming a first barrier layer in a forming area of a PMOS and an NMOS at the same time;
step two, forming a first metal layer in the forming areas of the PMOS and the NMOS at the same time; the first metal layer of the forming area of the PMOS is used as a first work function layer of the PMOS;
removing the first metal layer in the NMOS forming area;
step four, forming a second barrier layer in the forming areas of the PMOS and the NMOS at the same time;
step five, forming a second metal layer in the forming areas of the PMOS and the NMOS at the same time; the second metal layer of the NMOS forming area is used as a second work function layer of the NMOS;
the first work function layer and the second work function layer are separated by a second barrier layer;
step six, forming a third barrier layer in the forming areas of the PMOS and the NMOS at the same time; and
step seven, forming a metal gate; the first grid structure comprises a first barrier layer, a first work function layer, a second barrier layer, a second metal layer, a third barrier layer and a metal grid; the second gate structure comprises a first barrier layer, a second work function layer, a third barrier layer and a metal gate.
Further, the second step specifically comprises: a first metal layer is deposited on the first barrier layer by a physical vapor deposition process.
Further, the third step specifically comprises: and removing the first metal layer of the NMOS forming area by photoetching combined with an etching process.
Further, the step four specifically includes: depositing a second barrier layer over the first metal layer of the PMOS forming region and the first barrier layer of the NMOS forming region by an atomic layer deposition process.
Further, the step five specifically includes: depositing a second metal layer over the second barrier layer of the NMOS formation region by a physical vapor deposition process.
Further, step seven is followed by: and finishing the planarization of the metal gate by a chemical mechanical polishing process.
Furthermore, the material of the first barrier layer is TaN; the first metal layer is made of TiN; the second barrier layer is made of TaN, and the second metal layer is made of TiAl; the material of the metal grid comprises aluminum; the material of the third barrier layer comprises TiN and Ti.
Drawings
Fig. 1 is a schematic structural diagram of a novel metal gate according to an embodiment of the invention.
Fig. 2 is a flow chart of a method for manufacturing a novel metal gate according to an embodiment of the invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In an embodiment of the present invention, a structure of a novel metal gate is provided, and specifically, please refer to fig. 1 for a schematic structural diagram of a novel metal gate according to an embodiment of the present invention. In the novel metal gate structure according to an embodiment of the present invention, the PMOS has a first gate structure, and the NMOS has a second gate structure. The first gate structure includes a first barrier layer 11, a first metal layer 12, a second barrier layer 13, a second metal layer 14, a third barrier layer 15, and a metal gate 16. The second gate structure includes a first barrier layer 11, a second barrier layer 13, a second metal layer 14, a third barrier layer 15, and a metal gate 16. The first metal layer 12 of the first gate structure serves as a first work function layer of the PMOS. The second metal layer of the second gate structure serves as a second work function layer of the NMOS. The second barrier layer 13 separates the first work function layer and the second work function layer. In some embodiments, common processes are used to perform active area patterning, High-k dielectric deposition, sacrificial silicon gate patterning, interlayer dielectric (ILD0) deposition, and the like on the wafer until the sacrificial silicon gate is removed. The first barrier layer 11 is deposited with a predetermined thickness by a general Atomic Layer Deposition (ALD) process. The material of the first barrier layer 11 may be TaN. A first metal layer 12 is deposited over the first barrier layer 11 by general Physical Vapor Deposition (PVD) to a predetermined thickness. The material of the first metal layer 12 may be TiN. And removing the first metal layer 12 in the NMOS area by adopting a photoetching combined etching process. A second barrier layer 13 of a predetermined thickness is deposited by a general Atomic Layer Deposition (ALD) process over the first metal layer 12 of the PMOS region and the first barrier layer 11 of the NMOS region. The material of the second barrier layer 13 may be TaN. A second metal layer 14 is deposited over the second barrier layer 13 by general Physical Vapor Deposition (PVD) to a predetermined thickness. The material of the second metal layer 14 may be TiAl. A third barrier layer 15 is deposited by means of general Physical Vapour Deposition (PVD) over the second metal layer 14. The material of the third barrier layer 15 may comprise TiN and Ti, the TiN layer being deposited by general Physical Vapor Deposition (PVD) on top of the second metal layer 14, and the Ti layer being deposited on the TiN layer. A metal gate 16 is deposited by general Physical Vapour Deposition (PVD) over the third barrier layer 15. The material of the metal grid 16 comprises aluminum.
By adding the second barrier layer 13 between the first work function layer and the second work function layer, the influence of the metal gate and TiAl of the second metal layer of the NMOS on the TiN of the first metal layer of the PMOS is isolated, the in-plane uniformity of the threshold voltage (Vt) of the PMOS is improved, and the yield is improved.
The present application further provides a method for manufacturing a novel metal gate, and in particular, please refer to a flow chart of a method for manufacturing a novel metal gate according to an embodiment of the present invention shown in fig. 2. With reference to fig. 1 and 2, the method for manufacturing a novel metal gate of the present invention employs the following steps to form a first gate structure of a PMOS and a second gate structure of an NMOS.
Step one, forming a first barrier layer 11 in the forming areas of the PMOS and the NMOS at the same time.
Specifically, the first barrier layer 11 is deposited with a predetermined thickness by a general Atomic Layer Deposition (ALD) process. The material of the first barrier layer 11 may be TaN.
Forming a first barrier in the forming area of the PMOS and the NMOS, and completing the processes of active area patterning, High-k dielectric deposition, sacrificial silicon gate patterning, interlayer dielectric (ILD0) deposition and the like on a wafer by adopting a general process until the sacrificial silicon gate is removed and the like before 11.
Step two, forming a first metal layer 12 in the forming areas of the PMOS and the NMOS at the same time; the first metal layer of the formation region of the PMOS serves as a first work function layer of the PMOS.
Specifically, a first metal layer 12 is deposited by general Physical Vapor Deposition (PVD) to a predetermined thickness over the first barrier layer 11. The material of the first metal layer 12 may be TiN.
And step three, removing the first metal layer 12 in the formation region of the NMOS.
Specifically, the first metal layer 12 in the NMOS area is removed by photolithography and etching processes.
And step four, forming a second barrier layer 13 in the forming areas of the PMOS and the NMOS at the same time.
Specifically, a second barrier layer 13 of a predetermined thickness is deposited by a general Atomic Layer Deposition (ALD) process over the first metal layer 12 of the PMOS region and the first barrier layer 11 of the NMOS region. The material of the second barrier layer 13 may be TaN.
Step five, forming a second metal layer 14 in the forming areas of the PMOS and the NMOS at the same time; the second metal layer of the formation region of the NMOS serves as a second work function layer of the NMOS.
Specifically, a second metal layer 14 is deposited over the second barrier layer 13 by general Physical Vapor Deposition (PVD) to a predetermined thickness. The material of the second metal layer 14 may be TiAl.
The first work function layer and the second work function layer are separated by the second barrier layer. By adding the second barrier layer 13 between the first work function layer and the second work function layer, the influence of the metal gate and TiAl of the second metal layer of the NMOS on the TiN of the first metal layer of the PMOS is isolated, the in-plane uniformity of the threshold voltage (Vt) of the PMOS is improved, and the yield is improved.
And step six, forming a third barrier layer 15 in the forming areas of the PMOS and the NMOS at the same time.
In particular, a third barrier layer 15 is deposited by means of general Physical Vapour Deposition (PVD) over the second metal layer 14. The material of the third barrier layer 15 may comprise TiN and Ti, the TiN layer being deposited by general Physical Vapor Deposition (PVD) on top of the second metal layer 14, and the Ti layer being deposited on the TiN layer.
Step seven, forming a metal gate 16; the first gate structure includes the first barrier layer 11, the first work function layer 12, the second barrier layer 13, the second metal layer 14, the third barrier layer 15, and the metal gate 16; the second gate structure includes the first barrier layer 11, the second barrier layer 13, the second work function layer 14, the third barrier layer 15, and the metal gate 16.
In particular, a metal gate 16 is deposited by means of general Physical Vapour Deposition (PVD) over the third barrier layer 15. The material of the metal grid 16 comprises aluminum.
The first gate structure sequentially includes, from bottom to top, the first blocking layer 11, the first work function layer 12, the second blocking layer 13, the second metal layer 14, the third blocking layer 15, and the metal gate 16. The second gate structure is, from bottom to top, the first blocking layer 11, the second blocking layer 13, the second work function layer 14, the third blocking layer 15, and the metal gate 16 in sequence.
After forming the metal gate 16, planarization of the metal gate 16 is also accomplished by a chemical mechanical polishing process. And after the planarization step is completed, the method further comprises the step of continuously completing the contact hole and the whole flow of the later section by adopting a general process.
The above embodiments separate the first work function layer and the second work function layer by adding the second barrier layer. The second barrier layer adopts a high-step coverage Atomic Layer Deposition (ALD) process to deposit TaN 10A, so that the stability of the first work function layer of the PMOS metal gate is ensured, only one ALP process is added, and the method is simple and feasible. The increased thickness of the second barrier layer TaN is small and is expected to have a small effect on the threshold voltage (Vt) of the NMOS.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114300454A (en) * | 2021-12-14 | 2022-04-08 | 上海华力集成电路制造有限公司 | HKMG device metal gate construction method and SRAM device |
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| US20130026578A1 (en) * | 2011-07-28 | 2013-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing the same |
| CN108538837A (en) * | 2018-03-29 | 2018-09-14 | 上海华力集成电路制造有限公司 | Semiconductor devices and forming method thereof |
| US20190252259A1 (en) * | 2018-02-11 | 2019-08-15 | United Microelectronics Corp. | Method for forming semiconductor structure |
| CN112038339A (en) * | 2020-08-25 | 2020-12-04 | 上海华力集成电路制造有限公司 | High dielectric metal gate MOSFET structure and method of making same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130026578A1 (en) * | 2011-07-28 | 2013-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing the same |
| US20190252259A1 (en) * | 2018-02-11 | 2019-08-15 | United Microelectronics Corp. | Method for forming semiconductor structure |
| CN108538837A (en) * | 2018-03-29 | 2018-09-14 | 上海华力集成电路制造有限公司 | Semiconductor devices and forming method thereof |
| CN112038339A (en) * | 2020-08-25 | 2020-12-04 | 上海华力集成电路制造有限公司 | High dielectric metal gate MOSFET structure and method of making same |
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