CN113505554B - Aging pre-calibration method and system - Google Patents
Aging pre-calibration method and system Download PDFInfo
- Publication number
- CN113505554B CN113505554B CN202110758800.XA CN202110758800A CN113505554B CN 113505554 B CN113505554 B CN 113505554B CN 202110758800 A CN202110758800 A CN 202110758800A CN 113505554 B CN113505554 B CN 113505554B
- Authority
- CN
- China
- Prior art keywords
- calibration
- time sequence
- data
- layout
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3315—Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/337—Design optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/396—Clock trees
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Architecture (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
In order to solve the defects in the prior art, the invention provides an aging pre-calibration method and system, comprising the following steps: constructing a database by design data; taking the data in the database as input, and performing time sequence pre-calibration to obtain predicted data; comparing the predicted data with the data in the database to obtain an extracted scaling factor; and setting the extracted scaling factor into the P & R tool to perform incremental optimization, thereby completing time sequence pre-calibration. The method starts to perform time sequence calibration from the layout stage, so that the probability of time sequence convergence failure caused by small improvement space of the signing stage is effectively reduced; in addition, the consistency of the results of the P & R tool and the Signoff tool STA is enhanced by modifying the extracted scaling factors of the capacitor and the resistor, the negative influence on the area and the power consumption caused by over constraint can be reduced, and the number of ECO iterations is greatly reduced.
Description
Technical Field
The present invention relates to the field of integrated circuit design automation EDA technology, and in particular, to a method, a system, an application, an electronic device, and a computer readable storage medium for pre-calibrating time sequences of a layout and wiring tool for predicting capacitance and resistance by using a machine learning method.
Background
The back-end design of a chip is a physical implementation process of the chip, namely: the gate-level netlist provided by the front-end designer forms a layout file for the process manufacturer to flow through the back-end design. The back-end design flow is largely divided into floorplan, clock tree synthesis, wiring, implemented by a place and route (P & R) tool, and timing verification, accomplished by a verification (Signoff) tool.
Static Timing Analysis (STA) is an important step in back-end design, starting from the layout stage of the process, in each of which the EDA tool invokes the STA engine to perform timing analysis. If no violations occur as a result of the STA of the final Signoff tool, the design is considered to work properly at the clock frequency required by the designer.
The difference in model accuracy of the extraction of parasitic parameters of capacitance and resistance used by the P & R tool and the Signoff tool can cause a large difference in STA results of the two tools, and the STA results of the general P & R tool are optimistic compared with those of the Signoff tool. When a timing violation exists in the Signoff tool, the design needs to be iterated through the Engineering Change Order (ECO) technique back to the P & R tool, modified and optimized until the Signoff tool STA results in timing convergence. The consistency of the results of the P & R tool and Signoff tool STA greatly affects the workload of timing closure, and the back-end design typically consumes 60% of the design cycle on timing closure.
Currently, there are two main approaches to cope with the inconsistency problem existing in the results of P & R tools and Signoff tools STA: the first scheme is to reserve more timing margin in the P & R tool; the second scheme is as follows, chip back end design and layout design method, tool, chip and storage medium, application number: 202010820385.1, in: firstly, completing one-time layout and time sequence checking, comparing time sequence reports generated by two tools, correcting physical information of the P & R tools, and carrying out layout and wiring again.
The first solution is equivalent to accelerating the working frequency of design, and is easy to cause unnecessary voltage threshold replacement and driving replacement for the gate level unit, has negative influence on the power consumption and the area of design, and is not beneficial to improving the design quality; the second method requires a first layout and wiring and then a return modification, and usually requires multiple attempts to obtain a good calibration effect.
Therefore, a method for rapidly adjusting the consistency of static time sequence analysis between a P & R tool and a Signoff tool is sought, so that the design quality is improved, the development period is reduced, and the method is a problem which needs to be solved urgently in the current chip back-end design.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides an aging pre-calibration method and system, which are used for at least solving one technical problem in the background art.
The technical scheme adopted by the invention is as follows:
An aging pre-calibration method comprising:
constructing a database by design data;
Taking the data in the database as input, and performing time sequence pre-calibration to obtain predicted data; comparing the predicted data with the data in the database to obtain an extracted scaling factor;
and setting the extracted scaling factor into the P & R tool to perform incremental optimization, thereby completing time sequence pre-calibration.
The "taking the data in the database as input, perform timing pre-calibration" includes:
A step of performing layout timing pre-calibration and/or a step of performing wiring timing pre-calibration.
The step of pre-calibrating the layout time sequence comprises the following steps:
Carrying out layout planning;
Carrying out layout time sequence pre-calibration on the layout plan to obtain layout prediction data;
comparing the layout prediction data with designed layout data to obtain a layout extraction scaling factor;
And extracting a scaling factor according to the layout to perform layout increment optimization, and completing the step of pre-calibrating the layout time sequence.
The step of wiring timing pre-calibration includes:
after the step of pre-calibrating the layout time sequence, clock tree synthesis is carried out, and wiring is carried out;
carrying out wiring time sequence pre-calibration on the wiring process to obtain wiring prediction data;
comparing the wiring prediction data with designed wiring data to obtain wiring extraction scaling factors;
And performing wiring increment optimization according to the wiring extraction scaling factor to complete the step of pre-calibrating the layout time sequence.
The "set the extracted scaling factor into the P & R tool for incremental optimization," after that, includes: checking the sequence checking stage:
Obtaining data of a time sequence signing and checking stage through the time sequence pre-calibration;
and if the data in the time sequence checking stage has time sequence violations, performing ECO operation.
An application of the aging pre-calibration method in the time sequence pre-calibration direction of a layout wiring tool for capacitors and resistors.
A pre-calibration system for predicting the timing age of a capacitance, resistance layout wiring tool, comprising:
A control module;
The data acquisition module is connected with the external P & R tool and is used for extracting design data in the P & R tool;
The control module is connected with the module and used for carrying out time sequence pre-calibration according to the design data.
The control module comprises:
the time sequence pre-calibration module is connected with the data acquisition module and used for predicting according to the design data of the data acquisition module to obtain capacitance and resistance values of a time sequence checking stage;
the scaling factor calculation module is connected with the data acquisition module and the time sequence pre-calibration module and is used for comparing the corresponding design data with the capacitance and resistance values to obtain capacitance and resistance extraction scaling factors;
and the scaling factor calculation module is used for carrying out data exchange with the P & R tool and optimizing the scaling factor in the P & R tool.
An aging pre-calibration electronic device, comprising:
a storage medium storing a computer program;
and the processing unit is used for carrying out data exchange with the storage medium, and executing the computer program by the processing unit when carrying out pre-calibration on time sequence aging of the layout and wiring tool of the capacitor and the resistor, so as to carry out the steps of the aging pre-calibration method.
A computer-readable storage medium, wherein the computer-readable storage medium has a computer program stored therein;
The computer program, when run, performs the steps of the aging pre-calibration method as described above.
The beneficial effects of the invention are as follows:
The method of the invention establishes a database based on a large amount of design data of the same kind of back-end process library, respectively constructs a neural network to be applied to a layout stage and a wiring stage, takes the design data before the optimization of the layout increment and the design data before the optimization of the wiring increment as input, and predicts the total capacitance and the resistance of each node designed in a time sequence checking stage; comparing the total capacitance and resistance of each node before layout increment optimization and wiring increment optimization with the predicted total capacitance and resistance of each node respectively, so as to obtain proper capacitance and resistance extraction scaling factors; and finally, taking the scaling coefficient as constraint setting, feeding back the constraint setting to a P & R tool, completing time sequence calibration, and continuing layout increment optimization or wiring increment optimization operation.
Compared with the prior art, compared with the method which only relies on ECO technology to modify the circuit, the method of the invention increases the operation space of optimizing and improving the design, and effectively reduces the possibility of time sequence convergence failure caused by smaller improvement space in the signing and checking stage; in addition, the consistency of the results of the P & R tool and the Signoff tool STA is enhanced by modifying the extracted scaling factors of the capacitor and the resistor, the negative influence on the area and the power consumption caused by over constraint can be reduced, and the number of ECO iterations is greatly reduced.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
Fig. 2 is a system block diagram of the system of the present invention.
100. A control module; 200. a data acquisition module; 101. a timing pre-calibration module; 102. and a scaling factor calculation module.
Detailed Description
The application is further described below with reference to the accompanying drawings.
The present invention provides an embodiment:
In order to solve the problems in the prior art, as shown in fig. 1, the aging pre-calibration method in this embodiment is applied to the time sequence pre-calibration direction of a layout wiring tool for capacitors and resistors, and the working steps include:
As shown in fig. 1, a timing pre-calibration and extraction factor calculation are added in the conventional back-end design flow, so as to pre-calibrate the capacitor and resistor layout and wiring tool timing.
Wherein, the step of pre-calibrating the layout time sequence comprises the following steps: carrying out layout planning; carrying out layout time sequence pre-calibration on the layout plan to obtain layout prediction data; comparing the layout prediction data with designed layout data to obtain a layout extraction scaling factor; and extracting a scaling factor according to the layout to perform layout increment optimization, and completing the step of pre-calibrating the layout time sequence.
The step of wiring timing pre-calibration includes: after the step of pre-calibrating the layout time sequence, clock tree synthesis is carried out, and wiring is carried out; carrying out wiring time sequence pre-calibration on the wiring process to obtain wiring prediction data; comparing the wiring prediction data with designed wiring data to obtain wiring extraction scaling factors; and performing wiring increment optimization according to the wiring extraction scaling factor to complete the step of pre-calibrating the layout time sequence.
In the scheme of this embodiment, the time sequence pre-calibration is performed after the initial layout and after the initial wiring, and the specific steps of the time sequence pre-calibration are as follows:
1. Extracting relevant design data from the P & R tool;
2. Inputting the extracted design data into a trained time sequence pre-calibration module;
3. the time sequence pre-calibration module predicts and obtains the capacitance and resistance value of the time sequence checking stage;
4. transmitting the predicted capacitance and resistance and the capacitance and resistance extracted by the P & R tool to a scaling factor calculation module, and calculating the capacitance and resistance ratio of the two tools so as to obtain a capacitance and resistance extracted scaling factor;
5. The capacitor and resistor are returned to the P & R tool to finish the extraction factor setting, and the time sequence pre-calibration is finished;
6. after the timing pre-calibration is completed, the timing convergence is generally performed in the timing verification stage, and then the process after the back-end design can be continued. If a timing violation does exist, then an ECO operation is performed, modifying and optimizing the circuit.
When the layout time sequence pre-calibration and the wiring time sequence pre-calibration are carried out, the layout time sequence pre-calibration and the wiring time sequence pre-calibration are realized by the BP neural network, and in an actual engineering project, a large amount of design data are required to be acquired based on a process library used by the current engineering because process libraries used by different projects are possibly different, a data set is established, and then training of a time sequence pre-calibration model is completed; in some cases, the timing pre-calibration model may also be used all the time without changing the process library; in this embodiment, the neural network is used to predict the capacitance and resistance values of the neural network in the checking stage based on the design data before layout optimization and before wiring optimization, so that the time sequence calibration can be performed in the layout stage and the wiring stage, and the calibration is performed without iterating back to the layout or wiring stage after the checking stage is completed, thereby effectively reducing the development period.
Because there is no practical wiring information in the layout stage of the P & R tool, the capacitance and resistance values are estimated according to the minimum distance between two points, so the input characteristic values of the layout time sequence pre-calibration and the wiring time sequence pre-calibration are different, but the output is the predicted value of the capacitance and resistance in the time sequence checking stage.
Preferably, the following lists the input features at the time of the above two timing pre-calibration, respectively, including:
input features of the layout timing pre-calibration module, including but not limited to:
An estimated line resistance;
An estimated line capacitance;
the X-direction distance between the two nodes;
the Y-direction distance between the two nodes;
Line delay;
Number of fan-outs;
overturning time;
delay of the driving gate;
Input features at pre-calibration of wiring timing include, but are not limited to:
a line resistance;
A line capacitance;
A wire length;
Line delay;
Number of fan-outs;
overturning time;
The drive gate is delayed.
In the calculation process of the scaling factor, respectively obtaining proper resistance and capacitance extraction factors by comparing the capacitance and the resistance of the P & R tool, the layout time sequence pre-calibration module and the wiring time sequence pre-calibration module; the comparison methods described herein are: the sum of the resistances or capacitances predicted by the placement timing pre-calibration module or the routing timing pre-calibration module is divided by the sum of the resistances or capacitances extracted by the P & R tool.
The present invention provides another embodiment:
Referring to fig. 2, a pre-calibration system for predicting time-series aging of a capacitance and resistance layout and wiring tool includes: a control module 100 and a data acquisition module 200; the data acquisition module 200 is connected with an external P & R tool and is used for extracting design data in the P & R tool; the control module 100 is connected to the module 200 for performing timing pre-calibration according to the design data.
Preferably, the control module 100 includes: a timing pre-calibration module 101 and a scaling factor calculation module 102; the time sequence pre-calibration module 101 is connected with the data acquisition module 200 and is used for predicting according to design data of the data acquisition module 200 to obtain capacitance and resistance values of a time sequence signing stage; the scaling factor calculation module 102 is connected with the data acquisition module 200 and the time pre-calibration module 101, and is used for comparing the corresponding design data with the capacitance and resistance values to obtain capacitance and resistance extraction scaling factors; the scaling factor calculation module 102 is in data exchange with the P & R tool, and is configured to optimize a scaling factor in the P & R tool.
The invention also discloses an embodiment:
an aging pre-calibration electronic device, comprising: a storage medium and a processing unit; preferably, the storage medium is a mobile hard disk or a storage device such as a hard disk or a USB flash disk; a processing unit, preferably a CPU; the processing unit is in data exchange with said storage medium for executing said computer program by said processing unit when performing the age pre-calibration, performing the steps of the age pre-calibration method as described above.
The CPU described above can execute various appropriate actions and processes according to programs stored in a storage medium. The electronic device further includes peripherals including an input portion such as a keyboard, a mouse, etc., and may also include an output portion such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), etc., and a speaker, etc.; in particular, a process as described in any of fig. 1 may be implemented as a computer software program according to an embodiment of the present disclosure.
The invention also provides an embodiment:
A computer program product comprising a computer program on a computer readable medium, the computer program comprising program code for performing the method as shown in the flowchart of fig. 1. The computer program may be downloaded and installed from a network. The above-described functions defined in the system of the present invention are performed when the computer program is executed by a CPU.
The invention also provides an embodiment:
A computer-readable storage medium having a computer program stored therein; the computer program, when run, performs the steps of the aging pre-calibration method as described above.
In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present invention, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
What needs to be clarified is: the above-mentioned serial numbers appearing in the present invention are merely for description and do not represent the merits and merits of the implementation scenario.
In a word, the invention provides a chip back end design flow combined with time sequence pre-calibration, which utilizes a neural network to respectively predict the capacitance and resistance values of the chip back end design flow in a checking stage based on design data before layout increment optimization and wiring increment optimization, thereby obtaining an extraction factor for time sequence calibration, and carrying out time sequence calibration in advance and once without iterative calibration; in addition, because the invention selects to perform time sequence calibration before particularly time-consuming layout increment optimization and wiring increment optimization, the P & R tool can refer to parasitic parameter information in Signoff stages in the layout and wiring stages, the time sequence analysis accuracy is improved, the design can be correctly optimized, and the cost brought by useless optimization is reduced.
The foregoing disclosure is merely illustrative of some embodiments of the invention, and the invention is not limited thereto, as modifications may be made by those skilled in the art without departing from the scope of the invention.
Claims (6)
1. An aging pre-calibration method, comprising:
constructing a database by design data;
Taking the data in the database as input, and performing time sequence pre-calibration to obtain predicted data; comparing the predicted data with the data in the database to obtain an extracted scaling factor;
Setting the extracted scaling factor into a P & R tool to perform incremental optimization, thereby completing time sequence pre-calibration;
The step of performing time sequence pre-calibration by taking the data in the database as input comprises the following steps:
A step of performing a layout timing pre-calibration and a step of performing a wiring timing pre-calibration;
the step of pre-calibrating the layout time sequence comprises the following steps:
Carrying out layout planning;
Carrying out layout time sequence pre-calibration on the layout plan to obtain layout prediction data;
comparing the layout prediction data with designed layout data to obtain a layout extraction scaling factor;
extracting a scaling factor according to the layout to perform layout increment optimization, and completing the layout time sequence pre-calibration step;
the step of wiring timing pre-calibration includes:
after the step of pre-calibrating the layout time sequence, clock tree synthesis is carried out, and wiring is carried out;
carrying out wiring time sequence pre-calibration on the wiring process to obtain wiring prediction data;
comparing the wiring prediction data with designed wiring data to obtain wiring extraction scaling factors;
And performing wiring increment optimization according to the wiring extraction scaling factor to complete the step of pre-calibrating the layout time sequence.
2. The aging pre-calibration method according to claim 1, wherein said setting the extracted scaling factor into the P & R tool, after incremental optimization, comprises: checking the time sequence signing and checking stage:
Obtaining data of a time sequence signing and checking stage through the time sequence pre-calibration;
and if the data in the time sequence checking stage has time sequence violations, performing ECO operation.
3. Use of an aging pre-calibration method according to any one of claims 1-2 in a capacitor, resistor placement and routing tool timing pre-calibration direction.
4. A pre-calibration system for time-series aging of a layout wiring tool based on predicted capacitance, resistance of an aging pre-calibration method according to any one of claims 1-2, comprising:
A control module;
The data acquisition module is connected with the external P & R tool and is used for extracting design data in the P & R tool;
The control module is connected with the data acquisition module and is used for carrying out time sequence pre-calibration according to the design data;
the control module comprises:
the time sequence pre-calibration module is connected with the data acquisition module and used for predicting according to the design data of the data acquisition module to obtain capacitance and resistance values of a time sequence checking stage;
the scaling factor calculation module is connected with the data acquisition module and the time sequence pre-calibration module and is used for comparing the corresponding design data with the capacitance and resistance values to obtain capacitance and resistance extraction scaling factors;
and the scaling factor calculation module is used for carrying out data exchange with the P & R tool and optimizing the scaling factor in the P & R tool.
5. An aging pre-calibration electronic device, comprising:
a storage medium storing a computer program;
A processing unit, which is used for exchanging data with the storage medium, and executing the computer program by the processing unit when pre-calibrating the time sequence aging of the layout and wiring tool of the capacitor and the resistor, so as to perform the steps of the aging pre-calibration method according to any one of claims 1-2.
6. A computer-readable storage medium, characterized by:
the computer readable storage medium has a computer program stored therein;
The computer program, when run, performs the steps of the aging pre-calibration method according to any one of claims 1-2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110758800.XA CN113505554B (en) | 2021-07-05 | 2021-07-05 | Aging pre-calibration method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110758800.XA CN113505554B (en) | 2021-07-05 | 2021-07-05 | Aging pre-calibration method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113505554A CN113505554A (en) | 2021-10-15 |
| CN113505554B true CN113505554B (en) | 2024-08-16 |
Family
ID=78011307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110758800.XA Active CN113505554B (en) | 2021-07-05 | 2021-07-05 | Aging pre-calibration method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113505554B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108804734A (en) * | 2017-04-28 | 2018-11-13 | 三星电子株式会社 | The method and its system of integrated design circuit |
| CN111950226A (en) * | 2020-08-14 | 2020-11-17 | Oppo广东移动通信有限公司 | Chip back-end design and layout design methods, tools, chips and storage media |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10140407B2 (en) * | 2014-11-26 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method, device and computer program product for integrated circuit layout generation |
| KR102109101B1 (en) * | 2018-06-12 | 2020-05-12 | 연세대학교 산학협력단 | Static timing analysis method and appartus on near threshold voltage region |
| US10691854B1 (en) * | 2018-11-13 | 2020-06-23 | Avatar Integrated Systems, Inc. | Graph-based timing analysis timing calibration |
| CN109783984B (en) * | 2019-02-19 | 2023-02-07 | 中国人民解放军国防科技大学 | Layout and wiring method suitable for increasing CPU core frequency |
| CN111030630B (en) * | 2019-12-06 | 2023-05-05 | 深圳市纽瑞芯科技有限公司 | Circuit and method for calibrating RC time constant on chip by using switched capacitor |
| CN111931454A (en) * | 2020-08-19 | 2020-11-13 | Oppo广东移动通信有限公司 | Chip physical design method and electronic equipment |
-
2021
- 2021-07-05 CN CN202110758800.XA patent/CN113505554B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108804734A (en) * | 2017-04-28 | 2018-11-13 | 三星电子株式会社 | The method and its system of integrated design circuit |
| CN111950226A (en) * | 2020-08-14 | 2020-11-17 | Oppo广东移动通信有限公司 | Chip back-end design and layout design methods, tools, chips and storage media |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113505554A (en) | 2021-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11836641B2 (en) | Machine learning-based prediction of metrics at early-stage circuit design | |
| CN1885295B (en) | Building integrated circuits using logical units | |
| CN101842789B (en) | Method and apparatus for memory abstraction and verification using same | |
| US20110035203A1 (en) | system level power evaluation method | |
| US20050091627A1 (en) | Comparison of two hierarchical netlist to generate change orders for updating an integrated circuit layout | |
| US9589096B1 (en) | Method and apparatus for integrating spice-based timing using sign-off path-based analysis | |
| US8397204B2 (en) | System and methodology for development of a system architecture using optimization parameters | |
| US8713506B2 (en) | System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce dynamic power in an electronic circuit and an apparatus incorporating the same | |
| CN111611766A (en) | Method, apparatus and storage medium for determining circuit layout constraints | |
| US12175176B2 (en) | Fast synthesis of logical circuit design with predictive timing | |
| CN112069763A (en) | How to correct the circuit | |
| CN112651203A (en) | Parameter optimization method and device, server and storage medium | |
| CN113505554B (en) | Aging pre-calibration method and system | |
| CN117371386B (en) | Circuit layout updating method, device, equipment and storage medium | |
| CN117610491A (en) | Chip design method, device, equipment and computer readable storage medium | |
| US12032887B2 (en) | In-graph causality ranking for faults in the design of integrated circuits | |
| US11797739B2 (en) | Endpoint path margin based integrated circuit design using sub-critical timing paths | |
| US8185369B2 (en) | Method and apparatus for characterizing properties of electronic devices depending on device parameters | |
| JP2012168661A (en) | Verification support program, verification support device, and verification support method | |
| US7146301B2 (en) | Efficient production of disjoint multiple traces | |
| US10482206B1 (en) | System, method, and computer program product for providing feedback during formal verification | |
| CN116542196B (en) | Integrated circuit time sequence analysis method, system and medium based on effective clock path | |
| US12190039B1 (en) | Incremental clock tree planning | |
| US20220318475A1 (en) | Library Design and Co-optimization with a Circuit Design | |
| US10755023B1 (en) | Circuit timing analysis |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20240722 Address after: 518000 1104, Building A, Zhiyun Industrial Park, No. 13, Huaxing Road, Henglang Community, Longhua District, Shenzhen, Guangdong Province Applicant after: Shenzhen Hongyue Information Technology Co.,Ltd. Country or region after: China Address before: 510062 Dongfeng East Road, Yuexiu District, Guangzhou, Guangdong 729 Applicant before: GUANGDONG University OF TECHNOLOGY Country or region before: China |
|
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20240723 Address after: 529200 Beimen eighth industrial zone, Fucheng Town, Taishan City, Jiangmen City, Guangdong Province Applicant after: Taishan Lihua Electronics Factory Co.,Ltd. Country or region after: China Address before: 518000 1104, Building A, Zhiyun Industrial Park, No. 13, Huaxing Road, Henglang Community, Longhua District, Shenzhen, Guangdong Province Applicant before: Shenzhen Hongyue Information Technology Co.,Ltd. Country or region before: China |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |