CN113487019A - Circuit fault diagnosis method and device, computer equipment and storage medium - Google Patents

Abstract

The present application relates to a circuit fault diagnosis method, device, computer equipment and storage medium. The method includes: acquiring target test data obtained by testing a circuit to be diagnosed; using a circuit fault diagnosis model obtained by pre-training, performing circuit fault diagnosis on the target test data, and obtaining a circuit fault diagnosis result of the circuit to be diagnosed; The method of obtaining the circuit fault diagnosis model by training includes: acquiring a fault circuit sample set, where the fault circuit sample set includes sample information of each fault circuit, and the circuit fault sample information includes a sample test obtained by testing the fault sample circuit data and sample labels corresponding to each faulty sample circuit; based on the faulty circuit sample set, the fault diagnosis model of the circuit to be trained is trained based on the pigeon flock algorithm to obtain the circuit fault diagnosis model. By adopting the method, the correctness and efficiency of circuit fault diagnosis can be improved.

Description

Circuit fault diagnosis method, device, computer equipment and storage medium

technical field

The present application relates to the field of electronic technology, and in particular, to a circuit fault diagnosis method, device, computer equipment and storage medium.

Background technique

With the continuous advancement of electronic technology and the continuous development of the industry, the integration and complexity of electronic equipment have become higher and higher, especially the electrical equipment containing analog devices. Troubleshooting, repairing and maintaining such equipment is very difficult, exhausting energy and financial resources, but it is an indispensable and important part of ensuring the normal operation of the system. According to the survey, the cost of diagnosis, repair and maintenance of such equipment has exceeded the cost of the equipment. Therefore, in major industrial fields, such as military industry and aerospace, the fault diagnosis and maintenance of such complex equipment has put forward very urgent requirements.

The traditional way of diagnosing circuit faults is to determine whether a circuit fault occurs by monitoring the relevant electrical parameters of the circuit and comparing the monitored electrical parameters with relevant thresholds during the use of the circuit. However, this method of circuit fault diagnosis has poor accuracy.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide a circuit fault diagnosis method, device, computer equipment and storage medium for the above technical problems.

A circuit fault diagnosis method, the method comprising:

Obtain the target test data obtained by testing the circuit to be diagnosed;

Using the circuit fault diagnosis model obtained by pre-training, perform circuit fault diagnosis on the target test data, and obtain the circuit fault diagnosis result of the circuit to be diagnosed;

Wherein, the way of obtaining the circuit fault diagnosis model by training includes:

Obtaining a sample set of faulty circuits, the sample set of faulty circuits includes sample information of each faulty circuit, and the sample information of circuit faults includes sample test data obtained by testing the faulty sample circuits and sample labels corresponding to each of the faulty sample circuits;

Based on the faulty circuit sample set, the fault diagnosis model of the circuit to be trained is trained based on the pigeon flock algorithm, and the circuit fault diagnosis model is obtained.

A circuit fault diagnosis device, the device includes:

A model acquisition module, configured to acquire a circuit fault diagnosis model obtained by pre-training, wherein the circuit fault diagnosis model is obtained by acquiring a faulty circuit sample set, the faulty circuit sample set includes sample information of each faulty circuit, and the circuit fault The sample information includes sample test data obtained by testing the faulty sample circuit and sample labels corresponding to each of the faulty sample circuits; based on the faulty circuit sample set, obtained by training the fault diagnosis model of the circuit to be trained based on the pigeon flock algorithm;

a data acquisition module for acquiring target test data obtained by testing the circuit to be diagnosed;

The diagnosis module is configured to use a circuit fault diagnosis model obtained by pre-training to perform circuit fault diagnosis on the target test data, and obtain a circuit fault diagnosis result of the circuit to be diagnosed.

A computer device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps of the above-mentioned circuit fault diagnosis method are implemented.

A computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the steps of the above-mentioned circuit fault diagnosis method.

The above circuit fault diagnosis method, device, computer equipment and storage medium, for the circuit to be diagnosed, obtain the target test data obtained by testing the circuit to be diagnosed, and use the circuit fault diagnosis model to carry out circuit fault diagnosis, and the circuit fault diagnosis The model is trained based on the pigeon flock algorithm, which greatly improves the correctness and efficiency of circuit fault diagnosis.

Description of drawings

1 is an application environment diagram of a circuit fault diagnosis method in one embodiment;

2 is a schematic flowchart of a circuit fault diagnosis method in one embodiment;

3 is a schematic flowchart of training to obtain a circuit fault diagnosis model in one embodiment;

4 is a schematic flowchart of a circuit fault diagnosis model obtained by training in another embodiment;

Fig. 5 is the model principle schematic diagram of stochastic resonance in an example;

6 is a schematic diagram of a training process in a specific example;

7 is a schematic diagram of a circuit fault diagnosis in a specific example;

FIG. 8 is a schematic flowchart of training to obtain a circuit fault diagnosis model in a specific example;

9 is a structural block diagram of an apparatus for diagnosing circuit faults in one embodiment;

Figure 10 is an internal structure diagram of a computer device in one embodiment;

Figure 11 is a diagram of the internal structure of a computer device in one embodiment.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

The circuit fault diagnosis method provided by the present application can be applied to the application environment shown in FIG. 1 . The circuit 10 to be diagnosed is a target circuit to be used for diagnosing it and diagnosing whether it has a fault. The device 20 is a test device that can be used to test the circuit 10 to be diagnosed to obtain corresponding target test data. The obtained target test data may be transmitted to the computer device 30 by wire, wireless or other means (eg, forwarding by a third party, etc.). Based on the obtained target test data, the computer equipment uses the circuit fault diagnosis model obtained by pre-training to perform circuit fault diagnosis, so as to obtain the circuit fault diagnosis result of the circuit to be diagnosed. The obtained circuit fault diagnosis result may be whether there is a fault in the circuit to be diagnosed, or whether the circuit to be diagnosed is faulty, and if there is a fault, the specific fault type. The above circuit fault diagnosis model can be obtained by training the computer device 30 itself, or it can be obtained by training other devices (such as servers or other training devices), and the computer device 30 can obtain the trained circuit fault diagnosis model from these devices. Among them, the computer device 30 can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices.

In one embodiment, as shown in FIG. 2 , a method for diagnosing circuit faults is provided, which is illustrated by taking the method applied to the computer device 30 in FIG. 1 as an example, including the following steps S201 to S202 .

Step S201: Acquire target test data obtained by testing the circuit to be diagnosed.

The circuit to be diagnosed is a target circuit for diagnosing it, judging whether it has a fault, or judging whether it has a fault and the type of fault that exists in the case of another fault. In some specific examples, the circuit to be diagnosed may specifically be an analog circuit. Specifically, an analog diagnosis may be performed on the circuit to be diagnosed before it is actually measured.

When acquiring the target test data obtained by testing the circuit to be diagnosed, in some embodiments, the target test data may be obtained by testing the circuit to be diagnosed in real time, or the test of the circuit to be diagnosed has been completed in advance to obtain the target test data. For test data, when circuit fault diagnosis is required, the obtained target test data can be directly obtained.

Step S202: Using a circuit fault diagnosis model obtained by pre-training, perform circuit fault diagnosis on the target test data, and obtain a circuit fault diagnosis result of the circuit to be diagnosed.

Specifically, the target test data can be input into the circuit fault diagnosis model obtained by the pre-training, and the circuit fault diagnosis result of the circuit to be diagnosed corresponding to the target test data can be obtained. The obtained circuit fault diagnosis result may be whether there is a fault in the circuit to be diagnosed, or whether the circuit to be diagnosed is faulty, and if there is a fault, the specific fault type. The specific type of circuit fault diagnosis result is related to the trained circuit fault diagnosis model.

The above-mentioned circuit fault diagnosis model can be obtained by training the computer equipment 30 itself, or it can be obtained by training other equipment (such as a server or other training equipment), and the computer equipment 30 can obtain the trained circuit fault diagnosis from these equipments. Model.

Referring to FIG. 3 , in one embodiment, the method for obtaining the circuit fault diagnosis model by training includes the following steps S301 and S302.

Step S301: Obtain a sample set of faulty circuits, where the sample set of faulty circuits includes sample information of each faulty circuit, and the sample information of circuit faults includes sample test data obtained by testing the faulty sample circuits and samples corresponding to each of the faulty sample circuits Label.

In some embodiments, the faulty circuit sample set may include more than one sample subset, wherein one sample subset corresponds to one fault type, and the fault type corresponding to each faulty circuit sample information in one sample subset is the sample subset Set the corresponding fault type.

In one embodiment, the sample set of faulty circuits can be obtained in the following manner:

Corresponding circuit faults are respectively set for each sample circuit, and each fault sample circuit and the fault type corresponding to each fault sample circuit are obtained, and the sample label includes the fault type corresponding to the fault sample circuit;

respectively test each of the faulty sample circuits to obtain sample test data of each of the faulty sample circuits;

Based on the corresponding fault type and sample test data of each of the faulty sample circuits, a sample set of faulty circuits is obtained.

Therefore, the corresponding faults are respectively set for the sample circuits, so that the fault sample circuits of the corresponding fault types can be directly obtained, and on this basis, each fault sample circuit can be tested, and the sample test of each fault sample circuit can be directly obtained. data.

In another embodiment, the faulty circuit sample set may also be obtained directly on the basis of the faulty circuit, which may specifically include:

Test each circuit (ie, faulty sample circuit) that has failed historically, and obtain sample test data of each of the faulty sample circuits;

Based on the corresponding fault type and sample test data of each of the faulty sample circuits, a sample set of faulty circuits is obtained.

In some embodiments, for a faulty sample circuit that has historically failed, since the test data of the circuit may have been obtained by means of testing after the circuit has failed, the data of each circuit (ie, faulty sample circuit) that has historically failed can be directly obtained. Test data, as sample test data for the faulty sample circuit. Then, based on each sample test data and the fault type corresponding to each circuit corresponding to each sample test data, a sample set of faulty circuits is obtained.

Wherein, in the above-mentioned process of testing the circuit, any possible manner may be used, and the result of testing the circuit may include any test data related to the circuit.

In one embodiment, referring to FIG. 4 , after acquiring the faulty circuit sample set, the following steps S3011 to S3013 may be further included.

Step S3011: Perform normalization processing on each of the fault samples.

进行归一化处理，其中，x_ie为第i个样本集的第e中样本，e＝1,2,…,d，x_emax和x_emin分别为第i个样本集中的数据的最大和最小值，

为归一化值。Among them, the normalization processing can be performed in various possible ways. Assuming that the fault circuit sample set is X={x ₁ , x ₂ ,...x _i ,...,x _n }, where _n is the number of sample sets, then pass

Perform normalization processing, where x _ie is the e-th sample in the ith sample set, e=1, 2,...,d, x _emax and x _emin are the maximum and minimum data in the ith sample set, respectively value,

is the normalized value.

Step 2: Perform stochastic resonance processing on each of the normalized fault samples.

The purpose of stochastic resonance is to improve the signal-to-noise ratio of the test data of each sample, so as to reduce the influence of noise.

噪声强度为D，那么随机共振系统的数学模型可以表示为The processing model of stochastic resonance in one embodiment is shown in Figure 5. In stochastic resonance, if the target input signal of the nonlinear system is s(t), during the transmission process, the noise signal is

The noise intensity is D, then the mathematical model of the stochastic resonance system can be expressed as

Among them, _τ is the delay time; δ(t) is the impulse function; U(x) is the system potential function, and its expression is:

where _α and β are both internal parameters of the system.

After combining the above two equations, we can get

By discretizing it, we can get:

对归一化处理后的各所述故障样本进行随机共振处理。so that the combined

Stochastic resonance processing is performed on each of the normalized fault samples.

For convenience of expression, the sample obtained after stochastic resonance can be rewritten as Y={y ₁ ,y ₂ ,...y _i ,...,y _n }, where

Step 3: Perform data dimension reduction processing on each of the fault samples after stochastic resonance processing.

所示的高斯核函数作为核函数，在特征空间中通过式

和式

确定非线性主成分个数，进而提取出非线性主成分。其中K(y_i,y_j)为核函数矩阵；y_i,y_j为样本点；σ为高斯核函数的宽度，f_r(y_j)为

在第r个特征向量方向上的投影，即求得的非线性主成分分量，v_r为样本数据由高维空间向低维空间的投影向量；α_r为核函数矩阵的第r个特征向量。In an embodiment of the present application, data dimensionality reduction processing may be performed based on KPCA data dimensionality reduction. Specifically, the optional

The Gaussian kernel function shown is used as the kernel function in the feature space by the formula

Japanese

Determine the number of nonlinear principal components, and then extract nonlinear principal components. where K(y _i , y _j ) is the kernel function matrix; y _i , y _j are the sample points; σ is the width of the Gaussian kernel function, and f _r (y _j ) is

The projection in the direction of the rth eigenvector, namely the obtained nonlinear principal component, v _r is the projection vector of the sample data from the high-dimensional space to the low-dimensional space; α _r is the rth eigenvector of the kernel function matrix .

Step S302: Based on the faulty circuit sample set, train the fault diagnosis model of the circuit to be trained based on the pigeon flock algorithm to obtain the circuit fault diagnosis model.

The circuit fault diagnosis model to be trained includes an input layer, a hidden layer and an output layer. The pigeon swarm algorithm is a swarm intelligent optimization algorithm designed to simulate the homing behavior of pigeons. It has the characteristics of simple principle, few parameters to be adjusted, and easy to be implemented. advantage. In one embodiment, referring to FIG. 6 , based on the faulty circuit sample set, the circuit fault diagnosis model to be trained is trained based on the pigeon flock algorithm, and the circuit fault diagnosis model is obtained, including the following steps S601 to S609 .

Step S601: Initialize the number of pigeon flocks, and set the maximum number of iterations.

The number of pigeon groups can be randomly generated, or the initial number of pigeon groups can be generated by a specified method. In one embodiment, if the diagnosis target of the circuit fault diagnosis model is only to diagnose whether there is a fault, the number of pigeons to be initialized may be 1. In the case that the diagnosis target of the circuit fault diagnosis model is a specific fault type of the circuit fault , the number of initialized pigeon flocks can be the same as the number of diagnosable fault types. In a specific example, the number of initialized pigeon flocks may be the same as the number of sample subsets in the faulty circuit sample set.

The maximum number of iterations is the maximum number of iterations in the training process of the pigeon flock algorithm. The maximum number of iterations can be set based on the requirements of training efficiency and training accuracy.

Step S602: Initialize the number of neurons in the hidden layer of the hidden layer, and set the search interval of the pigeon.

Wherein, each pigeon corresponds to a set of model parameters of the circuit fault diagnosis model to be trained, and the number of hidden layer neurons that can be initialized in a possible manner.

Step S603: Calculate the space vector dimension of the pigeon group based on the number of input layer neurons in the input layer and the number of neurons in the hidden layer.

In a specific example, the vector space dimension of the pigeon group may be the sum of the product of the number of neurons in the input layer and the number of neurons in the hidden layer and the number of neurons in the hidden layer. Denote the space vector dimension of the pigeon group as SizePop, the number of neurons in the input layer as n _i , and the number of neurons in the hidden layer as L, the space vector dimension of the pigeon group can be calculated by the following formula:

SizePop=L×n _i +L

Step S604: Generate a space vector of each pigeon according to the space vector dimension of the pigeon group, wherein each pigeon corresponds to a set of model parameters of the circuit fault diagnosis model to be trained.

Step S605: Input each sample test data in the faulty circuit sample set into the fault diagnosis model of the circuit to be trained, obtain a sample training result corresponding to each sample test data, and calculate each pigeon based on the sample training result and the corresponding sample label. fitness value.

Step S606: Calculate the training error according to the fitness value of each pigeon.

Step S607: According to the training error, update the global optimal space vector in the space vector of each pigeon, and update the vector space of each pigeon, update the number of iterations, and return to the step of generating the space vector of each pigeon, until the maximum number of iterations is reached.

Step S608: After reaching the maximum number of iterations, update the search range value, if the search range value does not reach the maximum search range value, initialize the number of iterations, and return to initialize the number of hidden layer neurons of the hidden layer, and set the pigeon's Steps to search the range until the maximum search range value is reached.

In a specific example, the maximum search range value is the same as the number of neurons in the hidden layer.

Step S609: When the maximum search range value is reached, determine the circuit fault diagnosis model based on the global optimal space vector.

Based on the above-mentioned embodiments, the following detailed description is given in conjunction with a specific example.

In the analog circuit, according to the order of the circuit simulation in the actual measurement, there are pre-test simulation diagnosis and post-test simulation diagnosis. In order to ensure the stable operation of the analog circuit, the analog diagnosis before the test is more important than the analog diagnosis after the test. The embodiment of the present application relates to the pre-test simulation diagnosis, that is, for the simulation circuit, the fault diagnosis of the simulation circuit is performed before the simulation circuit is actually measured.

Referring to FIG. 7 , the analog circuit fault diagnosis algorithm proposed in the embodiment of the present application firstly uses stochastic resonance and nuclear principal component analysis (KPCA) to process the faulty circuit samples for the faulty circuit samples, and then uses the pigeon colony algorithm (PIO) to process the faulty circuit samples. The parameters of input weights and hidden layer biases of extreme learning machine (ELM) are optimized to obtain a circuit fault diagnosis model. Then, the circuit fault diagnosis model is used as a classification algorithm to classify the faults of the analog circuit to be tested (ie the circuit to be diagnosed).

The process of obtaining the circuit fault diagnosis model proposed in the embodiment of the present application mainly includes two parts: a data acquisition and processing part and an optimized training classification model part. In the data acquisition and processing part, it first obtains a sample of the faulty circuit. Specifically, it can test the faulty circuit that has failed to obtain sample test data, or manually set the corresponding type of fault on the target analog circuit, and set the fault The target analog circuit (ie the faulty sample circuit) is tested to obtain sample test data. In the part of optimizing the training classification model, for the obtained sample test data, data sampling is performed, and fault features are extracted through stochastic resonance and KPCA Kernel Principal Component Analysis (KPCA Kernel Principal Component Analysis), and they are divided into training data and test data. The PIO-ELM is trained with the training data, and the optimal circuit fault diagnosis model is finally obtained. Then, the obtained circuit fault diagnosis model is tested with the test data. If the test passes, the final circuit fault diagnosis model is obtained.

Referring to FIG. 8 , the process of obtaining a circuit fault diagnosis model in one embodiment may be as follows.

进行归一化处理，获得归一化处理后的故障电路样本集，其中_n为样本集个数，x_ie为第i个样本集的第e中样本，e＝1,2,…,d，x_emax和x_emin分别为第i个样本集的样本数据的最大值和最小值，

为对第i个样本集的第e中样本的归一化值。First, for the faulty circuit sample set X={x ₁ , x ₂ ,...x _i ,...,x _n }, by

Perform normalization processing to obtain the normalized fault circuit sample set, where _n is the number of sample sets, x _ie is the e-th sample in the i-th sample set, e=1,2,...,d, x _emax and x _emin are the maximum and minimum values of the sample data of the ith sample set, respectively,

is the normalized value for the e-th sample in the i-th sample set.

Then, for the normalized fault circuit sample set, stochastic resonance processing is performed to enhance the useful input signal and improve the system output signal-to-noise ratio,

来进行随机共振处理。在随机共振中，若随机共振系统的目标输入信号为s(t)，在传输过程中，噪声信号为

噪声强度为D，那么随机共振系统的数学模型可以表示为In an example, one can use

for stochastic resonance processing. In stochastic resonance, if the target input signal of the stochastic resonance system is s(t), during the transmission process, the noise signal is

The noise intensity is D, then the mathematical model of the stochastic resonance system can be expressed as

In formula (1), _τ is the delay time; δ(t) is the impulse function; U(x) is the system potential function, and its expression is:

Among them, _α and β are internal parameters of the system, which can be set according to actual technical needs.

After combining the above two equations, we can get

Discretization gives:

For convenience of expression, the sample obtained after stochastic resonance is rewritten as Y={y ₁ , y ₂ ,...y _i ,...,y _n }, where

所示的高斯核函数作为核函数，在特征空间中通过式

和式

确定非线性主成分个数，进而提取出非线性主成分，从而据此进行数据降维处理，获得数据降维后的样本，以减少后续的计算量。其中K(y_i,y_j)为核函数矩阵；y_i,y_j为样本点；σ为高斯核函数的宽度，f_r(y_j)为

在第r个特征向量方向上的投影，即求得的非线性主成分分量，v_r为样本数据由高维空间向低维空间的投影向量；α_r为核函数矩阵的第r个特征向量。For the samples obtained after stochastic resonance, the formula can be selected

The Gaussian kernel function shown is used as the kernel function in the feature space by the formula

Japanese

Determine the number of nonlinear principal components, and then extract the nonlinear principal components, so as to perform data dimensionality reduction processing accordingly, and obtain samples after data dimensionality reduction, so as to reduce the subsequent calculation amount. where K(y _i , y _j ) is the kernel function matrix; y _i , y _j are the sample points; σ is the width of the Gaussian kernel function, and f _r (y _j ) is

The projection in the direction of the rth eigenvector, namely the obtained nonlinear principal component, v _r is the projection vector of the sample data from the high-dimensional space to the low-dimensional space; α _r is the rth eigenvector of the kernel function matrix .

Set the initial parameters of the pigeon flock algorithm, including: the number of pigeon flocks N, the maximum number of iterations kmax.

Enable the map compass factor and build an extreme learning machine network architecture. When building the extreme learning machine network architecture, the number L of neurons in the hidden layer can be initialized and the search interval can be set.

In order to get the optimal weight W between the input layer and the hidden layer, the space vector dimension SizePop of the pigeon flock can be calculated first:

SizePop=L×n _i +L

Among them, n _i is the number of neurons in the input layer, and L is the number of neurons in the hidden layer;

Then, according to the space vector dimension of the pigeon group, the space vector of each pigeon is generated, wherein each pigeon corresponds to a set of model parameters of the fault diagnosis model of the circuit to be trained, and the individual space vector is searched according to the update of all the pigeon groups:

V _i (k)=V _i (k-1)·e ^-Rk +rand·(Y _best -Y _i (k-1))

_{Yi (k)=Y i (} k-1)+V _i (k)

The position and velocity of each pigeon are represented by Y and V, respectively, where the new velocity of the ith pigeon after k iterations is V _i (k), the position is Y _i (k), and R is between 0 and 1 The map compass factor between; k is the current number of iterations; rand is a random number; Y _best is the global optimal position after k-1 iterations.

计算权重矩阵δ；其中，H是隐藏层节点的输出。T为极限学习机输出层的期望输出矩阵。According to the formula

Calculate the weight matrix δ; where H is the output of the hidden layer node. T is the expected output matrix of the output layer of the extreme learning machine.

g(x) is the activation function. Wi =[ _{wi ,1} ,wi _,2 ,...,wi _,n ] ^T is the weight coefficient between the input layer and the hidden layer, δ _i is the weight between the hidden layer and the output layer coefficient. b _i is the bias coefficient of the ith neuron in the hidden layer. Wi · X _{j represents} the inner product of _{Wi and X j ,} and H is the output of the hidden layer node. T is the expected output matrix of the output layer of the extreme learning machine.

即获得各样本测试数据对应的样本训练结果。Input each sample test data in the faulty circuit sample set into the fault diagnosis model of the circuit to be trained, and calculate the output of the training data through W, b and δ

That is, the sample training results corresponding to each sample test data are obtained.

与T计算训练误差。一个具体示例中，可以用均方差作为训练误差。用公式可表示为：use

Calculate the training error with T. In a specific example, the mean squared error can be used as the training error. The formula can be expressed as:

Update the global optimal space vector.

Update the number of iterations, and determine whether the conditions for jumping out of the iteration are reached. If not, for example, the maximum number of iterations is not reached, update the global optimal space vector in the space vector of each pigeon, and update the vector space of each pigeon, and return The process of inputting each sample test data in the faulty circuit sample set into the fault diagnosis model of the circuit to be trained.

If the condition for jumping out of the iteration is reached, the search range value is updated. If the search range value does not reach the search range value, the number of iterations is initialized, and the number of hidden layer neurons that initialize the hidden layer is returned, and the search range of the pigeon is set. steps until the maximum search range value is reached.

If the maximum search range value is reached, jump out of the pigeon flock algorithm iteration and output W _best and b _best .

计算δ_best。并通过W_best、b_best和δ_best搭建最优极限学习机分类网络模型，搭建的最优极限学习机分类网络模型，记为最终获得的电路故障诊断模型。Then, by the formula Hδ=T and

Calculate delta _best . And build the optimal extreme learning machine classification network model through W _best , b _best and δ _best , and the built optimal extreme learning machine classification network model is recorded as the final obtained circuit fault diagnosis model.

After the above circuit fault diagnosis model is obtained, the circuit fault diagnosis model can be applied to the actual circuit fault diagnosis process, and the circuit fault diagnosis model is used to classify the faults of the analog circuit.

It should be understood that although the steps in the flowcharts involved in the above-mentioned embodiments are sequentially displayed according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in these flowcharts may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution sequence of these steps or stages It is also not necessarily performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of a step or phase within the other steps.

In one embodiment, as shown in FIG. 9, a circuit fault diagnosis device is provided, including:

The model acquisition module 901 is configured to acquire a circuit fault diagnosis model obtained by pre-training, wherein the circuit fault diagnosis model is obtained by acquiring a faulty circuit sample set, the faulty circuit sample set includes sample information of each faulty circuit, and the circuit The fault sample information includes sample test data obtained by testing the faulty sample circuit and sample labels corresponding to each of the faulty sample circuits; based on the faulty circuit sample set, the fault diagnosis model of the circuit to be trained is trained based on the pigeon flock algorithm;

a data acquisition module 902, configured to acquire target test data obtained by testing the circuit to be diagnosed;

The diagnosis module 903 is configured to use a circuit fault diagnosis model obtained by pre-training to perform circuit fault diagnosis on the target test data, and obtain a circuit fault diagnosis result of the circuit to be diagnosed.

For the specific limitations of the circuit fault diagnosis apparatus, reference may be made to the above description of the embodiments of the circuit fault diagnosis method, which will not be repeated here. Each module in the above-mentioned circuit fault diagnosis apparatus may be implemented in whole or in part by software, hardware and combinations thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

In one embodiment, a computer device is provided, and the computer device may be a server, and its internal structure diagram may be as shown in FIG. 10 . The computer device includes a processor, memory, and a network interface connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium, an internal memory. The nonvolatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the execution of the operating system and computer programs in the non-volatile storage medium. The database of the computer equipment is used to store a sample set of faulty circuits. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program implements a circuit fault diagnosis method when executed by the processor.

In one embodiment, a computer device is provided, and the computer device may be a terminal, and its internal structure diagram may be as shown in FIG. 11 . The computer equipment includes a processor, memory, a communication interface, a display screen, and an input device connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium, an internal memory. The nonvolatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the execution of the operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for wired or wireless communication with an external terminal, and the wireless communication can be realized by WIFI, operator network, NFC (Near Field Communication) or other technologies. The computer program implements a circuit fault diagnosis method when executed by the processor. The display screen of the computer equipment may be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment may be a touch layer covered on the display screen, or a button, a trackball or a touchpad set on the shell of the computer equipment , or an external keyboard, trackpad, or mouse.

Those skilled in the art can understand that the structures shown in FIGS. 10 and 11 are only block diagrams of partial structures related to the solution of the present application, and do not constitute a limitation on the computer equipment to which the solution of the present application is applied. A device may include more or fewer components than shown in the figures, or combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, including a memory and a processor, where a computer program is stored in the memory, and when the processor executes the computer program, the processor implements any of the foregoing circuit fault diagnosis methods in any of the embodiments. step.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, implements the steps in any one of the foregoing circuit fault diagnosis methods:

In one embodiment, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the steps in the foregoing method embodiments.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage In the medium, when the computer program is executed, it may include the processes of the above-mentioned method embodiments. Wherein, any reference to memory, storage, database or other media used in the various embodiments provided in this application may include at least one of non-volatile and volatile memory. The non-volatile memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, and the like. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, the RAM may be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM).

The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, all It is considered to be the range described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims (10)

1. A method of diagnosing a circuit fault, the method comprising:

acquiring target test data obtained by testing a circuit to be diagnosed;

performing circuit fault diagnosis on the target test data by adopting a circuit fault diagnosis model obtained by pre-training to obtain a circuit fault diagnosis result of the circuit to be diagnosed;

the method for training to obtain the circuit fault diagnosis model comprises the following steps:

acquiring a fault circuit sample set, wherein the fault circuit sample set comprises each fault circuit sample information, and the circuit fault sample information comprises sample test data obtained by testing a fault sample circuit and a sample label corresponding to each fault sample circuit;

and training a circuit fault diagnosis model to be trained based on the fault circuit sample set and a pigeon group algorithm to obtain the circuit fault diagnosis model.

2. The method of claim 1, wherein obtaining a sample set of fault circuits comprises:

respectively setting corresponding circuit faults for each sample circuit, and obtaining each fault sample circuit and a fault type corresponding to each fault sample circuit, wherein the sample label comprises the fault type corresponding to the fault sample circuit;

respectively testing each fault sample circuit to obtain sample test data of each fault sample circuit;

and obtaining a fault circuit sample set based on the corresponding fault type and sample test data of each fault sample circuit.

3. The method of claim 1, wherein after obtaining the fault circuit sample set, before training a circuit fault diagnosis model to be trained based on a pigeon swarm algorithm based on the fault circuit sample set, further comprising the steps of:

carrying out normalization processing on the test data of each sample;

carrying out stochastic resonance processing on the normalized sample test data;

and performing data dimension reduction treatment on the sample test data subjected to the stochastic resonance treatment.

4. The method of claim 1, wherein the fault circuit sample set includes more than one sample subset, one sample subset corresponds to one fault type, and the fault type corresponding to each fault circuit sample information in one sample subset is the fault type corresponding to the sample subset.

5. The method of claim 1, wherein the circuit fault diagnosis model to be trained comprises an input layer, a hidden layer and an output layer, and based on the fault circuit sample set, training the circuit fault diagnosis model to be trained based on a pigeon-swarm algorithm to obtain the circuit fault diagnosis model comprises:

training a circuit fault diagnosis model to be trained based on a pigeon swarm algorithm to obtain the circuit fault diagnosis model, wherein the training comprises the following steps:

initializing the number of pigeon groups, and setting the maximum iteration times;

initializing the hidden layer neuron number of the hidden layer, and setting a search interval of the pigeon;

calculating the spatial vector dimension of the pigeon group based on the input layer neuron number of the input layer and the hidden layer neuron number;

generating a space vector of each pigeon according to the space vector dimension of the pigeon group, wherein each pigeon corresponds to a group of model parameters of the circuit fault diagnosis model to be trained;

inputting each sample test data in a fault circuit sample set into the circuit fault diagnosis model to be trained, obtaining a sample training result corresponding to each sample test data, and calculating an adaptive value of each pigeon based on the sample training result and a corresponding sample label;

calculating a training error according to the adaptive value of each pigeon;

updating the global optimal space vector in the space vectors of the pigeons according to the training errors, updating the vector space of the pigeons, updating the iteration times, and returning to the step of generating the space vectors of the pigeons until the maximum iteration times are reached;

after the maximum iteration number is reached, updating the search range value, if the search range value does not reach the maximum search range value, initializing the iteration number, returning to the step of initializing the neuron number of the hidden layer and setting the search interval of the pigeon until the maximum search range value is reached;

when the maximum search range value is reached, the circuit fault diagnosis model is determined based on the global optimal space vector.

6. The method of claim 5, wherein the vector space dimension of the pigeon population is the sum of the product of the number of input layer neurons and the number of hidden layer neurons.

7. The method of claim 5, wherein the maximum search range value is the same as the number of hidden layer neurons.

8. A circuit fault diagnosis apparatus characterized by comprising:

the circuit fault diagnosis system comprises a model acquisition module, a fault diagnosis module and a fault diagnosis module, wherein the model acquisition module is used for acquiring a circuit fault diagnosis model obtained by pre-training, the circuit fault diagnosis model is obtained by acquiring a fault circuit sample set, the fault circuit sample set comprises each fault circuit sample information, and the circuit fault sample information comprises sample test data obtained by testing a fault sample circuit and a sample label corresponding to each fault sample circuit; based on the fault circuit sample set, training a fault diagnosis model of the circuit to be trained based on a pigeon swarm algorithm to obtain the fault diagnosis model;

the data acquisition module is used for acquiring target test data obtained by testing the circuit to be diagnosed;

and the diagnosis module is used for performing circuit fault diagnosis on the target test data by adopting a circuit fault diagnosis model obtained by pre-training to obtain a circuit fault diagnosis result of the circuit to be diagnosed.

9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 7.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.

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