CN113485946A - Persistent memory key value system and operation method thereof - Google Patents
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- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
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- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
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- G06F12/02—Addressing or allocation; Relocation
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Abstract
The embodiment of the invention provides a persistent memory key value system and an operation method thereof, wherein the operation method comprises the following steps: searching an index of a persistent memory key value system to locate key value pair metadata to be inserted; acquiring write lock resources corresponding to the key value pair metadata in a dynamic random access memory; allocating a persistent memory to the key-value pair metadata and persisting the key-value pair metadata; atomically inserting the key-value pair metadata in the persistent memory key-value system. By the method and the device, in the key value pair insertion operation process, any write to the persistent memory is not introduced to the write lock resource operation, any log operation is not needed, the insertion operation performance is improved, and the expansibility under a multi-core architecture is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of persistent memory storage, in particular to a persistent memory key value system and an operation method thereof.
Background
Persistent Memory (Persistent Memory) has similar performance to Dynamic Random Access Memory (DRAM) and supports byte-granular addressing; meanwhile, the persistent memory can store data persistently like a magnetic disk. For example, existing persistent memory products have sub-microsecond latency and a single maximum capacity of 512GB, which presents many opportunities for new memory storage systems. Existing persistent memory supports two modes: a direct access mode and a memory mode are applied. And abstracting the persistent memory into special storage equipment which can be directly read and written through load and store instructions by applying a direct access mode. In memory mode, DRAM acts as a cache for persistent memory, providing an abstraction of large memory for applications, but without storage capability.
Most modern servers are of a multi-core architecture, that is, one processor contains dozens or even hundreds of CPU cores, so as to improve the concurrency performance of the whole system. However, the multi-core architecture presents a problem of concurrency control, i.e., how efficiently and correctly threads on different CPU cores concurrently access data.
The existing persistent memory key value system is not designed for a multi-core architecture, so that a plurality of problems are caused. First, concurrent primitives (e.g., read-write locks) that guarantee correct execution of multiple threads cause data to jitter back and forth between caches of different CPU cores, frequently triggering inefficient cache coherency protocols, and severely impacting CPU performance. Secondly, the write bandwidth of the persistent memory is very low, the single write bandwidth is only about 2.3GB/s, which is about 1/6 of DRAM, and various consistency mechanisms (such as logs) adopted by the key value system for ensuring crash consistency can consume extra write bandwidth of the persistent memory; meanwhile, the read-write lock is usually embedded inside the data structure, and the cache jitter caused by the read-write lock also causes write-back of a large amount of persistent memory. Finally, due to the high read latency and persistence latency of persistent memory, the time of critical sections is lengthened, causing the conflicting operations among different threads to be severely blocked.
Disclosure of Invention
The embodiment of the invention provides a persistent memory key value system and an operation method thereof, which at least solve the problem of low operation performance caused by the fact that the existing persistent memory key value system in the related art is not designed for a multi-core architecture.
According to an embodiment of the present invention, there is provided an operating method of a persistent memory key-value system, the method including: searching an index of a persistent memory key value system to locate key value pair metadata to be inserted; acquiring write lock resources corresponding to the key value pair metadata in a dynamic random access memory; allocating a persistent memory to the key-value pair metadata and persisting the key-value pair metadata; atomically inserting the key-value pair metadata into the persistent memory key value system, wherein the submission process of the key-value pair metadata insertion comprises two stages, in the first stage, emptying a persistent flag bit in the key-value pair metadata, and calling a CPU persistent instruction to write the persistent flag bit from a CPU cache to a persistent memory; in the second phase, the persistence flag is set and the read operation is notified that the key-value pair metadata has been successfully persisted.
In an exemplary embodiment, before acquiring the write lock resource corresponding to the key-value pair metadata in the dynamic random access memory, the method further includes; separating the write lock resource from an index of a persistent memory key value system, and maintaining the write lock resource in the dynamic random access memory.
In one exemplary embodiment, the write lock resource is maintained in the dynamic random access memory in a table structure, wherein an input of the table structure is an indexed node address and an output of the table structure is the corresponding write lock resource.
In an exemplary embodiment, before atomically inserting the key-value pair metadata in the persistent memory key-value system, the method further comprises: storing the key-value pair metadata in an atomically modifiable format.
In an exemplary embodiment, the atomically modifiable format means that the key-value pair metadata is wrapped into a continuous persistent memory space and is supported for atomic modification by the CPU.
In an exemplary embodiment, when the conflicting first insert operation and second insert operation occur simultaneously, the first insert operation is returned without allocating and writing persistent memory to the first insert operation.
In one exemplary embodiment, the key-value pair metadata includes at least one of: a key-value pair fingerprint, a key-value pair address, and a persistence flag bit; wherein the key-value pair fingerprint is a number of bits of a hash value of a key, the key-value pair address points to a key-value pair in persistent memory, and the persistent flag bit indicates a persistent state of the key-value pair metadata.
In one exemplary embodiment, after atomically inserting the key-value pair metadata into the persistent memory key-value system, further comprising: querying the key-value pair metadata in the persistent memory key-value system without a lock.
In one exemplary embodiment, querying the key-value pair metadata without a lock comprises: checking a persistence flag bit in the key-value pair metadata, and calling a CPU persistence instruction to persist the target key-value pair metadata if the persistence flag bit is in a clear state; and calling an atomic instruction to set the persistent flag bit and read the key-value pair pointed by the metadata.
In one exemplary embodiment, the method further comprises: and periodically recovering the persistent memory garbage through the background thread based on a memory recovery mode of a time period.
According to another embodiment of the present invention, there is provided a persistent memory key-value system, including: the searching module is used for searching the index of the persistent memory key value system to locate the key value pair metadata to be inserted; the acquisition module is used for acquiring write lock resources corresponding to the key value pair metadata in the dynamic random access memory; the allocation module is used for allocating a persistent memory for the key-value pair metadata and persisting the key-value pair metadata; the insertion module is used for atomically inserting the key-value pair metadata into the key-value system of the persistent memory, wherein the submission process of the key-value pair metadata insertion comprises two stages, in the first stage, a persistent flag bit in the key-value pair metadata is cleared, and a CPU persistent instruction is called to flush the persistent flag bit from a CPU cache to the persistent memory; in the second phase, the persistence flag is set and the read operation is notified that the key-value pair metadata has been successfully persisted.
In one exemplary embodiment, the system further comprises: and the maintenance module is used for separating the write lock resource from the index of the persistent memory key value system and maintaining the write lock resource in the dynamic random access memory.
In one exemplary embodiment, the system further comprises: a storage module to store the key-value pair metadata in an atomically modifiable format.
In one exemplary embodiment, the system further comprises: and the query module is used for querying the key-value pair metadata in the persistent memory key-value system without lock.
In one exemplary embodiment, the system further comprises: and the recovery module is used for periodically recovering the persistent memory garbage through the background thread based on a memory recovery mode of a time period.
According to a further embodiment of the present invention, there is also provided a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.
According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.
Through the embodiment of the invention, in the inserting operation process of the key value pair, the operation on the write lock resource does not introduce any writing on the persistent memory, and any log operation is not needed, so that the inserting operation performance is improved, and the expansibility under a multi-core architecture is improved.
Drawings
FIG. 1 is a flow diagram of a method of operation of a persistent memory key-value system according to an embodiment of the present invention;
FIG. 2 is a block diagram of a persistent memory key-value system according to an embodiment of the present invention;
FIG. 3 is a block diagram of a persistent memory key-value system according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a multi-core architecture-friendly persistent memory key-value system, according to one embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure of key-value pair metadata according to an embodiment of the present invention;
FIG. 6 is a flowchart of an insert operation of a multi-core architecture-friendly persistent memory key-value system according to an embodiment of the present invention;
FIG. 7 is a flowchart of a query operation of a multi-core architecture-friendly persistent memory key-value system according to an embodiment of the present invention;
fig. 8 is a schematic diagram of the elimination of two concurrent collision insertion operations according to an embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in conjunction with the embodiments.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Example 1
In this embodiment, an operation method of a persistent memory key value system is provided, and fig. 1 is a flowchart according to an embodiment of the present invention, where as shown in fig. 1, the flowchart includes the following steps:
step S102, searching an index of a persistent memory key value system to locate key value pair metadata to be inserted;
step S104, acquiring write lock resources corresponding to the key value pair metadata in the dynamic random access memory;
step S106, allocating a persistent memory for the key-value pair metadata and persisting the key-value pair metadata;
step S108, the key value pair metadata are atomically inserted into the key value system of the persistent memory, wherein the submission process of the key value pair metadata insertion comprises two stages, in the first stage, a persistent flag bit in the key value pair metadata is cleared, and a CPU persistent instruction is called to flush the persistent flag bit from a CPU cache to the persistent memory; in the second phase, the persistence flag is set and the read operation is notified that the key-value pair metadata has been successfully persisted.
Before step S104 in this embodiment, the method may further include; separating the write lock resource from an index of a persistent memory key value system, and maintaining the write lock resource in the dynamic random access memory.
In this embodiment, the write lock resource may be maintained in the dynamic random access memory in a table structure, where an input of the table structure is an indexed node address, and an output of the table structure is the corresponding write lock resource.
Before step S108 in this embodiment, the method may further include: storing the key-value pair metadata in an atomically modifiable format.
In this embodiment, the atomically modifiable format means that the key-value pair metadata is wrapped into a continuous persistent memory space and supported to be atomically modified by the CPU.
In this embodiment, when the conflicting first insert operation and second insert operation occur simultaneously, the first insert operation is returned without performing allocation and writing of the persistent memory to the first insert operation.
In this embodiment, the key-value pair metadata includes at least one of: a key-value pair fingerprint, a key-value pair address, and a persistence flag bit; wherein the key-value pair fingerprint is a number of bits of a hash value of a key, the key-value pair address points to a key-value pair in persistent memory, and the persistent flag bit indicates a persistent state of the key-value pair metadata.
After step S108 of the present embodiment, the method may further include: querying the key-value pair metadata in the persistent memory key-value system without a lock.
In this embodiment, querying the key-value pair metadata without a lock may include: checking a persistence flag bit in the key-value pair metadata, and calling a CPU persistence instruction to persist the target key-value pair metadata if the persistence flag bit is in a clear state; and calling an atomic instruction to set the persistent flag bit and read the key-value pair pointed by the metadata.
In this embodiment, the method may further include: and periodically recovering the persistent memory garbage through the background thread based on a memory recovery mode of a time period.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
Example 2
In this embodiment, a persistent memory key value system is further provided, and the system is used to implement the foregoing embodiments and preferred embodiments, and the description of which has been already made is omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 2 is a block diagram of a persistent memory key value system according to an embodiment of the present invention, and as shown in fig. 2, the system includes a lookup module 10, an acquisition module 20, an allocation module 30, and an insertion module 40.
The searching module 10 is configured to search an index of the persistent memory key value system to locate key value pair metadata to be inserted.
An obtaining module 20, configured to obtain a write lock resource in the dynamic random access memory, where the write lock resource corresponds to the key-value pair metadata.
An allocating module 30, configured to allocate a persistent memory to the key-value pair metadata and persist the key-value pair metadata.
An inserting module 40, configured to insert the key-value-pair metadata into the persistent memory key-value system atomically, where a submitting process of the key-value-pair metadata insertion includes two stages, and in a first stage, a persistent flag bit in the key-value-pair metadata is cleared, and a CPU persistent instruction is called to flush the persistent flag bit from a CPU cache to a persistent memory; in the second phase, the persistence flag is set and the read operation is notified that the key-value pair metadata has been successfully persisted.
Fig. 3 is a block diagram of a persistent memory key-value system according to another embodiment of the present invention, and as shown in fig. 3, the system includes a maintenance module 50, a storage module 60, a query module 70, and a recycle module 80 in addition to all the modules shown in fig. 2.
A maintaining module 50, configured to separate the write lock resource from an index of a persistent memory key-value system, and maintain the write lock resource in the dynamic random access memory.
A storage module 60 for storing the key-value pair metadata in an atomically modifiable format.
A query module 70 configured to query the key-value pair metadata in the persistent memory key-value system without lock.
The recovery module 80 is configured to periodically recover persistent memory garbage through a background thread in a memory recovery manner based on a time period.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
In order to facilitate understanding of the technical solutions provided by the present invention, the following detailed description will be made with reference to embodiments of specific scenarios.
Example 3
Fig. 4 is a schematic diagram of a multi-core architecture-friendly persistent memory key value system according to an embodiment of the present invention. As shown in fig. 4, based on the multi-core architecture-friendly persistent memory key value system of the present embodiment, the following insertion and query operations may be performed:
s1, separating the write lock resource from the index of the persistent memory key value system, and maintaining the write lock resource in the dynamic random access memory;
s2, storing the key-value pair metadata into an atomically modifiable format, atomically switching the system from one coherency state to another coherency state (two-phase atomic insertion) when an insert operation occurs using the atomic instructions of the CPU;
s3, when two conflict insert operations occur at the same time, one operation is returned directly without any allocation and writing of the persistent memory (concurrent insert elimination);
s4, when a query operation occurs, the key-value data is read without lock.
In this embodiment, the write lock resource is used to control multiple concurrent insert operations.
Further, in one embodiment of the invention, the write lock resources in the dynamic random access memory are maintained in a table structure with the table structure input being the node address of the index and the output being the corresponding lock resource.
Specifically, for example, the table structure of write lock resources is an array of 4096 64-bit lock fields; since the lock table only occupies 32KB of space, it can be cached in a high speed CPU second level cache with little introduction of TLB misses. Notably, the table structure may introduce a pseudo conflict, i.e., different inodes contend for the same lock field. But since the true load is mostly query intensive and the query operation is lock-free, the probability of false collisions is very low.
It should be noted that, the conventional persistent memory key-value system embeds the write lock into the persistent index, which may cause various problems: firstly, the lock operation brings extra write of the persistent memory, and consumes the limited bandwidth of the persistent memory; second, when the key-value system crashes and restarts, the entire index needs to be scanned, clearing the contents of the lock fields. The invention maintains the lock resources in the DRAM, reduces the consumption of the bandwidth of the persistent memory and improves the recovery performance at the same time.
Further, in one embodiment of the invention, the metadata of the key-value pair includes a key-value pair fingerprint, a key-value pair address, and a persistence flag bit, wherein the key-value pair fingerprint is bits of a hash value of the key, the key-value pair address points to a key-value pair in a persistence memory, and the persistence flag bit indicates a persistence state of the key-value pair metadata.
In particular, key-value pair fingerprints are used to speed up the positioning of key-value pairs. When the fingerprints are not matched, the query operation can directly skip the corresponding key-value pair metadata, so that the key-value pair in the persistent memory is prevented from being read for one time. When the persistence flag bit is 0, the key value pair metadata is not persisted; otherwise, it is successfully persisted. Key-value metadata is typically stored in indexes including hash tables, B + trees, dictionary trees, and the like.
Further, in one embodiment of the invention, an atomically modifiable format means that the key-value pair metadata is wrapped into a continuous persistent memory space and supported to be atomically modified by the CPU.
Specifically, fig. 5 is a schematic structural diagram of key-value pair metadata according to an embodiment of the present invention. As shown in FIG. 5, the key-value pair metadata is 64 bits, with the highest 16 bits storing the key-value pair fingerprint, the middle 47 bits storing the key-value pair address, and the lowest 1 bit storing the persistence flag bit. The reason why the highest 16 bits and the lowest bit can store additional information is that: first, the virtual address space of the intel processor has only the low 48 bits, and second, the key-value system assigns a persistent memory address that is 8-byte aligned (i.e., the lowest 3 bits of the address are 0). The CPU may atomically manipulate 64-bit key-value pair metadata.
Further, in one embodiment of the invention, the coherency state means that the metadata of the key value system and the inserted key value pairs may be in a one-to-one correspondence and permanently stored in persistent memory.
Further, in an embodiment of the present invention, the commit process of the insert operation includes two stages, where the first stage clears the persistent flag bit in the key-value pair metadata and invokes a CPU persistent instruction to flush it from the CPU cache to the persistent memory; in the second phase, a persistence flag bit is set to inform a read operation that the key-value pair metadata has been successfully persisted.
Fig. 6 is a flowchart of an insert operation of a multi-core architecture-friendly persistent memory key value system according to an embodiment of the present invention, and as shown in fig. 6, the insert operation may include the following steps:
step S601, searching indexes and positioning key value pair metadata;
step S602, acquiring corresponding lock resources in the DRAM;
step S603, allocating a persistent memory and persisting key value pairs;
step S604, the submission process of the key-value pair metadata insertion comprises two stages, wherein in the first stage, the persistent flag bit in the key-value pair metadata is cleared, and a CPU persistent instruction is called to flush the persistent flag bit from the CPU cache to a persistent memory;
step S605, in the second phase of the submission of the insert operation, sets the persistence flag bit, and notifies the read operation that the key-value pair metadata has been successfully persisted.
As shown in FIG. 6, prior to the commit process, the insert operation successfully acquires the corresponding lock resources in DRAM and allocates persistent memory and persists the inserted key-value pair. For example, on an Intel CPU, the persistence instructions include CLFLUSH, CLWB, and CLFLUSHOPT. Assignment of key-value pair metadata in both phases of submission is atomic; in the first phase, the entire new key-value pair metadata value is written and persisted. Depending on the atomic write provided by the CPU, the consistency of the insertion operation is protected without a mechanism such as a log.
Further, in an embodiment of the present invention, in the lock-free query process of the query operation, the persistent flag bit in the target key-value pair metadata is checked, if the persistent flag bit is in a clear state, the CPU persistent instruction persistent key-value pair metadata is called, and then the atomic instruction is called to set the persistent flag bit.
Fig. 7 is a flowchart of a query operation of a multi-core architecture-friendly persistent memory key-value system according to an embodiment of the present invention, where, as shown in fig. 7, the query operation may include the following steps:
step S701, searching indexes and positioning target key value pair metadata;
step S702, judging whether the persistent flag bit of the target key value pair metadata is in an empty state, if so, executing step S703, and if not, executing step S705;
step S703, calling a CPU persistence instruction to persist the target key value pair metadata;
step S704, calling an atomic instruction CAS (compare-and-swap) to set a persistent flag bit;
step S705, the target key-value pair pointed to by the metadata is read.
As shown in fig. 7, in the process of query operation, when the persistence flag bit of the target key value pair metadata is in a clear state, it represents that the metadata has not been successfully persisted, and in order to ensure that the query operation does not read uncommitted data, the query operation actively persists the metadata, and calls an atomic instruction to set the persistence flag bit. The active persistence mechanism ensures that all key-value pair metadata do not need to be traversed to set the persistence flag after a system crash restarts.
Fig. 8 is a schematic diagram illustrating the elimination of two concurrent conflict insertion operations according to an embodiment of the present invention. As shown in fig. 8, in this embodiment, when two concurrent conflicting insert operations occur, one of the operations returns directly without any allocation and modification of persistent memory. This mechanism of eliminating operations does not violate the correct concurrency semantics because the execution results of two operations that overlap in time are equivalent to the execution results in some serial order in the definition of linearization (linearization).
Further, in an embodiment of the present invention, for the problem of lock-free reading of the query operation, an Epoch (time period) -based memory reclamation method is used, and the background thread is used to periodically reclaim the memory garbage.
Specifically, the key-value system maintains a global counter while each thread maintains a local counter. Each key value operation begins by updating a local counter to a global counter. When the persistent memory space needs to be released, the value of the local counter and the released memory address are recorded in the recovery linked list. Meanwhile, a background thread periodically adds 1 to the global counter, collects the local counter values of all threads, calculates the minimum value and records the minimum value as Safe-Epoch; at this time, all the memory smaller than Safe-Epoch in the recycle linked list can be safely released.
In the insertion operation process of the embodiment of the invention, the operation on the write lock resource does not introduce any write on the persistent memory, and any log operation is not needed, so that the insertion operation performance is improved. In addition, when multiple concurrent conflicting insert operations occur, persistent memory allocation and writing is further reduced. Aiming at query operation, the lock-free process greatly improves the concurrent query performance of a key value system under a multi-core architecture while ensuring correct semantics.
Embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above-mentioned method embodiments when executed.
In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.
In an exemplary embodiment, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary embodiments, and details of this embodiment are not repeated herein.
It will be apparent to those skilled in the art that the various modules or steps of the invention described above may be implemented using a general purpose computing device, they may be centralized on a single computing device or distributed across a network of computing devices, and they may be implemented using program code executable by the computing devices, such that they may be stored in a memory device and executed by the computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into various integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.
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| WO2022095685A1 (en) * | 2020-11-04 | 2022-05-12 | 中兴通讯股份有限公司 | Persistent memory key value system and operation method therefor |
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