CN113485749B - Data control system and data control method - Google Patents
Data control system and data control methodInfo
- Publication number
- CN113485749B CN113485749B CN202110711153.7A CN202110711153A CN113485749B CN 113485749 B CN113485749 B CN 113485749B CN 202110711153 A CN202110711153 A CN 202110711153A CN 113485749 B CN113485749 B CN 113485749B
- Authority
- CN
- China
- Prior art keywords
- control
- cache
- control instruction
- data
- network chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The application provides a data management and control system and a data management and control method, wherein the data management and control system comprises a Central Processing Unit (CPU) controller, a network chip and an external memory, the network chip comprises a statistics and counting module, the statistics and counting module is externally connected with the external memory, the CPU controller is connected with the network chip and is used for sending a management and control instruction to the network chip, and the statistics and counting module in the network chip is used for executing management and control operation on related data of a counter in the external memory based on the management and control instruction. Therefore, the management and control of the data of the network chip are realized, and the participation of CPU cores in the network chip is not needed.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a data management and control system and a data management and control method.
Background
The statistical counter is used as a functional module which is indispensable for the normal operation of the chip, and provides an important debugging means for the monitoring of the operation state information of the chip. In the chip, the statistics and counting of the related information such as the number of messages, the flow of messages, the service quality (Quality Of Service, QOS), the state of each functional module and the like can be realized by using a statistics counter. During the chip operation, the statistics counting module monitors various types of counters, and a special module is generally used for updating and collecting statistics counter information. In general, data collected by a counter is stored in an external memory of a chip or an internal memory area (SRAM) of a statistics counting module, and a one-to-one mapping rule of a counter address and a memory (DDR/SRAM) and strict hardware design logic are preset to ensure accurate access to a specific counter. During the operation of the chip, various counter data can be continuously refreshed, and each counter needs to be subjected to the step of 'reading- > modifying- > writing' when being updated. Meanwhile, if the counter data related to the specific state needs to be acquired, the data can be unloaded from the memory related to the corresponding counter address in a resource scheduling mode and the like, and then the data is transmitted back to the CPU core in the chip for processing. With the expansion of chip services and in order to guarantee the operation of chips more efficiently, there is an increasing demand for statistical counters, so the statistical count entries (types and numbers) that the chips need to supervise will become more and more huge.
Due to the limitation of the resources of the chip (high implementation cost and limited processing performance), the supervision of a large number of statistics counting entries may bring additional overhead to the main business of the CPU core in the chip, and also cause excessive consumption of the internal area of the chip. When the statistical data of the specific service state is acquired, a command needs to be initiated through the CPU core, the statistical data is loaded into the memory corresponding to the designated counter in the process of executing the command, and then the statistical data is transmitted back to the chip CPU core for processing, so that the same software and hardware resources are required to be contended for the chip service and the state supervision. Meanwhile, the access speed to the statistical data is reduced, and the chip is not beneficial to the real-time supervision of the running state data.
Therefore, how to use the debugging means to monitor the statistics of the network chip in real time in an efficient and convenient manner is one of the technical problems that deserve consideration.
Disclosure of Invention
In view of the above, the present application provides a data management and control system and a data management and control method for efficiently managing and controlling the statistical data of a network chip.
Specifically, the application is realized by the following technical scheme:
According to a first aspect of the present application, there is provided a data management and control system, comprising a Central Processing Unit (CPU) controller, a network chip and an external memory, wherein the network chip comprises a statistics counting module, the statistics counting module is externally connected with the external memory, wherein:
The CPU controller is connected with the network chip and used for sending a control instruction to the network chip;
and the statistical counting module in the network chip is used for executing control operation on the relevant data of the counter in the external memory based on the control instruction.
According to a second aspect of the present application, there is provided a data management and control method applied to a central processing unit CPU controller, the CPU controller being connected to a network chip, the network chip including a statistics counting module, the statistics counting module being externally connected to the external memory, the method comprising:
And sending a control instruction to the network chip so that the statistical counting module in the network chip executes control operation on the relevant data of the counter in the external memory based on the control instruction.
According to a third aspect of the present application, there is provided a data management and control method applied to a network chip, where the network chip is connected to a CPU controller of a central processing unit, the network chip includes a statistics counting module, and the statistics counting module is externally connected to an external memory, the method includes:
receiving a control instruction sent by the CPU controller;
and executing control operation on the relevant data of the counter in the external memory based on the control instruction by utilizing the statistics counting module.
The embodiment of the application has the beneficial effects that:
When the CPU controller needs to manage the data in the network chip, the management and control instruction is sent to the network chip, and after the network chip receives the management and control instruction, the management and control instruction is sent to the statistics counting module, so that the statistics counting module can access the external memory based on the received management and control instruction, and then execute management and control operation on the relevant data of the counter recorded in the external memory. Therefore, the CPU core in the network chip can realize the control of the statistical data in the network chip without participation, so that the business service work of the CPU core in the network chip is not delayed, namely, the efficient control of the statistical data in the network chip is realized.
Drawings
FIG. 1 is a schematic diagram of a data management and control system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an interaction flow of a data management and control method according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another data management and control system according to an embodiment of the present application;
FIG. 4a is a flowchart illustrating another data management and control method according to an embodiment of the present application;
FIG. 4b is a schematic diagram of a signal flow scheme according to an embodiment of the present application;
FIG. 5a is a flowchart illustrating another data management and control method according to an embodiment of the present application;
FIG. 5b is a schematic diagram of another signal flow scheme provided by an embodiment of the present application;
Fig. 6 is a schematic structural diagram of a network chip according to an embodiment of the present application;
Fig. 7 is a schematic structural diagram of a statistics counting module according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the corresponding listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The term "if" as used herein may be interpreted as "at..once" or "when..once" or "in response to a determination", depending on the context.
The data management and control system provided by the application is described in detail below.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a data management and control system provided by the present application, where the data management and control system includes a CPU controller, a network chip and an external memory, the network chip includes a statistics counting module, the statistics counting module is externally connected to the external memory, and the network chip further includes at least one CPU core, where each network chip in fig. 1 may include n+1 CPU cores, the CPU core 0 runs a main program, and the CPU cores 1 to CPU cores n respectively run application programs APP1 to APPn to provide various service respectively. The schematic interaction flow of the CPU controller and the network chip can be referred to as fig. 2:
s201, the CPU controller sends a control instruction to the network chip.
In this step, the CPU controller is connected to the network chip, and generates a control instruction when the statistical data in the network chip needs to be controlled, and then sends the control instruction to the network chip.
It should be noted that, in this embodiment, the number of network chips externally connected to the CPU controller is not limited, that is, the CPU controller may be externally connected to at least one network chip, but the executing process of controlling the statistical data of each network chip by the CPU controller is the same, and for convenience of subsequent description, only the statistical data of controlling one network chip by the CPU controller is taken as an example for illustration.
In particular, the main function of the CPU controller is to handle transactions of the control management plane on the network chip, which may relate to aspects of the chip operating state (as embodied by the statistics). By adopting the control mode, each CPU core in the network chip can be helped to run the service more independently, and the CPU controller can provide a more convenient means to realize the real-time state supervision of the network chip. And, as the manager of the control plane, the CPU controller can realize the state monitoring of a plurality of network chips and communicate with the network chips at the same time.
Alternatively, the CPU controller may be connected to each network chip by way of, but not limited to, a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI). Specifically, the CPU controller comprises a plurality of PCI interfaces, and can be connected with one network chip through each PCI on the CPU controller, so that the CPU controller can be hung with a plurality of network chips at the same time, and then the statistical data of the plurality of network chips can be managed and controlled at the same time.
Optionally, when the CPU controller needs to perform management and control on a specified network chip, the CPU controller may log onto the network chip first, after the login is successful, the CPU controller may display a management and control view of the network chip, where the management and control view includes various management and control options for managing and controlling the network chip, and then the user may trigger a management and control instruction for a certain management and control option, so that a management and control instruction is generated, and then the CPU controller may send the management and control instruction to the network chip.
Optionally, the user may configure the control requirements of the network chip in the CPU controller in advance, and different control requirements correspond to different control instructions, and the CPU controller may send the preconfigured control instructions to each network chip as required, so as to implement supervision of the running state of the network chip and control of data.
And S202, the network chip uses a statistics counting module therein to execute a control operation on the relevant data of the counter in the external memory based on the control instruction.
In this step, after receiving the control instruction, the network chip sends the control instruction to the statistics counting module, so that the statistics counting module can access the external memory based on the received control instruction, and then execute the control operation on the relevant data of the counter recorded in the external memory. Therefore, the CPU core in the network chip can realize the control of the statistical data in the network chip without participation, so that the business service work of the CPU core in the network chip is not delayed, namely, the efficient control of the statistical data in the network chip is realized.
Optionally, the above-mentioned control instruction may be, but not limited to, a read instruction, a modify instruction, a find instruction, a write instruction, etc., that is, control instructions of different instruction types and different control instructions include different operation codes therein, that is, the read, modify, find, write operation codes respectively correspond to different operation codes, for example, when the read operation code is written in the control instruction, the control instruction is a read instruction, and so on, and will not be described in detail herein. Based on the different management instructions, the statistics counting module in the network chip can execute different management operations based on the management instructions, such as reading the statistics, modifying the statistics, writing the statistics or searching the statistics, and the like.
In a possible embodiment, the network chip further includes a cache module, and the CPU controller is connected to the cache module through a communication channel, with reference to the data management and control system shown in fig. 3.
On the basis, when the CPU controller sends a control instruction to the network chip, the step S201 can be implemented according to the following process that when the CPU controller needs to control the related data of the counter in the network chip, the control instruction is sent to the communication channel to be converted into a control message and sent to the cache module in the network chip, and the control message comprises the control instruction.
On the basis, after receiving the control message, the cache module sends the control instruction analyzed from the control message to the statistics counting module. Thus, the statistics counting module can receive the control instruction sent by the CPU controller.
Specifically, the CPU controller accesses and controls the statistical data stored in the external memory and used for counting the running state of the network chip in a bypass mode, so that the method is simple, convenient and quick. In this embodiment, the CPU controller bypasses the CPU core of the network chip, directly sends the control instruction through a communication channel between the CPU controller and the cache module, and then the cache module forwards the control instruction to the statistics counting module to implement control of the running state of the network chip, that is, control of the data of the corresponding counter stored in the external memory, referring to the signal flow mode of the data control method shown in fig. 3, path1 in fig. 3 is the data flow process in this embodiment.
Further, the communication channel between the CPU controller and the buffer module is a PCI channel, the CPU controller may send a management and control command to the PCI channel through a PCI interface, and the PCI channel is configured with a PCI packet configuration module, where the PCI packet configuration module captures the management and control command, and encapsulates the management and control command into a management and control packet, where the management and control packet includes the management and control command, and then the PCI packet configuration module sends the management and control packet to the buffer module in the network chip. Specifically, after receiving the management and control instruction, the PCI message construction module automatically constructs a message according to the instruction type, and then fills relevant contents such as filling address information, a counter identifier and the like according to a message format, wherein it can be understood that the address information can be understood as address information of a next hop, the counter identifier can be understood as a counter identifier of a counter to be accessed, and in addition, if the management and control instruction is a write instruction, the management and control instruction further comprises data to be written, and the filled management and control message further comprises the data to be written.
On the basis, after the cache module receives the management and control message, the management and control instruction is analyzed from the management and control message, and the management and control instruction is forwarded to the statistics counting module. The statistics counting module may perform a policing operation based on the policing instruction to the external memory with respect to the counter indicated by the policing instruction. Thus, the statistical data for monitoring the running state of the network chip is efficiently managed.
The statistics counting module can analyze the target counter identification from the control instruction after receiving the control instruction, and execute control operation based on the data recorded in the storage space corresponding to the target counter identification in the external memory.
Specifically, the statistics counting module may find a storage address corresponding to a counter identifier recorded in the management instruction according to a predetermined address mapping rule, where the storage address is recorded as a storage address of data recorded in an external memory and corresponding to the counter identifier, and then access the external memory based on the determined storage address and perform a management operation on data recorded in a storage space corresponding to the counter identifier in the external memory. Therefore, the CPU controller monitors the statistical data in a bypass mode, the participation of CPU cores in the network chip is not needed, the running efficiency of the network chip is greatly improved, and the access efficiency and the processing performance of the bypass mode to the statistical data can reach higher level.
In another possible embodiment, the CPU controller further includes a buffer, on the basis of which the CPU controller may further execute a data management method according to the flow shown in fig. 4a, including the following steps:
s401, the CPU controller caches the control instruction into a cache region of the CPU controller.
S402, a CPU core in the network chip accesses a buffer area in the CPU controller, and after the control instruction is read, the control instruction is sent to a statistics counting module in the network chip.
In steps S401 and S402, part of the memory, i.e., the buffer, in the CPU controller may be used to buffer the control instruction or the returned statistics. When the CPU controller needs to monitor the statistic data in the network chip, the control instruction is written into the own buffer area, so that the dispatching of the kernel CPU is realized, namely, the CPU kernel meeting the condition can be appointed in advance, and then the buffer area of the CPU controller is accessed by the CPU kernel. The CPU cores satisfying the condition may be CPU cores with relatively high processing capacity or relatively low traffic processing capacity, and may be at least one CPU core satisfying the condition according to the actual situation, and when a plurality of CPU cores satisfying the condition are selected, the CPU cores may be polled to access the cache area of the CPU controller, so that no processing pressure is brought to the CPU cores.
In addition, after the selected CPU core in the network chip reads the management instruction from the cache area of the CPU controller, the management instruction may be sent to the statistics counting module through, but not limited to, the SOC internal bus. In this way, the statistics counting module may perform a policing operation based on the policing instruction. Specifically, the selected CPU core may be pre-reserved with several threads dedicated to reading the control instruction from the cache area of the CPU controller and writing the control result later, which may not affect the processing pressure of the CPU core, and may be used as related services for processing the CPU core when the control instruction does not need to be read.
Optionally, the network chip provided in this embodiment may further include a buffer module, and on the basis of this, the signal flow mode of the implemented data management and control method is shown in fig. 4b, and path2 in fig. 4b is the data flow process in this embodiment. On the basis, after the selected CPU core reads the control instruction from the cache area, the control instruction is sent to the cache module shown in fig. 4b, then the cache module forwards the control instruction to the statistics counting module, and then the statistics counting module executes corresponding control operation based on the control instruction.
Optionally, the control instruction in this embodiment includes a target counter identifier, and the statistics counting module may execute step S202 according to a procedure of parsing the target counter identifier from the control instruction, and executing a control operation based on data recorded in a storage space corresponding to the target counter identifier in the external memory.
Specifically, the statistics counting module may find a storage address corresponding to a counter identifier recorded in the management instruction according to a predetermined address mapping rule, where the storage address is recorded as a storage address of data recorded in an external memory and corresponding to the counter identifier, and then access the external memory based on the determined storage address and perform a management operation on data recorded in a storage space corresponding to the counter identifier in the external memory.
It should be noted that, when the CPU core sends a control instruction to the statistics counting module, the CPU core may also send the control instruction in a message form.
And S403, if the control result exists in the operation of executing the control operation, the statistical counting module sends the control result to a CPU core in the network chip.
In this step, after the statistics counting module performs the control operation, a control result may be obtained, and when the control result exists, the control result is returned to the CPU core in the network chip according to the original path.
S404, the CPU core in the network chip writes the control result into the cache region of the CPU controller.
In this step, the CPU core writes the control result (e.g., returned data) into the cache region of the CPU controller through the connection line between the network chip and the CPU controller.
S405, the CPU controller reads the control result from the self cache area.
In the step, the CPU controller can read the control result from the own buffer area, thereby realizing the real-time supervision of the statistical data by the method by utilizing the external CPU controller.
It should be noted that, steps S403 to S405 are only executed when the statistics counting module needs to return the control result to the CPU controller, for example, when the control instruction is a read instruction, the statistics counting module needs to return the read data (control result) to the CPU core in the network chip, and then the CPU core writes the read data into the cache area of the CPU controller, so that the CPU controller can read the data returned by the statistics counting module into its own cache area. Therefore, the management and control of the CPU controller to the statistical data of the network chip are also realized, and as only the CPU cores meeting the conditions are selected to forward the management and control instruction in the application, the participation of all the CPU cores in the network chip is not needed, and the service processing of the CPU cores is not influenced.
In another possible embodiment, the data management method may also be performed according to the method shown in fig. 5a, and includes the following steps:
s501, when a CPU core in the network chip needs to operate a counter in the service processing process, a data operation instruction is sent to a statistics counting module, and the data operation instruction comprises a target counter identifier.
S502, after receiving the data operation instruction, the statistical counting module in the network chip executes corresponding operation on the data in the storage space corresponding to the target counter identifier in the external memory.
In steps S501 to S502, the CPU core in the network chip may have a need to call the statistics data of the network chip, and on this basis, when the CPU needs to operate the counter during the service processing, a data operation instruction may be generated, and then the data operation instruction is sent to the statistics counting module. Thus, the statistics counting module can execute the operation corresponding to the data operation instruction according to step S502.
It should be noted that, when the CPU core sends a data operation instruction to the statistics counting module, the CPU core may also send the data operation instruction in a packet form.
Optionally, the network chip in this embodiment further includes a buffer module interposed between the CPU core and the statistics counting module, that is, the buffer module is connected to the CPU core and the statistics counting module respectively. On this basis, please refer to fig. 5b for a signal flow manner of the implemented data management and control method, and path3 in fig. 5b is a data flow process in this embodiment. On this basis, the CPU core sends the data operation instruction to the cache module in fig. 5b, and then the cache module forwards the data operation instruction to the statistics counting module, so that the statistics counting module performs the corresponding operation.
It should be noted that, the data operation instruction in this embodiment may include, but is not limited to, read, modify, and write operation instructions. It should be noted that when the data operation instruction is a read instruction, the statistics counting module reads data after executing corresponding read operation on the data in the storage space corresponding to the target counter identifier in the external memory, and then the statistics data module sends the read data to the CPU core through the cache module, so that the control operation on the statistics data when the CPU core has a demand is realized.
It should be noted that, the three data management and control modes provided by the application can exist simultaneously in practical application, namely, can be started simultaneously, or can be configured with any one or two data management and control modes, and can be specific according to practical situations. Thereby increasing the flexibility of data management of the network chip.
Optionally, based on any of the above embodiments, when the network chip includes a buffer module, and the buffer module is interposed between a CPU core and a statistics counting module in the network chip, refer to any one of the data management manners under the data management system shown in fig. 3, fig. 4b, or fig. 5 b. On this basis, a first clock synchronization module and a second clock synchronization module are configured between the above-mentioned buffer module and the statistics counting module, and refer to fig. 6, where:
The first clock synchronization module receives the control instruction or the data operation instruction sent by the cache module, performs clock domain conversion processing on the control instruction or the data operation instruction, and sends the converted control instruction or data operation instruction to the statistics counting module.
In addition, the second clock synchronization module receives the control result sent by the statistics counting module, performs clock domain conversion processing on the control result, and sends the converted control result to the cache module.
In particular, in the whole data path, it is critical to compare the cache module directly interacting with the statistics counting module with the external memory. The buffer module performs preliminary classification on the received control message, control command, data operation command or control result and sends the classified data operation command or control result to the corresponding interface. After receiving the control message, the operation instruction, the data operation instruction or the control result, the statistical counting module analyzes and processes the control message, the operation instruction, the data operation instruction or the control result, and an external memory mapped by the statistical counting module is required to be accessed in the processing process. The statistics counting module is mainly used for initializing the statistics data, completing the updating of the counter data, periodically scanning, updating and reporting the statistics data, collecting the statistics information through the message queue, and realizing the dynamic allocation, circulation and automatic allocation between the counter and the network data flow. Implementation of the statistics function relies on the delivery, resolution and response of commands.
On the basis, taking the case that the buffer module receives the control instruction as an example, after the buffer module receives the control instruction, the buffer module can recognize and process the control instruction, if the control instruction is found to be sent to the statistics counting module, the buffer module can buffer the control instruction to the first clock synchronization module, and the first clock synchronization module can convert and process the clock domain of the control instruction so as to synchronize to the clock domain of the first clock synchronization module, so that the follow-up recognition and processing of the statistics counting module are facilitated. And then sending the converted control instruction to a statistics counting module. After receiving the control instruction, the statistical counting module analyzes the control instruction to analyze the operation code and the target counter identification of the control instruction, and then executes the control operation indicated by the operation code, such as reading, writing or modifying data, etc., on the data corresponding to the target counter identification recorded in the external memory based on the target counter identification and the operation code.
In addition, after the statistics counting module obtains data based on the control instruction executing control operation, the obtained data is packaged into a data packet, and the data packet is used as a control result and returned to the second clock synchronization module, and the second clock synchronization module can perform clock domain conversion processing on the control result so as to convert the control result into a clock domain matched with the cache module, so that the cache module can process conveniently. And then the converted control result is sent to a cache module, and the cache module feeds back the control result to the CPU controller. Therefore, the control operation is executed from the external memory and the control result is returned, namely, the control of the statistical data of the network chip is realized.
When the first clock synchronization module receives the control message, the first clock synchronization module is used for performing clock domain conversion processing on the control message after receiving the control message sent by the cache module, and sending the converted control message to the statistics counting module. When the control result is obtained based on the control message statistics and counting module, the second clock synchronization module is used for receiving the control result sent by the statistics and counting module, performing clock domain conversion processing on the control result, and sending the converted control result to the cache module.
It should be noted that, the processing procedure of the management and control message and the data operation instruction refers to the processing procedure of the management and control instruction, which will not be described in detail here. Furthermore, the first clock synchronization module and the second clock synchronization module in the present embodiment may be, but not limited to, first-in-first-out (FIFO) modules.
Further, a statistics memory adapting module and a message queue module are further disposed between the statistics counting module and the external memory, as shown in fig. 6. When the control instruction is a read instruction, a modify instruction or a write instruction, the statistic data module sends the read instruction, the modify instruction or the write instruction to the statistic memory adapting module, so that the statistic memory adapting module can read, modify or write the data of the counter recorded in the external memory based on the read instruction, the modify instruction or the write instruction, but in the operation process, some state changes may occur, and some data representing the state changes may be generated, and the generated data is temporarily stored in the message queue module first, and then is read from the message queue module by the statistic memory adapting module and written into the external memory, so that the data is written into the storage space corresponding to the counter identifier in the external memory. Thus, the access of the software program can be facilitated, and the message interaction between the software and the hardware is realized more conveniently.
In addition, when the memory adapting module reads data from the external memory and the read data needs to be returned, the statistical memory adapting module can send the read data to the statistical counting module, the read data is a management and control result, the statistical counting module sends the read data to the second clock synchronization module, and the second clock synchronization module sends the data after clock domain conversion to the cache module. The received data is then returned by the cache module to the CPU controller or CPU core.
Optionally, based on any one of the foregoing embodiments, the statistics counting module in this embodiment includes a scheduling unit, a command buffer unit, and an execution unit, where the scheduling unit and the command buffer unit are in communication with each other, and the command buffer unit is connected to the execution unit, as shown in fig. 7, where:
The scheduling unit is used for sending a cache request to the command cache unit after receiving the control instruction so as to cache the control instruction in the command cache unit;
And the command cache unit is used for inserting the control instruction into a connection table corresponding to the counter indicated by the control instruction. In practical application, the scheduling unit continuously analyzes the management and control instruction, and then sends the management and control instruction to the command cache unit, so that the command cache unit also continuously inserts the received management and control instruction into the corresponding connection table.
The execution unit is used for reading the control command from the command cache unit, analyzing the counter identification from the read control command, and executing the operation indicated by the control command on the data in the storage space corresponding to the counter identification in the external memory.
Specifically, after the information (the control instruction, the control message, and the data operation instruction) arrives at the statistics counting module, the scheduling unit receives the information first, and then the scheduling unit classifies the received information to determine whether the received information is sent to the external memory or is returned to the CPU controller or the CPU core, so as to execute different operations, for example, determine the target of the control instruction, and determine the target to send the control instruction to the corresponding interface and execute the corresponding operation (such as obtaining the data corresponding to the target counter identifier from the external memory). For convenience of description, taking the control instruction as an example, when the control instruction arrives at the scheduling unit, the scheduling unit confirms that the control instruction is to operate the external memory, and then parses the operation code from the control instruction to identify the type of the control instruction. In addition, the scheduling unit sends a cache request (request) to the command cache unit, and after receiving a response result sent by the command cache unit, writes the control instruction into a connection table corresponding to a counter (counter identifier) indicated by the control instruction maintained by the command cache unit.
Then, the execution unit in this embodiment reads the management and control instruction from the command buffer unit according to the set rule, and then parses the target counter identifier and the operation code from the management and control instruction, and because the external memory stores the statistics data of each counter for monitoring the running state of the network chip, the execution unit can determine the target storage address corresponding to the target counter identifier based on the mapping relationship between the counter identifier and the storage address, and then execute the management and control operation indicated by the operation code on the data in the storage space corresponding to the target storage address in the external memory.
Further, after the execution unit performs the control operation on the control instruction, the scheduling unit is notified to instruct the scheduling unit to delete the control instruction.
Further, when the execution unit performs the control operation with respect to the control instruction, there is a control result, the execution unit may send the control result to the cache module.
Optionally, the control instruction recorded in the connection table provided in this embodiment is written in time sequence, and in addition, the statistics counting module further includes a cache, the scheduling unit may communicate with the cache, please refer to fig. 7, and the control instruction in this embodiment includes a target counter identifier, where:
the scheduling unit is also used for sending the cache address of the control instruction to the cache, wherein the cache address is an idle address after the command cache unit writes the last control command to the scheduling unit;
The cache is used for caching the received cache address and the control instruction sent by the command caching unit, and also can cache the data generated after the execution unit executes the control instruction;
The execution unit is further configured to read a management and control command from the command cache unit, parse a target counter identifier from the read management and control command, query whether data corresponding to the target counter identifier exists in the cache based on the target counter identifier, and execute an operation indicated by the management and control command on the data corresponding to the target counter identifier in the cache if the data corresponding to the target counter identifier exists in the cache.
Specifically, the command buffer unit maintains a connection table, the connection table is written into the connection table according to the time sequence of receiving the control instruction, and after the control instruction is written into the connection table corresponding to the counter indicated by the control instruction, the command buffer unit sends an idle address after the connection table is written into the control instruction to the scheduling unit. Meanwhile, the command buffer unit also informs the scheduling unit of the idle state of the connection table, namely, whether the connection table is idle or not. Based on this, the cache address is the free address in the connection table, i.e. the free address after the command cache unit writes the control command. When the scheduling unit receives the buffer address and the idle state of the connection table, if the connection table is confirmed to be idle, the control instruction is written into the idle buffer address and is sent to the cache, and if the connection table is not idle, the control instruction can be temporarily written into the command buffer unit.
In this way, after the cache receives the above-mentioned cache address, the cache may store the cache address, in addition, the cache may also store the initial data read from the external memory, and may also cache the data generated by the execution unit executing the control instruction, etc., which is specific to the actual situation.
On the basis, the execution unit can execute the management and control operation according to the following process that after the management and control instruction is read from the command cache unit, a target counter identifier is extracted from the management and control instruction, then whether data corresponding to the target counter identifier exist in a cache is queried by utilizing the target counter identifier, if so, the data is extracted from the cache, and then the management and control operation indicated by the management and control instruction is executed on the data. And if the data corresponding to the target counter identification does not exist in the cache, executing the operation indicated by the control instruction on the data of the counter corresponding to the target counter identification recorded in the external memory.
It should be noted that, the command buffer unit may maintain a connection table for each counter, or may correspond to one connection table for a plurality of counters, which may be specific according to the actual situation, but the management and control instructions stored in each connection table are written in time sequence.
In a possible embodiment, the statistics counting module in this embodiment further includes an internal storage area, as shown in fig. 7, wherein:
And the internal storage area is used for storing the related data of the counter.
In practical applications, the relevant data of the counters are typically stored in an external memory, but the data of some of the counters used to detect the operation state of the network chip may also be stored in a custom manner in an internal storage area, and then the data of the remaining counters are stored in the external memory. In this way, after the statistics counting module parses the target counter identifier, if the data of the counter corresponding to the target counter identifier is located based on the target counter identifier and stored in the internal storage area, the management and control operation is performed on the data corresponding to the target counter in the internal storage area, and if the network chip needs the related data of the counter, the statistics counting module sends the data generated by performing the management and control operation to the network chip, as shown in fig. 7. When the data of the counter corresponding to the target counter is located based on the target counter identifier and stored in the external memory, the data corresponding to the target counter stored in the external memory is executed to perform the control operation, and at this time, if the network chip needs the related data of the counter, the statistics counting module sends the data generated by executing the control operation to the network chip, as shown in fig. 7.
The number of the counters stored in the internal storage area is not limited, and may be specifically determined according to practical situations. For example, in an actual scene, if the number of counters for detecting the operation state of the network chip is relatively small, data of all the counters may be stored in the internal memory area in the scene.
It should be noted that the internal storage area in the present embodiment may be, but not limited to, SRAM or the like.
Optionally, the statistics counting module in the present application further includes a transmit TX interface and a receive RX interface for communicating with an external memory, as also shown in fig. 7. On the basis, the execution unit can write data into the external memory according to the TX interface or read the statistical data recorded in the external memory through the RX interface, and in addition, the cache can also read the statistical data recorded in the external memory through the RX interface.
It should be noted that the cache module in any of the above embodiments of the present application may be, but is not limited to, a secondary cache module. Furthermore, the external memory in any of the embodiments of the present application may be, but is not limited to, DDR-type memory.
Based on the same inventive concept, the embodiment also provides a data management and control method which is applied to the CPU controller, wherein the CPU controller is connected with the network chip, the network chip comprises a statistics counting module, and the statistics counting module is externally connected with an external memory. On the basis, the CPU controller can send a control instruction to the network chip according to the process data control method so that the statistics counting module in the network chip can execute control operation on the related data of the counter in the external memory based on the control instruction.
By implementing the data management and control method, when the CPU controller needs to manage the data of the network chip detected by the counter, the CPU controller can send the management and control instruction to the network chip, and after the network chip receives the management and control instruction, the network chip can send the management and control instruction to the statistics and control module, so that the statistics and control module can access the external memory based on the received management and control instruction, and then execute management and control operation on the related data of the counter recorded in the external memory. Therefore, the CPU core in the network chip can realize the control of the statistical data in the network chip without participation, so that the business service work of the CPU core in the network chip is not delayed, namely, the efficient control of the statistical data in the network chip is realized.
Optionally, when the CPU controller sends a control instruction to the network chip, the CPU controller may implement the following process, where when related data of a counter in the network chip needs to be controlled, the control instruction is sent to the communication channel to be converted into a control packet, and sent to the cache module in the network chip, where the control packet includes the control instruction.
Specifically, the implementation of the above process may refer to the related description of the CPU controller in the data management and control system, which is not described in detail herein.
Optionally, the CPU controller comprises a buffer area, on the basis of the buffer area, the data management and control method further comprises the steps that the CPU controller caches the management and control instruction into the buffer area, and reads a management and control result from the buffer area, wherein the management and control result is obtained after the kernel in the network chip reads the management and control instruction from the buffer area and forwards the management and control instruction to the statistics counting module, and the statistics counting module executes the management and control instruction.
Specifically, the implementation of the above process may refer to the related description of the CPU controller in the data management and control system, which is not described in detail herein.
Based on the same inventive concept, the embodiment also provides a data management and control method which is applied to a network chip, wherein the network chip is connected with a CPU controller and comprises a statistics counting module, and the statistics counting module is externally connected with an external memory. On the basis, the data management and control method can be implemented according to the following processes when the network chip executes the data management and control method, wherein the control and control instructions are sent by the CPU controller, and the statistics counting module executes the management and control operation on the relevant data of the counter in the external memory based on the control and control instructions.
By implementing the data management and control method, when the CPU controller needs to manage the data in the network chip detected by the statistics and counting module by using the counter, a management and control instruction can be sent to the network chip, and after the network chip receives the management and control instruction, the management and control instruction can be sent to the statistics and counting module, so that the statistics and counting module can access the external memory based on the received management and control instruction, and then execute management and control operation on the related data of the counter recorded in the external memory. Therefore, the CPU core in the network chip can realize the control of the statistical data in the network chip without participation, so that the business service work of the CPU core in the network chip is not delayed, namely, the efficient control of the statistical data in the network chip is realized.
Optionally, the network chip further comprises a buffer module, the CPU controller is connected with the buffer module through a communication channel, and on the basis, the control instruction sent by the CPU controller can be received according to the following process, wherein the buffer module receives a control message, the control message is obtained by converting the control instruction after the CPU controller sends the control message to the communication channel, and the control instruction analyzed from the control message is sent to the statistics counting module.
Specifically, the implementation of the above-mentioned process may refer to the relevant description of the cache module and the statistics counting module in the network chip in the data management and control system with respect to the above-mentioned process, which is not described in detail herein.
Optionally, the control instruction in this embodiment includes a target counter identifier, and on the basis of the control instruction, the statistics counting module may execute a step of performing a control operation on relevant data of a counter in an external memory according to the control instruction, where after the control message is received, the control instruction is parsed from the control message, the target counter identifier is parsed from the control instruction, and the control operation is performed on the basis of the data recorded in a storage space corresponding to the target counter identifier in the external memory.
Specifically, the implementation of the above-mentioned process may refer to a related description of the statistical counting module in the network chip of the data management and control system with respect to the above-mentioned process, which is not described in detail herein.
Optionally, the network chip further comprises at least one CPU core, the CPU controller further comprises a buffer area, on the basis of the buffer area, the data management and control method further comprises the steps that the CPU core in the network chip accesses the buffer area in the CPU controller, after the management and control instruction is read, the management and control instruction is sent to the statistics counting module, when the management and control result exists in the management and control operation executed by the statistics counting module, the management and control result is sent to the CPU core in the network chip, and the CPU core writes the management and control result into the buffer area of the CPU controller.
Specifically, the implementation of the above-mentioned process may refer to the relevant description of the CPU core and the statistics counting module in the network chip in the data management and control system with respect to the above-mentioned process, which is not described in detail herein.
Further, the control operation can be performed based on the control instruction according to the method that the statistics counting module analyzes the target counter identification from the control instruction and performs the control operation based on the data recorded in the storage space corresponding to the target counter identification in the external memory.
Specifically, the implementation of the above-mentioned process may refer to a related description of the statistical counting module in the network chip of the data management and control system with respect to the above-mentioned process, which is not described in detail herein.
Optionally, the network chip further comprises at least one CPU core, and on the basis of the at least one CPU core, the data management and control method further comprises the steps that when the counter needs to be operated in the service processing process, the CPU core in the network chip sends a data operation instruction to the statistics counting module, the data operation instruction comprises a target counter identifier, and the statistics counting module executes corresponding operation on data in a storage space corresponding to the target counter identifier in the external memory after receiving the data operation instruction.
Specifically, the implementation of the above-mentioned process may refer to the relevant description of the CPU core and the statistics counting module in the network chip in the data management and control system with respect to the above-mentioned process, which is not described in detail herein.
Optionally, the network chip in this embodiment further includes a buffer module, where the buffer module is interposed between a CPU core in the network chip and the statistics counting module, and a first clock synchronization module and a second clock synchronization module are configured between the buffer module and the statistics counting module. On the basis, the method can be used for sending the control instruction or the data operation instruction to the statistics counting module according to the following method that the first clock synchronization module receives the control instruction or the data operation instruction sent by the cache module, performs clock domain conversion processing on the control instruction or the data operation instruction, and sends the converted control instruction or data operation instruction to the statistics counting module.
On the basis, the control message can be sent to the statistics counting module according to the following method, namely, after the control message sent by the caching module is received, clock domain conversion processing is carried out on the control message, and the converted control message is sent to the statistics counting module.
On the basis, when the statistics counting module executes corresponding operations based on the control instruction, the control message and the data operation instruction to generate a control result, the data control method provided by the embodiment further comprises the steps that the second clock synchronization module receives the control result sent by the statistics counting module, clock domain conversion processing is conducted on the control result, and the converted control result is sent to the cache module.
Specifically, the implementation of the above-mentioned process may refer to a related description of the above-mentioned process by the first clock synchronization module and the second clock synchronization module in the network chip in the data management and control system, which is not described in detail herein.
Optionally, the statistics counting module provided in this embodiment further includes a scheduling unit, a command buffering unit, and an executing unit, where the scheduling unit is in communication with the command buffering unit, and the command buffering unit is connected to the executing unit. On the basis, the data management and control method can be executed according to the following processes that a scheduling unit receives a management and control instruction and sends a cache request to a command cache unit to cache the management and control instruction in the command cache unit, the command cache unit inserts the management and control instruction into a connection table corresponding to a counter indicated by the management and control instruction after receiving the management and control instruction, the executing unit reads the management and control instruction from the command cache unit, analyzes a counter identifier from the read management and control instruction, and executes the operation indicated by the management and control instruction on data in a storage space corresponding to the counter identifier in the external memory.
In particular, the implementation of the above-mentioned process may refer to the relevant description of the above-mentioned units in the network chip of the data management and control system, which is not described in detail herein.
Optionally, the control instruction recorded in the connection table in this embodiment is written in time sequence, and the statistics counting module further includes a cache, and the control instruction includes a target counter identifier. On the basis of the data management and control method, the data management and control method further comprises the steps that a scheduling unit sends a cache address of a management and control instruction to a cache, wherein the cache address is an idle address which is written into a previous management and control instruction and sent to the scheduling unit by a command cache unit, the cache address received by the cache and pre-read initial data from an external memory, an executing unit reads the management and control instruction from the command cache unit and analyzes a target counter identifier from the read management and control instruction, whether data corresponding to the target counter identifier exist or not is inquired from the cache based on the target counter identifier, and if the data corresponding to the target counter identifier exist, the operation indicated by the management and control instruction is executed by the data corresponding to the target counter identifier in the cache.
In addition, the cache can also store and read initial data from an external memory, and can also cache data generated by the execution unit executing the control instruction and the like, and the cache is specific to the actual situation.
In particular, the implementation of the above-mentioned process may refer to the relevant description of the above-mentioned units in the network chip of the data management and control system, which is not described in detail herein.
By implementing the data management and control system and the data management and control method provided by any embodiment of the application, the operation efficiency and forwarding performance of the network chip can be greatly improved. And when the network chip runs a plurality of service programs, all CPU cores can be used for bearing the service without processing state monitoring data in the service flow. The state statistical data in the service operation is monitored and controlled by the CPU controller in a bypass mode. Therefore, by independent status supervision from traffic, the network chip can carry more traffic, and the CPU controller can also manage multiple network chips simultaneously. In addition, a large amount of statistical data for monitoring the running state of the network chip is returned to the CPU controller, and the network chip is not needed for management and control, so that the design complexity and the workload of the network chip are reduced, and the memory utilization rate of the processing service of the network chip is improved.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The implementation process of the functions and roles of each unit/module in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be repeated here.
For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The above described apparatus embodiments are merely illustrative, wherein the units/modules illustrated as separate components may or may not be physically separate, and the components shown as units/modules may or may not be physical units/modules, i.e. may be located in one place, or may be distributed over a plurality of network units/modules. Some or all of the units/modules may be selected according to actual needs to achieve the purposes of the present solution. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110711153.7A CN113485749B (en) | 2021-06-25 | 2021-06-25 | Data control system and data control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110711153.7A CN113485749B (en) | 2021-06-25 | 2021-06-25 | Data control system and data control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113485749A CN113485749A (en) | 2021-10-08 |
| CN113485749B true CN113485749B (en) | 2025-10-28 |
Family
ID=77937577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110711153.7A Active CN113485749B (en) | 2021-06-25 | 2021-06-25 | Data control system and data control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113485749B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116319464B (en) * | 2023-03-16 | 2024-02-06 | 南京金阵微电子技术有限公司 | Network message flow statistics method, system, storage medium and electronic equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105207794A (en) * | 2014-06-05 | 2015-12-30 | 中兴通讯股份有限公司 | Statistics counting equipment and realization method thereof, and system with statistics counting equipment |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6697371B1 (en) * | 1999-06-01 | 2004-02-24 | Advanced Micro Devices, Inc. | Network switch with on-board management information based (MIB) counters |
| US8339951B2 (en) * | 2010-07-28 | 2012-12-25 | Hewlett-Packard Development Company, L.P. | Method for configuration of a load balancing algorithm in a network device |
| CN102752196A (en) * | 2012-06-19 | 2012-10-24 | 中兴通讯股份有限公司 | Statistical information transmitting and counting method and device |
| US20180150256A1 (en) * | 2016-11-29 | 2018-05-31 | Intel Corporation | Technologies for data deduplication in disaggregated architectures |
| US10506044B1 (en) * | 2016-12-27 | 2019-12-10 | Amazon Technologies, Inc. | Statistics collecting architecture |
| CN111046072A (en) * | 2019-11-29 | 2020-04-21 | 浪潮(北京)电子信息产业有限公司 | A data query method, system, heterogeneous computing acceleration platform and storage medium |
-
2021
- 2021-06-25 CN CN202110711153.7A patent/CN113485749B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105207794A (en) * | 2014-06-05 | 2015-12-30 | 中兴通讯股份有限公司 | Statistics counting equipment and realization method thereof, and system with statistics counting equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113485749A (en) | 2021-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111949568B (en) | Message processing method, device and network chip | |
| CN108920153B (en) | Docker container dynamic scheduling method based on load prediction | |
| US12166844B2 (en) | Intelligent scheduling apparatus and method | |
| CN108667725A (en) | A kind of industrial AnyRouter and implementation method based on a variety of accesses and edge calculations | |
| US20100229182A1 (en) | Log information issuing device, log information issuing method, and program | |
| WO2019223596A1 (en) | Method, device, and apparatus for event processing, and storage medium | |
| CN102662889B (en) | Interruption processing method, interrupt control unit and processor | |
| US20240340343A1 (en) | Data processing system and method and device | |
| CN117971748A (en) | A communication method, conversion circuit and computer equipment | |
| US20050125797A1 (en) | Resource management for a system-on-chip (SoC) | |
| CN118897730A (en) | Load balancing method, device, equipment and storage medium based on computing cluster | |
| CN113485749B (en) | Data control system and data control method | |
| US11050653B2 (en) | Telemetry capture system for storage systems | |
| CN116610443A (en) | Log collection method, device and readable storage medium | |
| US10318362B2 (en) | Information processing apparatus, information processing method, and non-transitory computer-readable storage medium | |
| CN112532470B (en) | Method and system for actively reporting log information by BMC | |
| CN112035460A (en) | An identification distribution method, apparatus, device and storage medium | |
| CN116414534A (en) | Task scheduling method, device, integrated circuit, network equipment and storage medium | |
| CN114116645A (en) | Log management method and device for multi-processing unit, storage medium and electronic equipment | |
| CN117332881B (en) | Distributed training method and electronic equipment | |
| US9338219B2 (en) | Direct push operations and gather operations | |
| CN113886050B (en) | Pressure testing method, device, equipment and storage medium | |
| WO2024087663A1 (en) | Job scheduling method and apparatus, and chip | |
| CN116684496A (en) | Cluster resource management method, device, equipment and medium | |
| CN108847975A (en) | Communication means, device, computer equipment and medium based on NFV framework |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |