CN113472308B

CN113472308B - Resonator, forming method thereof and electronic equipment

Info

Publication number: CN113472308B
Application number: CN202110475611.1A
Authority: CN
Inventors: 张孟伦; 杨清瑞; 宫少波
Original assignee: Guangzhou Leyi Investment Co ltd
Current assignee: Shenzhen Weihai Zhixin Technology Co.,Ltd.
Priority date: 2021-04-29
Filing date: 2021-04-29
Publication date: 2022-11-22
Anticipated expiration: 2041-04-29
Also published as: CN113472308A

Abstract

The invention discloses a resonator, a forming method thereof and an electronic device. The method comprises the following steps: for an SOI wafer comprising a top silicon layer, a buried oxide layer and a bottom silicon layer, sequentially forming a patterned piezoelectric layer and a bottom electrode on the top silicon layer; bonding the current semiconductor structure on the lower silicon cap after inverting, wherein a lower cavity is formed between the current semiconductor structure and the lower silicon cap; removing the bottom silicon layer; forming a beam structure, wherein the top silicon layer serves as a driven layer of the beam structure; and bonding the upper silicon cap to the current semiconductor structure, wherein an upper cavity is formed between the current semiconductor structure and the upper silicon cap. The method adopts the technology of bonding the inverted device to realize the packaging of the vacuum cavity of the resonator, thereby avoiding the use of the SOI silicon chip with the cavity and greatly reducing the cost. Meanwhile, the stress problems caused by the fact that the top silicon of the cavity SOI is bent to be flat after being formed and the bottom silicon and the buried oxide layer are bonded hard are solved.

Description

Resonator, forming method thereof and electronic device

Technical Field

The invention relates to the technical field of micro/nano electromechanical systems, in particular to a resonator, a forming method thereof and electronic equipment.

Background

At present, most of devices with cantilever beams, such as resonators, are made of SOI silicon chips with cavities. Taking a resonator as an example, the beam in the conventional process is generally manufactured as follows: and sequentially depositing and patterning a lower electrode, a piezoelectric layer and an upper electrode on the SOI with the cavity, etching away the free end of the beam and the top silicon and buried oxide layers on two sides to form the beam, and finally packaging in a bonded silicon cap mode. There are many disadvantages in this process, first, as shown in fig. 1, because the pressure in cavity 1004 of cavity SOI is low, top silicon 1001 on cavity 1004 will be recessed under atmospheric pressure, and the device fabricated on cavity 1004 will bend accordingly; when the cavity 1004 is vented to atmosphere after the beam is formed as in fig. 2, the top silicon 1001 and buried oxide 1002 tend to return to a flat state while the initial state of the

electrode layers

1005, 1007 and piezoelectric layer 1006 are in a curved state, thus creating a large stress between the top silicon 1001 and piezoelectric layer 1006 during this process. This stress will result in a reduction of the device quality factor Q. Secondly, because silicon and silicon oxide are hard materials in the SOI manufacturing process, the two hard materials are bonded to form larger stress; although the cantilever is formed, its fixed end is fixed on the base silicon 1003 by the original silicon-silicon oxide bond interface of the SOI, so the parasitic stress in the SOI severely affects the performance of the device. Finally, the SOI wafer with the cavity is very expensive due to the fact that the SOI with the cavity is difficult in processing technology and long in manufacturing period, and therefore the process cost of the SOI with the cavity is high. Therefore, the device manufactured by using the SOI with cavity and the conventional packaging process is difficult to further improve the quality factor and has high cost, which becomes a key obstacle for realizing the product commercialization.

Disclosure of Invention

In view of the above, the present invention provides a resonator capable of the above technical drawbacks, a method of manufacturing the same, and an electronic device including the resonator.

A first aspect of the present invention provides a method of forming a resonator having a beam structure, the method comprising: sequentially forming a patterned piezoelectric layer and a bottom electrode on a top silicon layer of an SOI wafer comprising the top silicon layer, a buried oxide layer and a bottom silicon layer; bonding the current semiconductor structure on a lower silicon cap after inverting, wherein a lower cavity is formed between the current semiconductor structure and the lower silicon cap; removing the bottom silicon layer; forming the beam structure, wherein the top silicon layer serves as a driven layer of the beam structure; and bonding an upper silicon cap to the current semiconductor structure, wherein an upper cavity is formed between the current semiconductor structure and the upper silicon cap.

Optionally, after the step of forming the beam structure and before the step of bonding the upper silicon cap to the current semiconductor structure, further comprising: and removing the buried oxide layer above the beam structure.

Optionally, the beam structure is a cantilever beam or a clamped beam, or a multi-beam structure including a cantilever beam or a clamped beam.

Optionally, the beam structure and the upper silicon cap and the beam structure and the lower silicon cap are connected by bonding.

Optionally, after the step of removing the bottom silicon layer and before the step of forming the beam structure, further comprising: forming an electrode connection through the top silicon layer and the buried oxide layer; and, after the step of bonding the upper silicon cap to the present semiconductor structure, further comprising: forming an upper metal connection region in said upper silicon cap, wherein said upper metal connection region is in contact with said electrode connection.

Optionally, before the step of bonding the current semiconductor structure to the lower silicon cap after inverting, the method further comprises: forming a lower metal connection region in the lower silicon cap; and the step of bonding the current semiconductor structure to the lower silicon cap after being inverted comprises the following steps: after inverting the current semiconductor structure, a top electrode and/or a bottom electrode of the semiconductor structure is connected to the lower metal connection region.

Optionally, the method further comprises: and forming a getter layer on the inner side of the upper silicon cap and/or the inner side of the lower silicon cap.

Optionally, before the step of forming the piezoelectric layer, the method further includes: a patterned top electrode is formed over the top silicon layer.

Optionally, the top silicon layer is doped silicon with a doping concentration greater than 10 ¹⁹ cm ^-3 。

Optionally, the height of the upper cavity and the lower cavity is: 10 to 200 microns, or, 20 to 100 microns.

A second aspect of the present invention provides a resonator comprising: a resonator, comprising: a beam structure comprising, from top to bottom, a driven layer, a piezoelectric layer, and a bottom electrode, wherein the driven layer comprises a silicon layer; a lower silicon cap, wherein a lower cavity is formed between the lower silicon cap and the beam structure; and an upper silicon cap, wherein an upper cavity is formed between the upper silicon cap and the beam structure.

Optionally, the method further comprises: and the oxygen burying layer is positioned above the driven layer.

Optionally, a first bonding layer is arranged between the beam structure and the upper silicon cap, and a second bonding layer is arranged between the beam structure and the lower silicon cap.

Optionally, the first bonding layer or/and the second bonding layer is a metal bonding layer.

Optionally, the method further comprises: an electrode connection through the top silicon layer; and an upper metal connection region in the upper silicon cap, wherein the upper metal connection region is in connection contact with the electrode.

Optionally, the method further comprises: a lower metal connection region in the lower silicon cap, the lower metal connection region in contact with a top electrode and/or a bottom electrode of the beam structure.

Optionally, the method further comprises: and the air suction layer is positioned on the inner side of the upper silicon cap and/or the inner side of the lower silicon cap.

Optionally, the method further comprises: a top electrode located between the driven layer and the piezoelectric layer.

A third aspect of the present invention provides an electronic device, including the resonator disclosed in the present invention.

According to the technical scheme of the invention, the common SOI silicon chip is adopted, and the use of the cavity SOI silicon chip is avoided. The inverted packaging technology reduces the cost, and simultaneously, because the common SOI is directly used for replacing the SOI with the cavity, the bending phenomenon does not exist in the cantilever beam manufacturing process, thereby avoiding the stress problem caused by the formation of the cavity SOI. Second, the SOI base silicon is completely removed in the present example, thus eliminating stress problems due to the silicon oxide-silicon hard bond. The material with better toughness is adopted as the bonding layer between the fixed ends of the cantilever beam and the substrate, for example, the gold is made of a material, and because the gold has ductility, the coupling of external stress to the cantilever beam is effectively reduced compared with hard bonding. Because the stress is greatly reduced, the quality factor of the device is obviously improved, and meanwhile, the device is not interfered by external stress, and the stability is improved. And finally, the two cavities are etched by silicon, the height of the cavities is controllable, and the limitation of the cavity height of the SOI with the cavities is avoided.

Drawings

For purposes of illustration and not limitation, the present invention will now be described in accordance with its preferred embodiments, particularly with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a prior art SOI wafer with a cavity;

FIG. 2 is a schematic diagram of a prior art SOI silicon wafer with a cavity after a cantilever beam is formed;

fig. 3 to 11 are process diagrams illustrating a method for forming a resonator having a cantilever according to a first embodiment of the present invention;

figure 12 is a cross-sectional schematic view of a resonator with a cantilever beam according to a second embodiment of the present invention;

figure 13 is a cross-sectional schematic view of a resonator with a cantilever beam according to a third embodiment of the present invention;

figure 14 is a cross-sectional schematic view of a resonator with a cantilever beam according to a fourth embodiment of the present invention;

fig. 15 is a schematic cross-sectional view of a resonator having a clamped beam according to a fifth embodiment of the present invention.

Detailed Description

In the forming method of the resonator of the embodiment of the invention, the device is inverted and bonded to realize the packaging technology of the vacuum cavity of the resonator, and the technology avoids the use of an SOI silicon chip with a cavity and reduces the cost. Meanwhile, the stress problems caused by the fact that the cavity SOI top silicon is bent to be flat after being formed and the bottom silicon and the buried oxide layer are hard bonded are solved.

The structure and materials of the parts in the drawings are described as follows:

100: a silicon-on cap comprising:

101: the upper substrate is made of monocrystalline silicon, polycrystalline silicon, glass or quartz.

102: the upper insulating layer is made of silicon oxide, aluminum nitride, aluminum oxide and the like.

103a: the specific material of the upper metal connecting region can be selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a composite of the above metals or an alloy thereof.

103b: the specific material of the upper isolating layer can be silicon oxide, aluminum nitride, aluminum oxide and the like.

It is to be noted that the upper metal connection region 103a and the upper isolation layer 103b are not necessarily required to have an optional structure. In other embodiments (e.g., fig. 12) where the electrodes are extracted from the lower silicon cap, 103a and 103b may be omitted and instead a lower metal connection region 403a (which is the same material and function as 103 a) and a lower isolation layer 403b (which is the same material and function as 103 b) may be provided.

200: the beam structure may be a cantilever beam or a clamped beam, or a multi-beam structure including a cantilever beam or a clamped beam, for example: a tuning fork type structure formed by combining two cantilever beams or a comb-shaped structure formed by combining a plurality of cantilever beams. The beam structure 200 may specifically include:

201a: and a top silicon layer, wherein the material can be monocrystalline silicon, aluminum nitride, gallium arsenide, sapphire and the like. Note that the top silicon layer 201a is from an initially provided SOI wafer. The SOI wafer also includes a buried oxide layer 201b and a bottom silicon layer 201c. Wherein the bottom silicon layer 201c needs to be removed during processing. The buried oxide layer 201b may be removed or retained according to device requirements. The buried oxide layer, when not removed, may be present in the device as a temperature compensation layer. The specific principle is as follows: since the buried oxide layer (silicon dioxide) usually has a positive temperature coefficient, while ordinary silicon (doping concentration less than 10) ¹⁹ cm ^-3 ) The piezoelectric layer (such as AlN) and the electrode layer (Mo) generally have negative temperature coefficients, so that the frequency temperature coefficient of the whole device shows a negative temperature coefficient when the buried oxide layer is not arranged, and the temperature drift characteristic of the device can be improved (namely, the drift of the frequency of the device along with the temperature is reduced) when the buried oxide layer is reserved.

The first-order temperature drift coefficient of the device can be close to 0 by selecting or adjusting the thickness of the buried oxide layer.

202: the top electrode is made of molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, and iridiumOsmium, chromium or a composite of the above metals or an alloy thereof, and also can adopt a non-metallic conductive material doped with silicon and the like. The top electrode 202 is an optional structure when the top silicon layer 201a is doped silicon with a doping concentration greater than 10 ¹⁹ cm ^-3 And may function directly as an electrode, in which case the top electrode 202 may be omitted.

203: the piezoelectric layer can be made of materials such as aluminum nitride, zinc oxide, PZT and the like, and contains rare earth element doping materials with certain atomic ratios of the materials.

204: the bottom electrode is made of the same material as the top electrode 202.

300: a cavity, comprising: an upper cavity 301 and a lower cavity 302.

400: a lower silicon cap comprising:

401: the lower substrate is made of the same material as the upper substrate 101.

402: the lower insulating layer is made of the same material as the upper insulating layer 102.

In some embodiments (e.g., fig. 12), a lower metal connection region 403a (which is the same material and function as 103 a) and a lower isolation layer 403b (which is the same material and function as 103 b) may also be included in the lower silicon cap.

500: the bonding layer is generally made of gold, and may be made of other metals, silicon dioxide, high polymer, and other common bonding materials. It should be noted that the bonding layer 500 may be specifically subdivided into a first bonding layer located between the beam structure 200 and the upper silicon cap 100, and a second bonding layer located between the beam structure 200 and the lower silicon cap 400. For the sake of simplicity, the first bonding layer and the second bonding layer are not separately labeled in the drawings of the specification.

Optionally, the first bonding layer or/and the second bonding layer is a metal bonding layer. The concrete conditions are as follows: (1) If the resonator is designed to have an electrode led out from the upper silicon cap 100, the first bonding layer may be a metal bonding layer, and the second bonding layer may be Si — SiO ₂ Or a non-metallic bonding layer of Si-Si, or a metallic bonding layer; (2) If the resonator is designed to lead out the electrode from the lower silicon cap 400, the second bonding layer is a metal bonding layer, and the first bonding layer may be Si-SiO ₂ Or a non-metallic bonding layer of Si-Si, a metallic bonding layer may also be employed.

600: the specific material of the electrode connection can be selected from molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or the compound of the above metals or the alloy thereof.

700: the specific material of the getter layer can be selected from titanium (Ti) and titanium alloy, zirconium (Zr) and zirconium alloy.

The present invention will be further described with reference to the accompanying drawings. It should be noted that these examples are provided to illustrate the present invention and are not intended to limit the scope of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 3 to 11 are process diagrams illustrating a method for forming a resonator with a cantilever according to a first embodiment of the present invention, and the specific process flow is as follows (the parts in this patent are illustrated by taking one possible material as an example, but not limited thereto).

Step 1: a top electrode is deposited over an SOI wafer.

Specifically, as shown in fig. 3, an SOI wafer is provided that includes a top silicon layer 201a, a buried oxide layer 201b, and a bottom silicon layer 201c. Molybdenum is deposited on the top silicon layer 201a, and then the molybdenum electrode is etched by using the patterned photoresist as a mask to be patterned, so that the top electrode 202 is obtained. It should be noted that this step is optional. When the top silicon layer 201a is doped silicon with a doping concentration greater than 10 ¹⁹ cm ^-3 It may be used directly as an electrode, omitting the process of forming the top electrode 202.

Step 2: a piezoelectric layer and a bottom electrode are deposited.

Specifically, as shown in fig. 4, a layer of aluminum nitride is deposited, silicon oxide is deposited on the aluminum nitride, wet etching is performed on the silicon oxide using the photoresist as a mask, and then dry etching is performed on the aluminum nitride using the silicon oxide as a hard mask to pattern the aluminum nitride, so as to obtain the piezoelectric layer 203. Then, a bottom electrode 204 is formed on the piezoelectric layer 203, and the process of forming the top electrode 202 is referred to in step 1.

And step 3: and manufacturing a lower silicon cap.

Specifically, as shown in fig. 5, a silicon wafer is first re-taken, the silicon wafer includes a lower silicon substrate 401 and a lower insulating layer 402, a layer of aluminum nitride is deposited on the silicon wafer and patterned, then the patterned aluminum nitride is used as a mask, the silicon is dry etched to form a lower cavity 302, the aluminum nitride is then removed, and finally a layer of gold is deposited and patterned for subsequent bonding. This results in the lower silicon cap 400. Wherein the height of the lower cavity may be 10 to 200 micrometers, or, 20 to 100 micrometers.

And 4, step 4: and (5) packaging in an inverted mode.

Specifically, as shown in fig. 6, the structure obtained in step 2 is vertically turned over and covered on the lower silicon cap 400 obtained in step 3, and then bonding connection is performed. A material with better toughness may be used as the bonding layer 500 between the top silicon layer 201a and the fixed end of the contact position of the lower silicon cap 400, which effectively reduces the coupling between the external stress and the top silicon layer 201a compared to a hard connection. The bonding on at least one side can be selected from metal bonding, and is generally a gold-gold combination, and can also be other metal combinations, such as: aluminum-germanium, copper-copper, copper-gold-copper, gold-tin-copper, and the like. Non-metal bonding methods such as silicon dioxide and high polymer can also be selected.

And 5: and removing the bottom silicon layer.

Specifically, as shown in fig. 7, the bottom silicon layer 201c is completely etched away by dry etching.

And 6: and manufacturing an electric connection through hole.

Specifically, as shown in fig. 8, a patterned aluminum nitride layer is deposited first, then the top silicon layer is dry-etched using the aluminum nitride as a mask to obtain a through hole 600a, then the aluminum nitride is removed, and then the inner wall of the through hole 600a is oxidized to prevent the subsequent electrical connection from being shorted by polysilicon.

And 7: and making electrode connection.

Specifically, as shown in fig. 9, first, depositing metal copper until the through hole 600a is filled, and then removing the copper on the upper surface with a copper etching solution, so that only the copper inside the through hole remains; gold is then deposited and patterned. Thus, an electrode connection 600 was obtained.

And 8: forming a cantilever beam and removing the buried oxide layer.

Specifically, as shown in fig. 10, first, the photoresist is used as a mask, and HF is used as an etchant to etch the buried oxide layer 201b of the silicon oxide material; then, using the patterned silicon oxide as a hard mask, performing dry etching at a position of a preset free end of the cantilever beam (i.e., position a in fig. 9) until the top silicon layer is etched through to form a gap (i.e., gap B in fig. 10), thereby forming the cantilever-beam-shaped beam structure 200, where a left end (as viewed in the drawing) of the cantilever-beam-shaped beam structure 200 is the free end of the cantilever-beam-shaped beam structure 200. Then, the buried oxide layer 201b of the silicon oxide material on the upper part of the cantilever beam structure 200 is removed by BOE etching using the photoresist as a mask. The top silicon layer 201a now becomes the driven layer of the beam structure 200 in the form of a cantilever beam.

And step 9: and (7) bonding and packaging.

Specifically, as shown in fig. 11, the upper silicon cap 100 fabricated in advance is placed on the semiconductor structure obtained in step 8, and bonding packaging is performed, and an upper cavity 301 is formed between the semiconductor structure and the upper silicon cap 100. Wherein the height of the upper cavity may be 10 to 200 micrometers, or 20 to 100 micrometers. Wherein the upper silicon cap 100 and the lower silicon cap 400 have an upper metal connection region 103a and an upper isolation layer 103b on the right side added. The fabrication process of the upper silicon cap can be based on the fabrication process of the lower silicon cap 100. The upper metal connection region 103a and the upper isolation layer 103b are then formed as described with reference to steps 6 and 7. The silicon cap 100 can be bonded by Au-Au bonding, al-Ge bonding, cu-Au-Cu bonding or other polymer bonding.

Example 2

Fig. 12 is a cross-sectional view of a resonator having a cantilever beam according to a second embodiment of the present invention. As shown in fig. 12, the present embodiment is different from embodiment 1 in that: the working electrode is not led out from the upper silicon cap 100 but from the lower silicon cap 400. In this embodiment, the through hole 600a and the metal connection 600 in the through hole do not need to be made in the top silicon layer 201a, thereby simplifying the process and reducing the cost; and because heterostructures are avoided in the top silicon layer 201a, the existence of stress is further reduced, resulting in a further improvement in the quality factor of the device.

Example 3

Fig. 13 is a cross-sectional view of a resonator having a cantilever beam according to a third embodiment of the present invention. As shown in fig. 13, the present embodiment is different from embodiment 1 in that: the working electrode is led out of the lower silicon cap 400; the metal connections 600 in the top silicon layer 201a are no longer used to pull the working electrodes of the beam structure out of the upper silicon cap 100, but are used as test electrodes to facilitate wafer level testing and frequency tuning operation detection prior to the silicon cap on device packaging.

Example 4

Figure 14 is a cross-sectional schematic view of a resonator with a cantilever beam of a fourth embodiment of the present invention. As shown in fig. 14, the present embodiment is different from embodiment 1 in that: a getter layer 700 is provided on the inner side of the lower silicon cap 400. In other embodiments, the gettering layer 700 may also be disposed only inside the upper silicon cap 100, or both inside the upper silicon cap 100 and inside the lower silicon cap 400. The air suction layer is used for absorbing gaseous molecules in the cavity and slowing down vacuum degree drift in the cavity caused by air release of the bonding material and air leakage of a bonding interface, so that the device obtains high quality factor and better reliability. In conventional devices fabricated using cavity SOI, the gettering layer 700 can only be placed on the inside of the upper silicon cap 100. In the embodiment of the invention, the inverted packaging technology is adopted, so that the air suction layer can be more flexibly arranged.

Example 5

Fig. 15 is a schematic cross-sectional view of a resonator having a clamped beam according to a fifth embodiment of the present invention. As shown in fig. 15, the present embodiment is different from embodiment 1 in that: in this embodiment, the cantilever beam structure shown in embodiment 1 is not provided, and both the left and right ends of the beam structure 200 are not opened, but only both sides of the beam structure 200 are opened. In other words, the present embodiment employs the beam structure 200 in the form of a clamped beam. Clamped beam structures have a higher resonant frequency than cantilever beam structures and are advantageous for applications at high frequencies. It should be noted that the electrodes of the resonator in fig. 15 are led out from the upper silicon cap, which is only for example and not limited. In other embodiments, the resonator with clamped beams may be led out from the lower silicon cap similar to that shown in fig. 13, and details are not repeated.

The electronic equipment of the embodiment of the invention comprises any resonator disclosed by the invention.

According to the technical scheme of the embodiment of the invention, the resonator is made of a common SOI silicon chip, so that the use of a cavity SOI silicon chip is avoided. The inverted packaging technology reduces the cost, and simultaneously, because the common SOI is directly used for replacing the SOI with the cavity, the bending phenomenon does not exist in the cantilever beam manufacturing process, thereby avoiding the stress problem caused by the formation of the cavity SOI. Second, the SOI base silicon is completely removed in the present example, thus eliminating the stress problem due to the silicon oxide-silicon hard bond. The material with better toughness is adopted as the bonding layer between the fixed ends of the cantilever beam and the substrate, for example, the gold is made of a material, and because the gold has ductility, the coupling of external stress to the cantilever beam is effectively reduced compared with hard bonding. Because the stress is greatly reduced, the quality factor of the device is obviously improved, and meanwhile, the device is not interfered by external stress, and the stability is improved. And finally, the two cavities are etched by silicon, the height of the cavities is controllable, and the limitation of the cavity height of the SOI with the cavities is avoided.

The above-described embodiments should not be construed as limiting the scope of the invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions can occur, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of forming a resonator having a beam structure, the method comprising:

sequentially forming a patterned piezoelectric layer and a bottom electrode on a top silicon layer of an SOI wafer comprising the top silicon layer, a buried oxide layer and a bottom silicon layer;

bonding the current semiconductor structure on a lower silicon cap after inverting the current semiconductor structure, wherein a lower cavity is formed between the current semiconductor structure and the lower silicon cap;

removing the bottom silicon layer;

forming the beam structure, wherein the top silicon layer serves as a driven layer of the beam structure;

and bonding an upper silicon cap to the current semiconductor structure, wherein an upper cavity is formed between the current semiconductor structure and the upper silicon cap.

2. The method of claim 1, further comprising, after the step of forming the beam structure and before the step of bonding the upper silicon cap to the current semiconductor structure: and removing the buried oxide layer above the beam structure.

3. The method of claim 1, wherein the beam structure is a cantilever beam or a clamped beam, or a multi-beam structure comprising a cantilever beam or a clamped beam.

4. The method of claim 1, wherein the beam structure and the upper silicon cap and the beam structure and the lower silicon cap are bonded together.

5. The method of forming a resonator of claim 1,

after the step of removing the bottom silicon layer and before the step of forming the beam structure, further comprising: forming an electrode connection through the top silicon layer and the buried oxide layer; and the number of the first and second groups,

after the step of bonding the upper silicon cap to the current semiconductor structure, further comprising: forming an upper metal connection region in the upper silicon cap, wherein the upper metal connection region is in contact with the electrode connection.

6. The method of forming a resonator of claim 1,

before the step of bonding the current semiconductor structure to the lower silicon cap after being inverted, the method further comprises the following steps: forming a lower metal connection region in the lower silicon cap; and (c) a second step of,

the step of bonding the current semiconductor structure to the lower silicon cap after being inverted comprises the following steps: after inverting the current semiconductor structure, a top electrode and/or a bottom electrode of the semiconductor structure is connected to the lower metal connection region.

7. The method of forming a resonator according to claim 1, further comprising:

and forming a getter layer on the inner side of the upper silicon cap and/or the inner side of the lower silicon cap.

8. The method of forming a resonator of claim 1, further comprising, prior to the step of forming the piezoelectric layer: a patterned top electrode is formed over the top silicon layer.

9. The method of claim 1, wherein the top silicon layer is doped silicon and has a doping concentration greater than 10 ¹⁹ cm ^-3 。

10. The method of forming a resonator according to any of claims 1 to 9, wherein the height of the upper and lower cavities is: 10 to 200 microns.

11. A resonator, comprising:

a beam structure comprising, from top to bottom, a driven layer, a piezoelectric layer, and a bottom electrode, wherein the driven layer comprises a silicon layer;

a lower silicon cap, wherein a lower cavity is formed between the lower silicon cap and the beam structure;

an upper silicon cap, an upper cavity is formed between the upper silicon cap and the beam structure,

and a first bonding layer is arranged between the beam structure and the upper silicon cap, and a second bonding layer is arranged between the beam structure and the lower silicon cap.

12. The resonator of claim 11, further comprising: and the oxygen burying layer is positioned above the driven layer.

13. The resonator according to claim 11, characterized in that the beam structure is a cantilever beam or a clamped beam, or a multi-beam structure comprising a cantilever beam or a clamped beam.

14. The resonator according to claim 13, characterized in that the first or/and the second bonding layer is a metal bonding layer.

15. The resonator of claim 11, further comprising: an electrode connection through the driven layer; and an upper metal connection region in the upper silicon cap, wherein the upper metal connection region is in connection contact with the electrode.

16. The resonator of claim 11, further comprising: a lower metal connection region in the lower silicon cap, the lower metal connection region in contact with a top electrode and/or a bottom electrode of the beam structure.

17. The resonator of claim 11, further comprising: and the air suction layer is positioned on the inner side of the upper silicon cap and/or the inner side of the lower silicon cap.

18. The resonator of claim 11, further comprising: a top electrode positioned between the driven layer and the piezoelectric layer.

19. The resonator of claim 11, wherein the driven layer is doped silicon and has a doping concentration greater than 10 ¹⁹ cm ^-3 。

20. The resonator according to any of claims 11-19, characterized in that the height of the upper and lower cavities is: 10 to 200 microns.

21. An electronic device, characterized in that it comprises a resonator according to any of claims 11 to 20.