CN113471206A

CN113471206A - Multi-time programmable memory structure and manufacturing method thereof

Info

Publication number: CN113471206A
Application number: CN202111036001.8A
Authority: CN
Inventors: 秋珉完; 金起凖
Original assignee: Jingxincheng Beijing Technology Co Ltd
Current assignee: Jingxincheng Beijing Technology Co Ltd
Priority date: 2021-09-06
Filing date: 2021-09-06
Publication date: 2021-10-01

Abstract

The invention provides a multi-time programmable memory structure and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: a substrate; a floating gate on the substrate; the selection gate is positioned on the substrate and positioned on one side of the floating gate; the gate dielectric layer is positioned on the floating gate; the interlayer dielectric layer is positioned on the substrate, the selection gate and the gate dielectric layer; the first type of conductive plug and the second type of conductive plug are positioned in the interlayer dielectric layer; the first metal layer is positioned on the interlayer dielectric layer and comprises a first metal and a second metal, and the first metal is connected with the gate dielectric layer through a first conductive plug; the second metal is connected with the selection grid through a second type of conductive plug; wherein the radial dimension of the first type of conductive plugs is greater than the radial dimension of the second type of conductive plugs. The multi-time programmable memory structure and the manufacturing method thereof can improve the performance of the device.

Description

Multi-time programmable memory structure and manufacturing method thereof

Technical Field

The invention relates to the field of memories, in particular to a multi-time programmable memory structure and a manufacturing method thereof.

Background

Multi-Time Programmable Memory (MTP) devices have become a widely used Memory device for personal computers and electronic devices because they can perform operations such as data storage, reading, and erasing for many times, and the stored data will not disappear after power is turned off.

Multi-Time Program Memory (MTP) has the advantages that, compared with One-Time programmable Memory (OTP), it can store, read, erase data many times, and the stored data will not disappear after power-off, and has gradually become a Memory device widely used in the fields of personal computers, electronic devices, mobile storage, etc. However, the multi-time programmable memory structure formed by the conventional method has a large size and a poor performance.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides a multiple-time programmable memory structure and a method for manufacturing the same, so as to reduce the size of the multiple-time programmable memory structure and improve the performance of the multiple-time programmable memory.

To achieve the above and other objects, the present invention provides a multiple time programmable memory structure, comprising:

a substrate;

the floating gate is positioned on the substrate, and two sides of the floating gate comprise first side walls;

the selection gate is positioned on the substrate and positioned on one side of the floating gate;

the gate dielectric layer is positioned on the floating gate, extends towards the first side walls on two sides and covers part of the first side walls;

the interlayer dielectric layer is positioned on the substrate, the selection gate and the gate dielectric layer;

the first type of conductive plug and the second type of conductive plug are positioned in the interlayer dielectric layer;

the first metal layer is positioned on the interlayer dielectric layer and comprises a first metal and a second metal, the first metal is connected with the grid dielectric layer through a first conductive plug, and the second metal is connected with the selection grid through a second conductive plug;

wherein the radial dimension of the first type of conductive plugs is greater than the radial dimension of the second type of conductive plugs.

Furthermore, the gate dielectric layer comprises a first material layer and a second material layer, the first material layer is located on the floating gate, and the second material layer is located on the first material layer.

Further, the first material layer is an oxide, and the second material layer is a nitride.

Further, the substrate further comprises a source electrode and a drain electrode, and the floating gate and the selection gate are located between the source electrode and the drain electrode.

Further, the substrate further comprises a shared doped region, and the shared doped region is located between the floating gate and the selection gate.

Further, the first metal layer further includes a third metal and a fourth metal, the third metal is connected to the source through the second type of conductive plug, and the fourth metal is connected to the drain through the second type of conductive plug.

Furthermore, the transistor also comprises a self-aligned metal silicide layer which is respectively positioned on the upper surfaces of the selection gate, the source electrode and the drain electrode.

Further, a gate oxide layer is arranged between the floating gate and the substrate.

Furthermore, two sides of the select gate further include second sidewalls.

Furthermore, the invention also provides a manufacturing method of the multi-time programmable memory structure, which comprises the following steps:

providing a substrate;

forming a gate oxide layer on the substrate;

forming a floating gate on the gate oxide layer, and forming first side walls on two sides of the floating gate;

forming a selection gate on the substrate, wherein the selection gate is positioned on one side of the floating gate;

forming a source electrode and a drain electrode in the substrate, wherein the source electrode and the drain electrode are positioned at two sides of the selection gate and the floating gate;

forming a gate dielectric layer on the floating gate, wherein the gate dielectric layer extends towards the first side walls on two sides and covers part of the first side walls;

forming a self-aligned metal silicide layer on the upper surfaces of the selection gate, the source electrode and the drain electrode;

forming an interlayer dielectric layer on the substrate, the selection gate and the gate dielectric layer;

forming a first type conductive plug and a second type conductive plug in the interlayer dielectric layer;

forming a first metal on the interlayer dielectric layer, wherein the first metal is connected with the gate dielectric layer through the first conductive plug;

forming a second metal on the interlayer dielectric layer, wherein the second metal is connected with the selection gate through the second type of conductive plug;

forming a third metal and a fourth metal on the interlayer dielectric layer, wherein the third metal and the fourth metal are respectively connected with the source electrode and the drain electrode through the second type of conductive plug;

In summary, the present invention provides a multi-time programmable memory structure and a method for manufacturing the same, the multi-time programmable memory structure includes a substrate, the substrate includes a well region, a floating gate and a select gate are formed on the well region, a gate dielectric layer is formed on the floating gate, an interlayer dielectric layer is formed on the substrate, a first metal and a second metal are formed on the interlayer dielectric layer, the first metal is connected to the gate dielectric layer through a first type of conductive plug, the second metal is connected to the select gate through a second type of conductive plug, the radial dimension of the first type of conductive plug is larger than that of the second type of conductive plug, so that the first type of conductive plug can also function as a control gate, the coupling ratio of the multi-time programmable memory can be improved, and meanwhile, the first metal in the multi-time programmable memory performs data storage and erasure through coupling control of the floating gate without an additional tunneling region (i.e. a control gate region), due to the improvement of the coupling ratio, the performance of the multi-time programmable memory is improved.

In summary, the first side walls are formed on the two sides of the floating gate, the gate dielectric layer is formed on the floating gate, the gate dielectric layer extends to the first side walls on the two sides, and covers a part of the first side walls, so that damage to the first side walls when the gate dielectric layer is etched can be reduced or avoided, and the stability of the multi-time programmable memory is improved.

Drawings

FIG. 1: the invention discloses a manufacturing method flow chart of a multi-time programmable memory structure.

FIG. 2: schematic representation of a substrate in the present invention.

FIG. 3: the floating gate and the select gate of the present invention are illustrated.

FIG. 4: the invention discloses schematic diagrams of a first side wall and a second side wall.

FIG. 5: the first doped region, the second doped region and the third doped region are illustrated schematically.

FIG. 6: schematic representation of the first material layer and the second material layer in the present invention.

FIG. 7: schematic illustration of a patterned photoresist layer in the present invention.

FIG. 8: the invention discloses a schematic diagram of a gate dielectric layer.

FIG. 9: the invention is a schematic diagram of a salicide layer.

FIG. 10: the invention is a schematic diagram of forming a self-aligned metal silicide layer.

FIG. 11: the invention is a schematic diagram of an interlayer dielectric layer.

FIG. 12: the invention discloses a schematic diagram of a first contact hole and a second contact hole.

FIG. 13: the invention discloses a schematic diagram of a first type conductive plug and a second type conductive plug.

FIG. 14: top view of a multiple time programmable memory structure of the present invention.

FIG. 15: the multi-time programmable memory structure realizes the schematic diagram of data writing.

FIG. 16: the multi-time programmable memory structure realizes the schematic diagram of data erasure.

10: multiple time programmable memoryReservoir structure, 101: substrate, 102: well region, 103: gate oxide layer, 104: floating gate, 105: select gate, 106: first side wall, 107: second sidewall, 108: first doped region, 109: second doped region, 110: third doped region, 111: first material layer, 112: second material layer, 113: gate dielectric layer, 114: patterned photoresist layer, 115: salicide layer, 116: interlayer dielectric layer, 117: first-type conductive plug, 118: second-type conductive plug, 119: first metal, 120: second metal, 121: third metal, 122: fourth metal, 1051: nickel layer, 1052: ni₂Si layer, 1151: first opening, 1152: second opening, 1161: first contact hole, 1162: second contact hole, d: the gate dielectric layer covers the width of the first side wall.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, this embodiment provides a method for manufacturing a multi-time programmable memory structure, which can reduce the size of the multi-time programmable memory structure and improve the performance of the multi-time programmable memory.

As shown in fig. 1, the method for manufacturing the multi-time programmable memory structure includes:

s1: providing a substrate;

s2: forming a gate oxide layer on the substrate;

s3: forming a floating gate and a selection gate on the substrate;

s4: forming first side walls on two sides of the floating gate, and forming second side walls on two sides of the selection gate;

s5: forming a source electrode and a drain electrode in the substrate, wherein the source electrode and the drain electrode are positioned at two sides of the selection gate and the floating gate;

s6: forming a gate dielectric layer on the floating gate, wherein the gate dielectric layer extends towards the first side walls on two sides and covers part of the first side walls;

s7: forming a self-aligned metal silicide layer on the upper surfaces of the selection gate, the source electrode and the drain electrode;

s8: forming an interlayer dielectric layer on the substrate, the selection gate and the gate dielectric layer;

s9: forming a first type conductive plug and a second type conductive plug in the interlayer dielectric layer;

s10: and forming a first metal layer on the interlayer dielectric layer, wherein the first metal layer comprises a first metal, a second metal, a third metal and a fourth metal, the first metal is connected with the gate dielectric layer through the first type of conductive plug, the second metal is connected with the select gate through the second type of conductive plug, and the third metal and the fourth metal are respectively connected with the source electrode and the drain electrode through the second type of conductive plug.

As shown in fig. 2, in step S1, a substrate 101 is first provided, where the substrate 101 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group III-V compounds such as gallium arsenide. In step S1, a shallow trench isolation structure may be further formed in the substrate 101, an active region is defined in the substrate 101 through the shallow trench isolation structure, and then the active region may be further ion-doped, so as to form a well region 102 in the substrate 101, for example, a P-well region in the substrate 101.

As shown in fig. 2, in step S2, after the well region 102 is formed in the substrate 101, the gate oxide layer 103 may also be formed on the substrate 101, that is, the gate oxide layer 103 is formed on the well region 102, that is, the gate oxide layer 103 completely covers the well region 102. In this embodiment, the gate oxide layer 103 may be formed on the substrate 101 by using a thermal oxidation (wet oxidation or dry oxidation) process, an in-situ steam generation process, a chemical vapor deposition process, or an atomic layer deposition process, and the gate oxide layer 103 may be made of silicon dioxide, silicon oxynitride, or silicon nitride. The thickness of the gate oxide layer 103 may be 2nm to 30nm, for example 10nm or 20 nm.

As shown in fig. 3, in step S3, after forming the gate oxide layer 103, a gate material layer is then formed on the gate oxide layer 103, the gate material layer may be made of polysilicon, a metal material compound or other suitable materials, a patterned photoresist layer is then formed on the gate material layer, and the gate material layer is etched using the patterned photoresist layer as a mask to form the floating gate 104 and the select gate 105. In this embodiment, the floating gate 104 and the select gate 105 may be made of polysilicon, and a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process may be used to etch the polysilicon, for example, the floating gate 104 and the select gate 105 are formed by dry etching the polysilicon. Floating gate 104 and select gate 105 are both located on well region 102, and floating gate 104 is located on one side of select gate 105. In some embodiments, the materials of the floating gate 104 and the select gate 105 may be different, and the floating gate 104 and the select gate 105 may be formed by different methods, which are not limited herein.

As shown in fig. 4, in step S4, after the floating gate 104 and the select gate 105 are formed, a nitride layer may be formed on the substrate 101, the nitride layer may cover the floating gate 104 and the select gate 105, and then the nitride layer is etched through a plasma etching process, and since the plasma etching process has a good etching directionality, the nitride layer on the surfaces of the floating gate 104 and the select gate 105 is etched away, and the nitride layer on both sides of the floating gate 104 and the select gate 105 is remained, so that side walls (offset spacers) are formed on both sides of the floating gate 104 and the select gate 105, that is, the first side wall 106 is formed on both sides of the floating gate 104, and the second side wall 107 is formed on both sides of the select gate 105. In this embodiment, the materials of the first sidewall 106 and the second sidewall 107 are the same, the structures of the first sidewall 106 and the second sidewall 107 are the same, the material of the first sidewall 106 may also be one or a combination of silicon oxide and silicon nitride, and the thickness of the first sidewall 106 may be 3-10nm, for example, 5nm or 8 nm. In some embodiments, the first sidewall 106 and the second sidewall 107 may both include an Oxide-Nitride-Oxide (ONO) structure, that is, an isolation Oxide layer, a sidewall Nitride layer, and a sidewall Oxide layer (not shown in the figure) formed by sequentially overlapping side surfaces of the floating gate 104 and the select gate 105, where the isolation Oxide layer is close to the floating gate 104 and the select gate 105, and the isolation Oxide layer is an inner layer of the first sidewall 106 and the second sidewall 107. The isolation oxide layer is, for example, silicon dioxide, the sidewall nitride layer is, for example, silicon nitride, and the sidewall oxide layer is, for example, silicon oxynitride or silicon dioxide. The isolation oxide layer can be deposited by adopting a plasma enhanced chemical vapor deposition process, the side wall nitride layer can be deposited by adopting a low-pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process, and the side wall oxide layer can be deposited by adopting a normal-pressure chemical vapor deposition process, a low-pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process. The forming of the first side wall 106 and the second side wall 107 further includes etching the isolation oxide layer, the side wall nitride layer, and the side wall oxide layer by anisotropic etching.

As shown in fig. 5, in step S5, after the first and

second sidewalls

106 and 107 are formed, the substrate 101 is ion-doped, so that the first doped region 108, the second doped region 109 and the third doped region 110 are formed in the substrate 101, that is, the first doped region 108, the second doped region 109 and the third doped region 110 are formed in the well region 102. The first doped region 108, the second doped region 109 and the third doped region 110 have the same ion doping type, and the ion doping amount may be the same. The first doped region 108 and the second doped region 109 are located at two sides of the select gate 105, i.e., the first doped region 108 and the second doped region 109 are adjacent to the second sidewall 107. The second doped region 109 and the third doped region 110 are located at both sides of the floating gate 104, i.e., the second doped region 109 and the third doped region 110 are adjacent to the first sidewall 106. The second doped region 109 is located between the select gate 105 and the floating gate 104, that is, two ends of the second doped region 109 are adjacent to the first sidewall 106 and the second sidewall 107, respectively. In this embodiment, the floating gate 104 and the select gate 105 are located between the first doped region 108 and the third doped region 110, and the floating gate 104 and the select gate 105 share the second doped region 109. In the present embodiment, the first doped region 108 is defined as a source, the second doped region 109 is defined as a common doped region, and the third doped region 110 is defined as a drain. The present embodiment may employ an ion implantation process to form the first doped region 108, the second doped region 109 and the third doped region 110; for example, at least one of phosphorus ions, arsenic ions, or antimony ions is implanted into the substrate 101. In the present embodiment, the ion doping type of the first doping region 108 is different from the ion doping type of the well region 102.

As shown in fig. 6, in step S6, a first material layer 111 is first formed on the substrate 101, the first material layer 111 may cover the floating gate 104, and the first material layer 111 also covers the first sidewall 106 and the second sidewall 107. Then, a second material layer 112 is formed on the first material layer 111, and the second material layer 112 completely covers the first material layer 111. In this embodiment, the first material layer 111 is an oxide, such as silicon dioxide, and the second material layer 112 is a nitride, such as silicon nitride. The present embodiment may form the first material layer 111 by using a low pressure chemical vapor deposition method, and then form the second material layer 112 on the first material layer 111 by using a low pressure chemical vapor deposition method. The first material layer 111 and the second material layer 112 are used to form a gate dielectric layer on the floating gate 104.

As shown in fig. 7 to 8, in the present embodiment, after the second material layer 112 is formed, a patterned photoresist layer 114 is formed on the second material layer 112 on the floating gate 104, that is, the patterned photoresist layer 114 is formed only on the floating gate 104. The patterned photoresist layer 114 also extends towards the first sidewalls 106 on both sides, so as to prevent damage to the ONO structure of the first sidewalls 106 during subsequent etching of the second material layer 112 and the first material layer 111, for example, damage to the isolation oxide layer located inside the first sidewalls 106. Then, the second material layer 112 and the first material layer 111 are sequentially etched by using the patterned photoresist layer 114 as a mask, so that a gate dielectric layer 113 is formed on the floating gate 104, that is, the gate dielectric layer 113 includes the first material layer 111 and the second material layer 112. In this embodiment, a wet etching process may be used to remove the exposed second material layer 112 and the exposed first material layer 111, for example, whether the second material layer 112 is removed by using a phosphoric acid solution, and then the first material layer 111 is removed by using a hydrofluoric acid solution, where the wet etching is stopped at the first sidewall 106. It should be noted that, only the second material layer 112 and the first material layer 111 under the patterned photoresist layer 114 remain through the etching process, and the second material layer 112 and the first material layer 111 in other areas are removed.

As shown in fig. 7 to 8, in this embodiment, since the patterned photoresist layer 114 extends toward the first sidewalls 106 on both sides, the formed gate dielectric layer 113 also extends toward the first sidewalls 106 on both sides and covers a part of the first sidewalls 106, so that the gate dielectric layer 113 can prevent the structure of the first sidewalls 106 close to the floating gate 104 from being etched, that is, the gate dielectric layer 113 can also prevent the floating gate 104 from being etched, thereby ensuring the integrity of the floating gate 104 and improving the performance of the device. In the present embodiment, the thickness of the first material layer 111 may be 5-10nm, such as 6 or 7nm, and the thickness of the second material layer 112 may be 5-10nm, such as 8 or 9 nm. The width d of the gate dielectric layer 113 covering the first sidewall spacers 106 may be 20-30nm, for example, 25 nm.

As shown in fig. 8, in the present embodiment, after the gate dielectric layer 113 is formed, the patterned photoresist layer 114 is also removed. The gate dielectric layer 113 includes a two-layer structure, but the gate dielectric layer 113 may also include a three-layer structure of an oxide layer, a nitride layer, and an oxide layer.

As shown in fig. 9, in step S7, after the gate dielectric layer 113 is formed, the gate oxide layer 103 on the first doped region 108, the second doped region 109 and the third doped region 110 is then removed by an etching process, for example, the gate oxide layer 103 is removed by a wet etching; a salicide layer 115 is then formed over the first doped region 108, the second doped region 109, the third doped region 110, and the select gate 105. Self-aligned metal silicide layer 115For example, a metal silicide having low resistance and good adhesion to a silicon material, such as cobalt silicide, titanium silicide, or nickel silicide. The salicide layer 115 may serve as a contact structure for a transistor. The present embodiment is described by taking the formation of the salicide layer 115 in the select gate 105 as an example, and the salicide layer 115 is taken as the nickel silicide as an example. The step of forming the salicide layer 115 may include first forming a nickel layer 1051 on the select gate 105 by a sputtering technique, and then performing a first annealing process on the nickel layer 1051 at a temperature of about 300-₂ Si layer 1052, Ni₂Si layer 1052 may also be referred to as an intermediate suicide layer. The Ni₂The thickness of Si layer 1052 is, for example, 150-400 angstroms. Specifically, the first annealing process may be performed using a sputtering apparatus, and when nickel is deposited using the sputtering apparatus, the first annealing process may be performed using an in-situ (in-situ) process after the nickel is deposited, or may be performed using an ex-situ process. In the formation of Ni₂After Si layer 1052, the unreacted nickel layer 1051 is selectively removed, for the Ni₂Si layer 1052 is subjected to a second annealing process. The second annealing temperature is higher than the first annealing temperature. Specifically, the second annealing temperature is, for example, 400-. After a second annealing process, the Ni₂Si layer 1052 is converted into salicide layer 115, which salicide layer 115 has thermal stability. The salicide layer 115 can reduce the contact resistance between the select gate 105 and the conductive plug formed later, thereby improving the performance of the device; the salicide layer 115 may also prevent the first doped region 108 or the third doped region 110 from being broken down or leaking current, so that the stability of the device may be improved. The salicide layer 115 can also be used as a contact structure of the transistor to lead out the source, drain and gate of the transistor. In some embodiments, other metals, such as at least one of cobalt, tungsten, platinum, manganese, titanium, tantalum, may also be formed on the select gate 105.

As shown in fig. 11, in step S8, after forming the salicide layer 115, an interlayer dielectric layer 116 is then formed on the substrate 101. The interlayer dielectric layer 116 covers the substrate 101, that is, the interlayer dielectric layer 116 covers the floating gate 104 and the select gate 105, and the interlayer dielectric layer 116 also covers the gate dielectric layer 113. In the present embodiment, an interlayer dielectric layer 116 may be formed on the substrate 101 by, for example, a high density plasma chemical vapor deposition method, and the thickness of the interlayer dielectric layer 116 may be 6000-. The material of the interlayer dielectric layer 116 may be silicon dioxide.

As shown in fig. 11, after forming interlayer dielectric layer 116, since the surface of interlayer dielectric layer 116 is uneven, the surface of interlayer dielectric layer 116 is planarized. The thickness of interlevel dielectric layer 116 after planarization may be 1500-2000 angstroms. Meanwhile, after the planarization process, the interlayer dielectric layer 116 still covers the floating gate 104 and the select gate 105. After planarization, an interlayer dielectric layer 116 is deposited on the interlayer dielectric layer 116 again to increase the thickness of the interlayer dielectric layer 116, wherein the thickness of the interlayer dielectric layer 116 may be 3000-4000 angstroms. The compactness of the interlayer dielectric layer 116 formed for the second time is higher than that of the interlayer dielectric layer 116 formed for the first time, the surface uniformity of the interlayer dielectric layer 116 formed for the second time is good, and the performance of the device can be improved.

As shown in fig. 12, in step S9, after forming the interlayer dielectric layer 116, a patterned photoresist layer 114 is then formed on the interlayer dielectric layer 116, and the patterned photoresist layer 114 forms a first opening 1151 and a second opening 1152 on the interlayer dielectric layer 116. The width of the first opening 1151 is greater than the width of the second opening 1152. A first opening 1151 is positioned on the floating gate 104 and a second opening 1152 is positioned on the select gate 105. A second opening 1152 is also provided over the first doped region 108 and the third doped region 110.

As shown in fig. 12, after the first opening 1151 and the second opening 1152, the interlayer dielectric layer 116 is etched according to the first opening 1151 and the second opening 1152 through an etching process, so that a first contact hole 1161 and a plurality of second contact holes 1162 are formed in the interlayer dielectric layer 116. The first contact hole 1161 exposes the gate dielectric layer 113. The second contact hole 1162 exposes the select gate 105, and the second contact hole 1161 also exposes the first doped region 108 and the third doped region 110. Since the width of the first opening 1151 is greater than the width of the second opening 1152, the width of the first contact hole 1161 is greater than the width of the second contact hole 1162. The first contact hole 1161 and the second contact hole 1162 are, for example, inverted trapezoidal or elongated.

As shown in fig. 13, after the first contact hole 1161 and the second contact hole 1162 are formed, a conductive material is filled in the first contact hole 1161 and the second contact hole 1162, for example, a metal material is deposited in the first contact hole 1161 and the second contact hole 1162 through a deposition process, for example, a titanium/titanium nitride barrier layer and metal tungsten are deposited, so as to form the first type conductive plug 117 and the second type conductive plug 118. A first type of conductive plug 117 is located on the floating gate 104 and a second type of conductive plug 118 is located on the first doped region 108, the third doped region 110 and the select gate 105. Since the width of the first contact hole 1161 is greater than the width of the second contact hole 1162, the width of the first type conductive plug 117 is greater than the width of the second type conductive plug 118. The first type of conductive plug 117 and the second type of conductive plug 118 are similar in shape and may each have an inverted trapezoidal shape.

As shown in fig. 13, in step S10, after the first type conductive plugs 117 and the second type conductive plugs 118 are formed, a first metal layer is then formed on the interlayer dielectric layer 116, and the first metal layer includes a first metal 119, a second metal 120, a third metal 121, and a fourth metal 122. The first metal 119 is directly connected to the gate dielectric layer 113 through a first type of conductive plug 117 and the second metal 120 is connected to the select gate 105 through a second type of conductive plug 118. The third metal 121 is connected to the first doped region 108 (source) through a second type conductive plug 118. The fourth metal 122 is connected to the third doped region 110 (drain) through the second type conductive plug 118. In the present embodiment, the first metal 119, the second metal 120, the third metal 121 and the fourth metal 122 are made of metal materials, so as to form a good electrical connection with external electrical components.

As shown in fig. 13, in the present embodiment, a radial dimension of the first conductive plug 117 is greater than a radial dimension of the second conductive plug 118, specifically, for example, a width of the first conductive plug 117 is greater than a width of the second conductive plug 118, a contact area between the first conductive plug 117 and the first metal 119 is greater than a contact area between the second conductive plug 118 and the second metal 120, and a contact area between the first conductive plug 117 and the gate dielectric layer 113 is greater than a contact area between the second conductive plug 118 and the second metal 105. The width of the first type conductive plug 117 may be, for example, greater than or equal to 0.3 micrometers, and the width of the second type conductive plug 118 may be, for example, 0.12 micrometers, since the radial dimension of the first type conductive plug 117 is larger, the coupling ratio of the multi-time programmable memory structure may be improved, and meanwhile, in this embodiment, the first metal 119 controls the floating gate 104 to perform data storage and erasure through coupling, and thus, the performance of the multi-time programmable memory may be improved. Meanwhile, because the radial dimension of the first-type conductive plugs 117 is larger than that of the second-type conductive plugs 118, the first-type conductive plugs 117 can be used as control gates, and the control gates do not need to be formed on the gate dielectric layer 113, so that the overall height of the multi-time programmable memory can be reduced, that is, the size of the multi-time programmable memory can be reduced.

Fig. 14 shows a top view of a multi-time programmable memory structure, as shown in fig. 13-14. The multiple-time programmable memory structure 10 may include: the memory device includes a substrate 101, the substrate 101 includes a memory cell region where a floating gate 104 and a select gate 105 are located for forming a memory transistor and a high voltage transistor for controlling the memory transistor, and a peripheral circuit region where a structure such as a capacitor is formed. The first level metal layer of the multi-time programmable memory structure 10 includes a first metal 119, the first metal 119 being located over the floating gate 104. The first metal level of the multi-time programmable memory structure 10 includes a second metal 120, the second metal 120 being located on the select gate 105. The first metal layer further includes a third metal 121 and a fourth metal 122 respectively disposed at both ends of the substrate 101. The first metal 119 is connected to the gate dielectric layer 113 through a first type conductive plug 117, the second metal 120 is connected to the floating gate 105 through a second type conductive plug 118, the third metal 121 is connected to the first doped region 108 through a second type conductive plug 118, and the fourth metal 122 is connected to the third doped region 110 through a second type conductive plug 118. In this embodiment, the area of the first metal 119 is larger than that of the second metal 120, and the area of the second metal 120 is equal to that of the third metal 121 or the fourth metal 122. The area of the first metal 119 may be understood as a contact area of the first type conductive plug 117 and the first metal 119, and the area of the second metal 120 may be understood as a contact area of the second type conductive plug 118 and the second metal 120. The area of the third metal 121 or the fourth metal 122 can be understood as the contact area between the second type conductive plug 118 and the third metal 121 or the fourth metal 122.

As shown in fig. 14, in the present embodiment, the memory cells of the multi-time programmable memory include several multi-time programmable memory structures 10, and the floating gates 104 and the select gates 105 in the multi-time programmable memory structures 10 can be independently formed on the active regions in the substrate 101. Adjacent multi-time programmable memory structures 10 may share select gates 105.

As shown in fig. 15-16, the floating gate 104 serves as the electron storage layer in the multi-time programmable memory structure 10. By programming, when the voltage difference between the first metal 119 and the substrate 101 is large enough, electrons collected in the channel can enter the floating gate 104 by tunneling effect, and the gate dielectric layer 113 between the first metal 119 and the floating gate 104 prevents the electrons from being lost, so that the electrons are stored in the floating gate 104. When data writing operation is carried out, a high positive bias voltage is applied to the first metal 119, so that electrons pass through the gate oxide layer 103 from the first doped region 108 and are injected into the floating gate 104, meanwhile, the width of the first type of conductive plug 117 is larger than that of the second type of conductive plug 118, and the contact area of the first type of conductive plug 117 and the first metal 119 is larger than that of the second type of conductive plug 118 and the second metal 120, so that the coupling ratio of the multi-time programmable memory can be improved.

As shown in fig. 16, when a data erase operation is performed, a high negative bias voltage is applied to the first metal 119, and the first metal 119 controls the release of electrons in the floating gate 104 through coupling, so that the electrons stored in the floating gate 104 are removed from the floating gate 104 by Fowler-Nordheim (FN) tunneling, thereby completing the erase of the data stored in the multi-time programmable memory structure 10.

In summary, the first side walls are formed on the two sides of the floating gate, the gate dielectric layer is formed on the floating gate, the gate dielectric layer extends to the first side walls on the two sides, and covers a part of the first side walls, so that damage to the first side walls when the gate dielectric layer is etched can be reduced or avoided, and the performance of the multi-time programmable memory is improved.

Reference throughout this specification to "one embodiment", "an embodiment", or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily all embodiments, of the present invention. Thus, respective appearances of the phrases "in one embodiment", "in an embodiment", or "in a specific embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It is to be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the present invention.

It will also be appreciated that one or more of the elements shown in the figures can also be implemented in a more separated or integrated manner, or even removed for inoperability in some circumstances or provided for usefulness in accordance with a particular application.

Additionally, any reference arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise expressly specified. Further, as used herein, the term "or" is generally intended to mean "and/or" unless otherwise indicated. Combinations of components or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.

As used in the description herein and throughout the claims that follow, "a", "an", and "the" include plural references unless otherwise indicated. Also, as used in the description herein and throughout the claims that follow, unless otherwise indicated, the meaning of "in …" includes "in …" and "on … (on)".

The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.

The systems and methods have been described herein in general terms as the details aid in understanding the invention. Furthermore, various specific details have been given to provide a general understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

Thus, although the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Thus, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention is to be determined solely by the appended claims.

Claims

1. A multiple-time programmable memory structure, comprising:

a substrate;

2. The multiple-time programmable memory structure of claim 1, wherein the gate dielectric layer comprises a first material layer and a second material layer, and wherein the first material layer is on the floating gate and the second material layer is on the first material layer.

3. The multi-time programmable memory structure of claim 2, wherein the first material layer is an oxide and the second material layer is a nitride.

4. The multiple-time programmable memory structure of claim 1, further comprising a source and a drain in the substrate, the floating gate and the select gate being located between the source and the drain.

5. The multiple-time programmable memory structure of claim 4, further comprising a shared doped region in the substrate, the shared doped region being located between the floating gate and the select gate.

6. The multiple-time programmable memory structure of claim 5, wherein the first level metal layer further comprises a third metal and a fourth metal, the third metal being connected to the source through the second type of conductive plug, and the fourth metal being connected to the drain through the second type of conductive plug.

7. The multi-time programmable memory structure of claim 6, further comprising salicide layers on upper surfaces of the select gate, the source, and the drain, respectively.

8. The multiple-time programmable memory structure of claim 1, further comprising a gate oxide layer between the floating gate and the substrate.

9. The multiple-time programmable memory structure of claim 1, wherein two sides of the select gate further comprise second spacers.

10. A method of fabricating a multi-time programmable memory structure, comprising:

providing a substrate;

forming a gate oxide layer on the substrate;