CN113471149A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN113471149A CN113471149A CN202110750624.5A CN202110750624A CN113471149A CN 113471149 A CN113471149 A CN 113471149A CN 202110750624 A CN202110750624 A CN 202110750624A CN 113471149 A CN113471149 A CN 113471149A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
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- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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Abstract
本发明涉及一种半导体结构及其制备方法。其中，半导体结构的制备方法，包括：提供基底；在基底内形成多个间隔排布的接触孔；在接触孔内形成接触材料层；在接触材料层和基底上形成位线材料层；去除部分位线材料层和部分接触材料层，以形成位线结构,位线结构包括剩余的位线材料层构成的位线层以及剩余的接触材料层构成的接触层，接触层位于接触孔内，位线层跨越接触孔以及接触孔外的基底。本发明可以有效降低位线结构的高度，从而有效防止位线结构在之后的制成过程中倾斜或倒塌。
The present invention relates to a semiconductor structure and a preparation method thereof. Wherein, the preparation method of the semiconductor structure includes: providing a substrate; forming a plurality of contact holes arranged at intervals in the substrate; forming a contact material layer in the contact hole; forming a bit line material layer on the contact material layer and the substrate; The bit line material layer and part of the contact material layer are formed to form a bit line structure. The bit line structure includes a bit line layer composed of the remaining bit line material layers and a contact layer composed of the remaining contact material layers. The contact layer is located in the contact hole. The wire layer spans the contact hole and the substrate outside the contact hole. The present invention can effectively reduce the height of the bit line structure, thereby effectively preventing the bit line structure from tilting or collapsing in the subsequent manufacturing process.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
In semiconductor memory device fabrication processes, bit lines are typically formed by dry etching. After the formation of the bit lines by dry etching, a series of organics caused by dry etching can be removed by wet cleaning.
However, during wet cleaning, tension may exist between bit lines due to the flow of the solution. The tension easily causes the phenomena of inclination and collapse of the bit line.
Disclosure of Invention
In view of the above, it is necessary to provide a semiconductor structure and a method for fabricating the same, which can solve the problem that the bit line is easily tilted and collapsed due to the tensile force during the wet cleaning.
A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of contact holes arranged at intervals in the substrate;
forming a contact material layer in the contact hole;
forming a bit line material layer on the contact material layer and the substrate;
and removing part of the bit line material layer and part of the contact material layer to form a bit line structure, wherein the bit line structure comprises the bit line layer formed by the rest of the bit line material layer and the contact layer formed by the rest of the contact material layer, the contact layer is positioned in the contact hole, and the bit line layer spans the contact hole and the substrate outside the contact hole.
In one embodiment, the forming a plurality of contact holes arranged at intervals on the substrate includes:
forming a dielectric material layer on the substrate;
forming a first graphical mask layer on the medium material layer;
and etching the dielectric material layer and the substrate based on the first graphical mask layer, removing part of the dielectric material layer and part of the substrate, and forming the contact hole.
In one embodiment, before forming the contact material layer in the contact hole, the method includes:
and removing the remained dielectric material layer.
In one embodiment, the removing a portion of the bit line material layer and a portion of the contact material layer to form a bit line structure includes:
forming a second patterned mask layer on the bit line material layer;
and etching the bit line material layer and the contact material layer based on the second patterned mask layer, and removing part of the bit line material layer and part of the contact material layer to form the bit line structure.
In one of the embodiments, the first and second electrodes are,
the substrate is provided with an array region and a peripheral region which are adjacent, and a plurality of contact holes which are arranged at intervals are formed on the substrate, and the contact holes comprise:
forming a peripheral functional material layer on the substrate;
removing the peripheral functional material layer of the array region;
and forming the contact hole on the substrate of the array region.
In one embodiment, the removing the peripheral functional material layer of the array region includes:
forming an injection blocking layer on the polycrystalline silicon layer of the array region;
based on the injection blocking layer, carrying out ion injection on the polycrystalline silicon layer of the peripheral area to form doped polycrystalline silicon;
removing the injection blocking layer;
removing the undoped polysilicon layer of the array region and retaining the doped polysilicon of the peripheral region.
In one embodiment, the removing the undoped polysilicon layer of the array region and the remaining the doped polysilicon of the peripheral region comprises:
and removing the undoped polysilicon layer of the array region by utilizing a wet method or dry method self-aligned etching mode.
In one embodiment, the forming the contact hole on the substrate of the array region includes:
forming a dielectric material layer on the substrate of the array region and the peripheral functional material layer of the peripheral region;
carrying out planarization treatment on the dielectric material layer to enable the top surface of the dielectric material layer in the array area to be flush with the top surface of the dielectric material layer in the peripheral area;
forming a first graphical mask layer on the dielectric material layer, wherein the first graphical mask layer is provided with an opening positioned in the array area, and the opening exposes the dielectric material layer and defines the shape and the position of the contact hole;
and etching the dielectric material layer and the substrate based on the first patterned mask layer, removing part of the dielectric material layer and part of the substrate, and forming the contact hole.
In one embodiment, before forming the contact material layer in the contact hole, the method includes:
removing the remaining dielectric material layer;
the forming of the contact material layer in the contact hole includes:
and forming the contact material layer in the contact hole, and forming the contact material layer on the surface of the doped polysilicon.
In one embodiment, the forming a bit line material layer on the contact material layer and the substrate includes:
forming the bit line material layer on the contact material layer of the array region, the substrate, and the contact material layer of the peripheral region.
In one embodiment, the removing the portion of the contact material layer and the portion of the bit line material layer includes:
forming a second patterned mask layer on the bit line material layer, wherein the second patterned mask layer comprises a first mask pattern and a second mask pattern, the first mask pattern is located above the contact holes of the array region, and the second mask pattern is located above the bit line material layer of the peripheral region;
and etching the bit line material layer, the contact material layer and the doped polysilicon based on the second patterned mask layer to form the bit line structure of the array region and the gate structure of the peripheral region.
In one embodiment, the bit line material layer includes a barrier material layer, a conductive material layer and an insulating material layer stacked in sequence, wherein the barrier material layer is formed on the contact material layer and the substrate.
A semiconductor structure, comprising:
a substrate;
a plurality of contact holes arranged in the substrate at intervals;
the bit line structure comprises a contact layer and a bit line layer which are stacked, wherein the contact layer is positioned in the contact hole, and the bit line layer spans the contact hole and the substrate outside the contact hole.
In one embodiment, the substrate includes an array region and a peripheral region adjacent to each other, and the plurality of contact holes are located in the array region.
In one embodiment, the bit line layer includes a barrier layer, a conductive layer, and an insulating layer stacked in this order, and the semiconductor structure further includes:
the grid structure is positioned in the peripheral region;
wherein the gate structure includes the contact layer and the bit line layer.
In one embodiment, the semiconductor device comprises a plurality of spaced-apart active regions on a substrate, wherein a top surface of the contact layer is lower than a top surface of the active regions.
In one embodiment, the height of the gate structure in the peripheral region in the direction perpendicular to the substrate surface is greater than the height of the bit line structure in the direction perpendicular to the substrate surface, and the width of the gate structure in the peripheral region in the direction parallel to the substrate surface is greater than the width of the bit line structure in the direction parallel to the substrate surface.
In the semiconductor structure, the contact layer of the bit line structure is positioned in the contact hole. That is, the contact layer of the bit line structure does not exist on the substrate except the contact hole. Therefore, the contact layer inside the contact hole can effectively reduce the height of the bit line structure while realizing good contact between the bit line layer and the active area, so that the bit line structure is effectively prevented from inclining or collapsing in the later manufacturing process.
Drawings
In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments described in the specification, and other drawings can be obtained by those skilled in the art without inventive labor.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;
in fig. 2 to 12, the (a) diagram of each figure is a schematic structural view of an array region in the process of manufacturing a semiconductor structure;
in fig. 2 to 12, the (b) diagram of each of the drawings is a schematic structural view of the peripheral region in the process of manufacturing the semiconductor structure.
Description of reference numerals:
100-a substrate; 100 a-contact holes; 110-a substrate; 111-active region; 120-a dielectric layer; 121-a first dielectric layer; 122-a second dielectric layer; 130-shallow trench isolation structures; 200-a contact layer; 201-a layer of contact material; a 300-bit line layer; 310-a barrier layer; 320-a conductive layer; 330-an insulating layer; 301-bit line material layer; 311-a layer of barrier material; 321-a layer of conductive material; 331-a layer of insulating material; 400-insulating dielectric layer; 401-a layer of dielectric material; 501-a first masking material layer; 600-a second patterned mask layer; 601-a second layer of masking material; 701-peripheral functional material layer; 711-doped polysilicon; 710-a doped layer; 800-implanting a barrier layer; 900-Photoresist mask
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "upper," "lower," "front," "rear," "circumferential," and the like are based on the orientation or positional relationship shown in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In one embodiment, referring to fig. 1, a method for fabricating a semiconductor structure is provided, which includes the steps of:
step S100, providing a substrate 100;
step S200, forming a plurality of contact holes 100a arranged at intervals in the substrate 100, please refer to fig. 8 (a);
step S300, forming a contact material layer 201 in the contact hole 100a, please refer to fig. 9 (a);
step S400, forming a bit line material layer 301 on the contact material layer 201 and the substrate 100, as shown in fig. 10 (a);
in step S500, a portion of the bit line material layer 301 and a portion of the contact material layer 201 are removed to form a bit line structure, where the bit line structure includes the bit line layer 300 formed by the remaining bit line material layer 301 and the contact layer 200 formed by the remaining contact material layer 201, the contact layer 200 is located in the contact hole 100a, and the bit line layer 300 spans the contact hole 100a and the substrate 100 outside the contact hole 100a, as shown in fig. 12 (a).
In step S100, in an embodiment, the base 100 may include a substrate 110 and a dielectric layer 120.
Shallow trench isolation structures 130 may be formed in the substrate 110. The shallow trench isolation structure 130 isolates the substrate 110 into a plurality of active regions 111 arranged at intervals. The active region may include a source region (not shown), a drain region (not shown), and a channel region (not shown) therebetween of a transistor of the memory cell. In an embodiment, the substrate 110 may be a silicon substrate. Of course, it may be other semiconductor substrates such as silicon germanium and silicon carbide.
In step S200, the contact hole 100a may extend into the active region 111 of the substrate 110, and connect with a source region or a drain region in the source region 111.
In step S300, the material of the contact material layer 201 may be polysilicon or the like, and specifically, may be doped polysilicon or the like. Also, the contact material layer 201 may be formed by epitaxial growth, chemical vapor deposition, or the like.
In some embodiments, the contact material layer 201 may be formed on the source region or the drain region of the active region 111 directly in the contact hole 100a by epitaxy, or a raw material layer of the contact material layer 201 may be formed in the contact hole 100a and outside the contact hole 100a by chemical vapor deposition, and then the unnecessary raw material layer is removed by etching back or grinding, etc. to form the contact material layer 201 in the contact hole 100 a.
In some embodiments, the top surface of the contact material layer 201 located in the contact hole 100a is lower than the top surface of the active region 111 by increasing the etch back time. The top surface of the contact layer 200 formed subsequently is lower than the top surface of the active region 111, so that the height of the bit line is further reduced, and the stability of the bit line is improved.
In step S400, the bit line material layer 301 may include a plurality of film layers.
In one embodiment, the bit line material layer 301 may include a barrier material layer 311, a conductive material layer 321, and an insulating material layer 331 stacked in sequence.
Wherein a barrier material layer 311 is formed on the contact material layer 201 and the substrate 100, and a material thereof may include titanium (Ti), titanium nitride (TiN), and the like. The conductive material layer 321 is formed on the barrier material layer 311, and the material thereof may include a metal material such as tungsten (W). A layer of insulating material 331 is formed on the layer of conductive material 321, which may comprise a nitride or oxynitride material, among others.
Of course, the bit line material layer 301 may also include a single film layer, which is not limited in this application.
In step S500, a portion of the bit line material layer 301 may be removed first, and the remaining bit line material layer 301 constitutes the bit line layer 300. The bit line layer 300 crosses the contact hole 100a and the substrate outside the contact hole 100a so that it can be implemented to provide bit line signals to transistors of a row or a column of memory cells.
Specifically, when the bit line material layer 301 includes a plurality of film layers, a partial region of each film layer may be sequentially removed through a photolithography etching process. Such as sequentially removing portions of the insulating material layer 331, the conductive material layer 321, and the barrier material layer 311. The remaining layer of insulating material 331 constitutes the insulating layer 330, the remaining layer of conductive material constitutes the conductive layer 320, and the remaining layer of barrier material constitutes the barrier layer 310.
The bit line layer 300 may include a barrier layer 310, a conductive layer 320, and an insulating layer 330. Barrier layer 310 may prevent the metal in conductive layer 320 from diffusing downward. The insulating layer 330 can perform effective insulation protection.
After the bit line layer 300 is formed, a portion of the contact material layer 201 may be etched away based on the bit line layer 300, and the remaining contact material layer 201 constitutes the contact layer 200. The contact layer 200 is formed in the contact hole 100a connecting the source or drain region in the source region 111, so that good signal transmission between the bit line layer 300 and the source or drain region in each active region 111 can be achieved.
In some embodiments, substrate 100 includes dielectric layer 120, and after contact layer 200 is formed, etching of at least a portion of dielectric layer 120 (second dielectric layer 122) may be continued based on bit line layer 300 to align the remaining portion of dielectric layer 120 with bit line layer 300.
The contact layer 200 of the bit line structure formed in the present embodiment is located inside the contact hole 100a, i.e., the contact layer 200 of the bit line structure does not exist on the substrate 100 outside the contact hole 100 a. Therefore, the present embodiment can effectively reduce the height of the bit line structure while achieving good contact between the bit line layer 300 and the active region through the contact layer 200 inside the contact hole 100a, thereby effectively preventing the bit line structure from being tilted or collapsed in a later fabrication process.
In one embodiment, step S200 includes:
forming a dielectric material layer 401 on the substrate 100, please refer to fig. 6 (a);
a first patterned mask layer is formed on the dielectric material layer 401, and the material of the dielectric material layer 401 may include silicon dioxide or the like. Based on the first patterned mask layer, the dielectric material layer 401 and the substrate 100 are etched, and a portion of the dielectric material layer 401 and a portion of the substrate 100 are removed to form a contact hole 100a, as shown in fig. 7 (a). The first patterned mask layer may comprise a multi-layer or a single-layer mask layer. Specifically, a multi-layer or single-layer first mask material layer 501 may be formed on the dielectric material layer 401, see fig. 6 (a). Then, the first mask material layer 501 is subjected to patterning processing, thereby forming a first patterned mask layer (not shown).
Specifically, based on the first patterned mask layer, the dielectric material layer 401 is etched, and a portion of the dielectric material layer 401 is removed, so that the patterned insulating dielectric layer 400 is formed. The substrate 100 is then etched based on the patterned insulating dielectric layer 400, thereby forming the contact hole 100 a.
In one embodiment, the method further comprises removing the remaining dielectric material layer 401, i.e. removing the insulating dielectric layer 400, as shown in fig. 8 (a).
At this time, it is possible to facilitate formation of the contact material layer 201 with good quality in the contact hole 100a, and prevent the contact material layer 201 from being poorly filled due to an excessively large depth of the filling hole during the filling process.
In one embodiment, step S500 includes:
forming a second patterned mask layer on the bit line material layer 301, as shown in fig. 11 (a);
based on the second patterned mask layer, the bit line material layer 301 and the contact material layer 201 are etched, and a portion of the bit line material layer 301 and a portion of the contact material layer 201 are removed to form a bit line structure, as shown in fig. 12 (a).
The second patterned mask layer may comprise a multi-layer or a single-layer mask layer. Specifically, a plurality of layers or a single layer of second mask material 601 may be formed on the bit line material layer 301 first, see fig. 11 (a). Then, the second mask material layer 601 is subjected to patterning processing, thereby forming a second patterned mask layer (not shown). Specifically, the bit line material layer 301 may be etched based on the second patterned mask layer, and a portion of the bit line material layer 301 may be removed, thereby forming the bit line layer 300. Based on the bit line layer 300, the contact material layer 201 is etched to remove a portion of the contact material layer 201 to form the contact layer 200.
In one embodiment, the substrate 100 has an array region and a peripheral region that are adjacent. In the drawings described below, fig. 2 to 12(a) are schematic structural views of an array region in the process of manufacturing a semiconductor structure; fig. 2 to 12 (b) are schematic structural views of the peripheral region in the process of manufacturing the semiconductor structure.
In this embodiment, step S200 includes:
forming a peripheral functional material layer 701 on the substrate 100, please refer to fig. 2;
removing the peripheral functional material layer 701 in the array region, please refer to fig. 5;
The peripheral functional material layer 701 is a material layer that can be processed to form a certain functional film layer in the peripheral region, or directly form a certain functional film layer in the peripheral region. For example, the peripheral functional material layer 701 may be a polysilicon layer, and may be used to form a portion of a gate structure of the peripheral region.
In an embodiment, the substrate 100 may include a substrate 100, a first dielectric layer 121, and a second dielectric layer 122 in the array region. In the peripheral region, the substrate 100 may include the substrate 100 and the first dielectric layer 121.
Specifically, the peripheral functional material layer 701 may be formed on the surface of the second dielectric layer 122 in the array region and the surface of the first dielectric layer 121 in the peripheral region.
In the present embodiment, the peripheral functional material layer 701 of the array region is removed, thereby facilitating the formation of the contact hole 100a on the substrate 100.
In some embodiments, base 100 may include substrate 110 and dielectric layer 120. Before forming the contact hole 100a, the peripheral functional material layer 701 in the array region is removed, so that the active region 111 can be effectively protected by the dielectric layer 120 in the process of removing the peripheral functional material layer 701.
In some embodiments, the peripheral functional material layer 701 in the array region may not be removed before the formation of the contact hole 100a, which is not limited in the present application. At this time, the peripheral functional material layer 701 of the array region may be removed in a subsequent process or removed step by step.
In one embodiment, the peripheral function material layer 701 includes a polysilicon layer, so that the peripheral function material layer 701 may be used to form a component of a gate structure or the like of the peripheral region. The polycrystalline silicon layer herein may be a polycrystalline silicon layer having a certain impurity concentration.
The process step of removing the peripheral functional material layer 701 in the array region includes:
forming an implantation barrier layer 800 on the polysilicon layer in the array region, please refer to fig. 3;
performing ion implantation on the polysilicon layer in the peripheral region based on the implantation blocking layer 800 to form doped polysilicon 711, please refer to fig. 3;
removing the implantation barrier layer 800, please refer to fig. 4;
the undoped polysilicon layer in the array region is removed and the doped polysilicon 711 in the peripheral region is retained, as shown in fig. 5.
In some embodiments, the implant block layer 800 may be a patterned photoresist layer. A photoresist may be coated on the entire surface of the polysilicon layer in the array region and the peripheral region. And removing the photoresist in the peripheral area based on a photoetching process, wherein the residual photoresist in the array area forms a patterned photoresist layer. Since the polysilicon layer of the array region is shielded by the implantation blocking layer 800, the polysilicon layer of the array region is not doped by the implanted ions. And the ion implantation is carried out on the polycrystalline silicon layer in the peripheral area, and the concentration of the ion implantation can be adjusted according to the actual process requirement. After forming the doped polysilicon 711, the doped polysilicon 711 may be used to form a component of a gate structure or the like. The work function of the gate structure subsequently formed in the peripheral region is easily controlled by pre-forming the doped polysilicon 711 with an adjustable doping concentration.
Specifically, the implantation barrier 800 may be removed after the doped polysilicon 711 is formed. Since the doped polysilicon 711 formed by ion implantation has different doping concentrations and different etching rates from the undoped polysilicon layer in the array region, the doped polysilicon 711 in the peripheral region can be retained while the undoped polysilicon layer in the array region is removed by wet etching.
In one embodiment, the undoped polysilicon layer of the array region may also be removed by dry self-aligned etching using the difference in etch rate between the doped polysilicon 711 and the undoped polysilicon layer.
In one embodiment, a third patterned mask layer may also be formed on the polysilicon layer on the substrate 100 (including the array region and the peripheral region) by a photolithography process. And removing the undoped polysilicon layer in the array region based on the third patterned mask layer.
In some embodiments, the doped polysilicon layer may also be formed directly, and then the ion implantation of the polysilicon layer in the peripheral region is not required.
In one embodiment, a method for forming a contact hole 100a includes:
forming a dielectric material layer 401 on the substrate 100 in the array region and on the peripheral functional material layer 701 in the peripheral region, please refer to fig. 6;
performing planarization processing on the dielectric material layer 401 to make the top surface of the dielectric material layer 401 in the array region flush with the top surface of the dielectric material layer 401 in the peripheral region, please refer to fig. 6;
forming a first patterned mask layer on the dielectric material layer 401, wherein the first patterned mask layer has an opening located in the array region, and the opening exposes the dielectric material layer 401 and defines the shape and position of the contact hole 100 a;
based on the first patterned mask layer, the dielectric material layer 401 and the substrate 100 are etched, and a portion of the dielectric material layer 401 and a portion of the substrate 100 are removed to form a contact hole 100a, as shown in fig. 7.
The material of the dielectric material layer 401 may include silicon dioxide or the like. To facilitate subsequent planarization, the dielectric material layer 401 may be formed to be thicker, for example, in a thickness range of 200nm to 1000 nm.
The thicker dielectric material layer 401 may be planarized by Chemical Mechanical Polishing (CMP) or the like.
The first patterned mask layer may comprise a multi-layer or a single-layer mask layer. Specifically, a multi-layer or single-layer first mask material layer 501 may be formed on the dielectric material layer 401, see fig. 6. Then, the first mask material layer 501 is subjected to patterning processing, thereby forming a first patterned mask layer (not shown).
Based on the first patterned mask layer, the dielectric material layer 401 is etched, and a portion of the dielectric material layer 401 is removed, so that the patterned insulating dielectric layer 400 is formed. At this time, the insulating dielectric layer 400 covers the peripheral functional material layer 701 in the peripheral region and the substrate 100 at the position of the array region where the contact hole 100a is not designed. The substrate 100 is then etched based on the patterned insulating dielectric layer 400, thereby forming the contact hole 100 a.
In this embodiment, the dielectric material layer 401 is formed, so that the substrate 100 in the array region and the peripheral functional material layer 701 in the peripheral region can be effectively protected when the first patterned mask layer is formed, and the substrate 100 and the peripheral functional material layer 701 are prevented from being damaged.
In one embodiment, the step of forming the contact hole 100a further includes removing the insulating dielectric layer 400, as shown in fig. 8. So as to form a contact material layer 201 with good quality in the contact hole 100a, and prevent the contact material layer 201 from being poorly filled due to the excessive depth of the filling hole during the filling process.
A contact material layer 201 is formed in the contact hole 100a, and the contact material layer 201 is formed on the surface of the doped polysilicon 711 in the peripheral region.
The contact material layer 201 may be the same material as the peripheral functional material layer 701, for example, polysilicon, so that it may be used as a component of a gate structure or the like in the peripheral region.
In one embodiment, a bit line material layer 301 is formed on the contact material layer 201 in the array region, the substrate 100 and the contact material layer 201 in the peripheral region, as shown in fig. 10. Forming a second patterned mask layer on the bit line material layer 301, wherein the second patterned mask layer includes a first mask pattern and a second mask pattern, the first mask pattern is located above the contact holes 100a in the array region, and the second mask pattern is located above the bit line material layer 301 in the peripheral region, as shown in fig. 11; based on the second patterned mask layer, the bit line material layer 301, the contact material layer 201, and the doped polysilicon 711 are etched to form a bit line structure in the array region and a gate structure in the peripheral region, as shown in fig. 12.
The second patterned mask layer may comprise a multi-layer or a single-layer mask layer. Specifically, a multi-layer or single-layer second mask material layer 601 may be formed on the bit line material layer 301, see fig. 11. A patterned photoresist mask 900 is formed on the second mask material layer 601 through a photolithography process. The second mask material layer 601 is patterned based on the photoresist mask 900, thereby forming a second patterned mask layer (not shown).
The bit line material layer 301 may be first etched based on the second patterned mask layer to remove portions of the bit line material layer 301, thereby forming the bit line layer 300.
In one embodiment, the bit line material layer 301 may include a barrier material layer 311, a conductive material layer 321, and an insulating material layer 331 stacked in sequence. At this time, after removing a portion of the bit line material layer 301, the remaining insulating material layer 331 constitutes the insulating layer 330, the remaining conductive material layer constitutes the conductive layer 320, and the remaining barrier material layer constitutes the barrier layer 310. The bit line layer 300 may include a barrier layer 310, a conductive layer 320, and an insulating layer 330.
Based on the bit line layer 300, the contact material layer 201 and the doped polysilicon 711 are etched to form the contact layer 200 and the doped layer 710. In the array region, the bit line layer 300 and the contact layer 200 constitute an integral part of the bit line structure. In the peripheral region, the bit line layer 300, the contact layer 200, and the doped layer 710 constitute a gate structure. By the manufacturing method of the embodiment, the height of the bit line structure can be controlled, the manufacturing of the grid electrode structure in the peripheral region can be integrated, the manufacturing efficiency is improved, and the manufacturing cost is reduced.
In one embodiment, the height of the gate structure in the peripheral region in the direction perpendicular to the substrate surface is greater than the height of the bit line structure in the direction perpendicular to the substrate surface, and the width of the gate structure in the peripheral region in the direction parallel to the substrate surface is greater than the width of the bit line structure in the direction parallel to the substrate surface.
In one embodiment, a semiconductor structure is provided, referring to fig. 12, including a substrate, a plurality of contact holes 100a (see fig. 8), and a bit line structure.
The base may include a substrate 110 and a dielectric layer formed on the substrate 110. The substrate 110 may include a silicon substrate or the like, in which an active region 111 may be disposed. The dielectric layer may include a first dielectric layer 121 (e.g., a silicon dioxide layer), a second dielectric layer 122 (e.g., a silicon nitride layer), and the like. The contact holes 100a are arranged in the substrate at intervals.
The bit line structure includes a contact layer 200 and a bit line layer 300, which are stacked. The contact layer 200 is located in the contact hole 100a, and the bit line layer 300 spans the contact hole 100a and the substrate 100 outside the contact hole 100 a.
In one embodiment, the substrate includes an array region and a peripheral region adjacent to each other, and the plurality of contact holes 100a are located in the array region.
In one embodiment, the bit line layer 300 includes a barrier layer 310, a conductive layer 320, and an insulating layer 330, which are sequentially stacked. The semiconductor structure also includes a gate structure located in the peripheral region. The gate structure includes a contact layer 200 and a bit line layer 300.
In one embodiment, the method further comprises: a plurality of active regions 111 arranged at intervals on the substrate 110, wherein the top surface of the contact layer 200 is lower than the top surface of the active regions 111.
In one embodiment, the height of the gate structure in the peripheral region in the direction perpendicular to the substrate surface is greater than the height of the bit line structure in the direction perpendicular to the substrate surface, and the width of the gate structure in the peripheral region in the direction parallel to the substrate surface is greater than the width of the bit line structure in the direction parallel to the substrate surface.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (17)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of contact holes arranged at intervals in the substrate;
forming a contact material layer in the contact hole;
forming a bit line material layer on the contact material layer and the substrate;
and removing part of the bit line material layer and part of the contact material layer to form a bit line structure, wherein the bit line structure comprises the bit line layer formed by the rest of the bit line material layer and the contact layer formed by the rest of the contact material layer, the contact layer is positioned in the contact hole, and the bit line layer spans the contact hole and the substrate outside the contact hole.
2. The method of claim 1, wherein the forming a plurality of contact holes spaced apart on the substrate comprises:
forming a dielectric material layer on the substrate;
forming a first graphical mask layer on the medium material layer;
and etching the dielectric material layer and the substrate based on the first graphical mask layer, removing part of the dielectric material layer and part of the substrate, and forming the contact hole.
3. The method for manufacturing a semiconductor structure according to claim 2, wherein before forming a contact material layer in the contact hole, the method comprises:
and removing the remained dielectric material layer.
4. The method of claim 3, wherein the removing the portion of the bit line material layer and the portion of the contact material layer to form the bit line structure comprises:
forming a second patterned mask layer on the bit line material layer;
and etching the bit line material layer and the contact material layer based on the second patterned mask layer, and removing part of the bit line material layer and part of the contact material layer to form the bit line structure.
5. The method of claim 1, wherein the step of forming the semiconductor structure comprises the step of forming a semiconductor layer on the substrate,
the substrate is provided with an array region and a peripheral region which are adjacent, and a plurality of contact holes which are arranged at intervals are formed on the substrate, and the contact holes comprise:
forming a peripheral functional material layer on the substrate;
removing the peripheral functional material layer of the array region;
and forming the contact hole on the substrate of the array region.
6. The method as claimed in claim 5, wherein the peripheral functional material layer comprises a polysilicon layer, and the removing the peripheral functional material layer in the array region comprises:
forming an injection blocking layer on the polycrystalline silicon layer of the array region;
based on the injection blocking layer, carrying out ion injection on the polycrystalline silicon layer of the peripheral area to form doped polycrystalline silicon;
removing the injection blocking layer;
removing the undoped polysilicon layer of the array region and retaining the doped polysilicon of the peripheral region.
7. The method of claim 6, wherein the removing the undoped polysilicon layer of the array region and the remaining doped polysilicon of the peripheral region comprises:
and removing the undoped polysilicon layer of the array region by utilizing a wet method or dry method self-aligned etching mode.
8. The method as claimed in claim 6, wherein the forming of the contact hole on the substrate of the array region comprises:
forming a dielectric material layer on the substrate of the array region and the peripheral functional material layer of the peripheral region;
carrying out planarization treatment on the dielectric material layer to enable the top surface of the dielectric material layer in the array area to be flush with the top surface of the dielectric material layer in the peripheral area;
forming a first graphical mask layer on the dielectric material layer, wherein the first graphical mask layer is provided with an opening positioned in the array area, and the opening exposes the dielectric material layer and defines the shape and the position of the contact hole;
and etching the dielectric material layer and the substrate based on the first patterned mask layer, removing part of the dielectric material layer and part of the substrate, and forming the contact hole.
9. The method for manufacturing a semiconductor structure according to claim 8, wherein before forming a contact material layer in the contact hole, the method comprises:
removing the remaining dielectric material layer;
the forming of the contact material layer in the contact hole includes:
and forming the contact material layer in the contact hole, and forming the contact material layer on the surface of the doped polysilicon.
10. The method of claim 9, wherein forming a layer of bitline material over the layer of contact material and the substrate comprises:
forming the bit line material layer on the contact material layer of the array region, the substrate, and the contact material layer of the peripheral region.
11. The method of claim 10, wherein removing the portion of the contact material layer and the portion of the bit line material layer comprises:
forming a second patterned mask layer on the bit line material layer, wherein the second patterned mask layer comprises a first mask pattern and a second mask pattern, the first mask pattern is located above the contact holes of the array region, and the second mask pattern is located above the bit line material layer of the peripheral region;
and etching the bit line material layer, the contact material layer and the doped polysilicon based on the second patterned mask layer to form the bit line structure of the array region and the gate structure of the peripheral region.
12. The method of claim 1, wherein the bit line material layer comprises a barrier material layer, a conductive material layer and an insulating material layer sequentially stacked, wherein the barrier material layer is formed on the contact material layer and the substrate.
13. A semiconductor structure, comprising:
a substrate;
a plurality of contact holes arranged in the substrate at intervals;
the bit line structure comprises a contact layer and a bit line layer which are stacked, wherein the contact layer is positioned in the contact hole, and the bit line layer spans the contact hole and the substrate outside the contact hole.
14. The semiconductor structure of claim 13, wherein the substrate comprises adjacent array and peripheral regions, the plurality of contact holes being located in the array region.
15. The semiconductor structure of claim 14, wherein the bit line layer comprises a barrier layer, a conductive layer, and an insulating layer stacked in this order, the semiconductor structure further comprising:
the grid structure is positioned in the peripheral region;
wherein the gate structure includes the contact layer and the bit line layer.
16. The semiconductor structure of claim 15, further comprising:
the semiconductor device comprises a plurality of spaced active regions on a substrate, wherein the top surface of the contact layer is lower than the top surface of the active regions.
17. The semiconductor structure of claim 15, wherein the gate structures of the peripheral region have a height in a direction perpendicular to the substrate surface that is greater than a height of the bit line structures in a direction perpendicular to the substrate surface, and wherein the gate structures of the peripheral region have a width in a direction parallel to the substrate surface that is greater than a width of the bit line structures in a direction parallel to the substrate surface.
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