CN113452354B - RS trigger based on MTJ device - Google Patents

Abstract

An RS trigger based on an MTJ device relates to the technical field of integrated circuits. The invention aims to solve the problems of flip and poor anti-jamming capability in the traditional RS trigger. The invention relates to an RS trigger based on an MTJ device, which comprises: the dual-path pre-charging sensitive amplifier is used for reading information stored in the two pairs of MTJ devices through the CMOS dual-rail circuit. The invention realizes the RS trigger function by combining two pairs of MTJ devices with a CMOS circuit. The MTJ has the characteristic of non-volatility, and the memory content in the MTJ can not be changed in a reading stage. The addition of the write circuit can control the MTJ to switch between a write mode and a read mode.

Description

A kind of RS flip-flop based on MTJ device

technical field

The invention belongs to the technical field of integrated circuits, in particular to an RS flip-flop.

Background technique

A flip-flop is a basic logic unit that has a memory function and can store digital signals. The RS flip-flop is also known as a reset-set flip-flop (R-reset RESET, S-set SET), and its basic structure is formed by cross-connecting the input and output terminals of two NAND gates (NOR gates).

和

变化，输出信号Q就发生变化。这就造成一个问题：在时钟有效期间，只要输入信号发生变化，输出信号就可能发生变化，造成输出信号在一个时钟周期之内翻转两次或两次以上，也就是空翻现象。为了克服RS触发器的空翻现象，又出现了主从结构的RS触发器。这种触发器虽然输出信号在一个时钟周期内只变化一次，但是输入信号可能会受到干扰，造成输出结果错误。所以，这种触发器的抗干扰能力依然不强。Traditional clocked RS flip-flops are level triggered. During the active level, as long as the input

with

Change, the output signal Q changes. This creates a problem: during the effective period of the clock, as long as the input signal changes, the output signal may change, causing the output signal to flip twice or more within one clock cycle, that is, a flipping phenomenon. In order to overcome the overturning phenomenon of the RS flip-flop, the RS flip-flop of the master-slave structure has appeared. Although the output signal of this kind of flip-flop only changes once in a clock cycle, the input signal may be disturbed, causing the output result to be wrong. Therefore, the anti-interference ability of this trigger is still not strong.

To sum up, the traditional RS flip-flop has the problems of somersault and poor anti-interference ability.

Contents of the invention

The purpose of the present invention is to solve the problems of overturning and poor anti-interference ability in the traditional RS flip-flop, and now provides an RS flip-flop based on an MTJ device.

An RS flip-flop based on MTJ devices, including: dual precharge sensitive amplifiers, CMOS dual-rail circuits, two pairs of MTJ devices and two write circuits, the two write circuits are used to write information to the two pairs of MTJ devices respectively , the dual-way precharge sensitive amplifier reads the information stored in the two pairs of MTJ devices through the CMOS dual-rail circuit.

Further, the above writing circuit includes: NMOS transistors MN11-MN16, PMOS transistor MP11 and PMOS transistor MP12,

The drain of the NMOS transistor MN13 is the first clock signal terminal of the writing circuit, the source of the NMOS transistor MN14 is the second clock signal terminal of the writing circuit, the drain of the NMOS transistor MN15 is the third clock signal terminal of the writing circuit, and the NMOS transistor MN15 is the third clock signal terminal of the writing circuit. The source of MN16 is the fourth clock signal terminal of the writing circuit, the clock signals of the first clock signal terminal and the fourth clock signal terminal are complementary clock signals, and the clock signals of the second clock signal terminal and the third clock signal terminal are complementary clock signals Signal,

The gate of the NMOS transistor MN13 and the gate of the NMOS transistor MN16 are jointly used as the first writing control signal input end of the writing circuit, and the gate of the NMOS transistor MN14 and the gate of the NMOS transistor MN15 are jointly used as the second writing terminal of the writing circuit. Into the control signal input terminal,

The source of the NMOS transistor MN13 is connected to the gate of the PMOS transistor MP11, the drain of the NMOS transistor MN14 is connected to the gate of the NMOS transistor MN11, the source of the NMOS transistor MN15 is connected to the gate of the PMOS transistor MP12, and the drain of the NMOS transistor MN16 is connected to the NMOS the gate of tube MN12,

The drain of the PMOS transistor MP11 and the drain of the NMOS transistor MN11 are jointly used as the writing current A connection end of the writing circuit, and the drain of the PMOS transistor MP12 and the drain of the NMOS transistor MN12 are jointly used as the writing current B connection of the writing circuit. end,

The source of the PMOS transistor MP11 and the source of the PMOS transistor MP12 are connected to the positive pole of the power supply, and the sources of the NMOS transistor MN11 and the source of the NMOS transistor MN12 are connected to the negative pole of the power supply.

Further, the above two pairs of MTJ devices are respectively MTJ devices MTJ1-MTJ4,

Each MTJ device includes two ferromagnetic layers and an oxide barrier layer between the two ferromagnetic layers,

MTJ devices MTJ1 and MTJ1 correspond to one writing circuit, and MTJ devices MTJ3 and MTJ4 correspond to another writing circuit.

A ferromagnetic layer of the MTJ device MTJ1 is connected to a write current A connection end of a write circuit, and a ferromagnetic layer of the MTJ device MTJ2 is connected to a write current B connection end of a write circuit,

A ferromagnetic layer of the MTJ device MTJ3 is connected to the write current A connection end of another write circuit, and a ferromagnetic layer of the MTJ device MTJ4 is connected to the write current B connection end of the other write circuit.

Further, the material of the ferromagnetic layer is CoFeB, and the material of the oxide barrier layer is MgO.

Further, the above-mentioned precharge sensitive amplifier includes: PMOS transistor MP1, PMOS transistor MP2, PMOS transistor TP1, PMOS transistor TP2, NMOS transistor TN1, NMOS transistor TN2, capacitor C1 and capacitor C2,

Another pre-charge sensitive amplifier includes: PMOS transistor MP3, PMOS transistor MP4, PMOS transistor TP3, PMOS transistor TP4, NMOS transistor TN3, NMOS transistor TN4, capacitor C3 and capacitor C4,

The gates of the PMOS transistors MP1-MP4 are all input terminals of the clock signal clk, the sources of the PMOS transistors MP1-MP4 and the sources of the PMOS transistors TP1-TP4 are connected to the positive pole of the power supply,

The drain of the PMOS transistor MP1, the drain of the PMOS transistor TP1, the drain of the NMOS transistor TN1, the gate of the PMOS transistor TP2, the gate of the NMOS transistor TN2 are connected to one end of the capacitor C1, and together serve as the Q output of the RS flip-flop end,

输出端，The drain of the PMOS transistor MP2, the drain of the PMOS transistor TP2, the drain of the NMOS transistor TN2, the gate of the PMOS transistor TP1, the gate of the NMOS transistor TN1 are connected to one end of the capacitor C2, and together serve as the RS flip-flop

output terminal,

输出端，The drain of the PMOS transistor MP4, the drain of the PMOS transistor TP4, the drain of the NMOS transistor TN4, the gate of the PMOS transistor TP3, the gate of the NMOS transistor TN3 are connected to one end of the capacitor C4, and together serve as the RS flip-flop

output terminal,

The drain of the PMOS transistor MP3, the drain of the PMOS transistor TP3, the drain of the NMOS transistor TN3, the gate of the PMOS transistor TP4, the gate of the NMOS transistor TN4 are connected to one end of the capacitor C3, and together serve as the Q' of the RS flip-flop output terminal,

The other ends of the capacitors C1 - C4 are all connected to the power ground.

Further, the above CMOS dual-rail circuit includes: NMOS transistors T1-T6 and NMOS transistors MN1-MN6,

The gates of the NMOS transistors MN1-MN6 are all input terminals of the clock signal clk of the CMOS dual-rail circuit,

输出端，NMOS管MN3的漏极连接Q'输出端，NMOS管MN4的漏极连接

输出端，The drain of the NMOS transistor MN1 is connected to the Q output terminal, and the drain of the NMOS transistor MN2 is connected to

The output terminal, the drain of the NMOS transistor MN3 is connected to the Q' output terminal, and the drain of the NMOS transistor MN4 is connected to

output terminal,

The source of NMOS transistor MN4 is connected to the gates of NMOS transistors T1 and T2 at the same time, the source of NMOS transistor MN3 is connected to the gate of NMOS transistor T3, the source of NMOS transistor MN2 is connected to the gate of NMOS transistor T5, and the source of NMOS transistor MN1 The pole is connected to the gates of NMOS transistors T4 and T6,

The drain of NMOS transistor T1 is connected to the source of NMOS transistor TN1, the drain of NMOS transistor T4 is connected to the source of NMOS transistor TN4, the source of NMOS transistor TN2 is connected to the drains of NMOS transistors T2 and T3, and the source of NMOS transistor TN3 The pole is connected to the drains of NMOS transistors T5 and T6 at the same time,

The source of the NMOS transistor T1 is connected to a ferromagnetic layer of the MTJ device MTJ1, the sources of the NMOS transistors T2 and T3 are simultaneously connected to a ferromagnetic layer of the MTJ device MTJ2, and the source of the NMOS transistor T4 is connected to a ferromagnetic layer of the MTJ device MTJ3 , the sources of the NMOS transistors T5 and T6 are simultaneously connected to a ferromagnetic layer of the MTJ device MTJ4,

The drain of the NMOS transistor MN5 is connected to another ferromagnetic layer of the MTJ devices MTJ1 and MTJ2 at the same time, and the drain of the NMOS transistor MN6 is connected to the other ferromagnetic layer of the MTJ devices MTJ3 and MTJ4 at the same time,

The sources of the NMOS transistors MN5 and MN6 are simultaneously connected to the negative pole of the power supply.

An RS flip-flop based on MTJ devices described in the present invention uses two pairs of MTJ devices combined with a CMOS circuit to realize the RS flip-flop function. MTJ is non-volatile, and the storage content in MTJ will not change during the read phase. The MTJ device is used to save the input signal of the RS flip-flop, which ensures that the input signal of the RS flip-flop does not change within a clock cycle, and effectively overcomes the problems of somersaults and poor anti-interference ability in the traditional basic RS flip-flop.

Further, a writing circuit is added, which can control the MTJ to switch between writing mode and reading mode. In write mode, write operations to the MTJ are reliably performed. In the read mode, according to the stored content in the MTJ, the function of the RS flip-flop is completed. At the same time, different from the traditional writing circuit, the present invention controls the writing time by controlling the writing clock timing through the MOS tube switch, and realizes flexible control of the MTJ writing time while reducing one MOS tube in the writing power supply voltage direction.

Description of drawings

Fig. 1 is a structural schematic diagram of a pair of MTJ devices;

Fig. 2 is a functional block diagram of an RS flip-flop based on an MTJ device, wherein the solid line represents the write signal, and the dotted line represents the current;

Fig. 3 is a kind of circuit structural diagram of the RS flip-flop based on MTJ device;

Fig. 4 is the circuit structural diagram of writing circuit;

Figure 5 is a timing diagram for reading and writing RS flip-flops;

FIG. 6 is a circuit structure diagram of a conventional writing circuit.

detailed description

Some of the existing functional circuits using MTJ can only write to MTJ once, and some can write to MTJ periodically by setting regular clocks (clk1 and clk2), but there is no guarantee that the circuit can be written at any time and cycle at the same time. Sex writes two functions. If you need to write at any time, generally add a control MOS transistor in the direction of the power supply voltage of the write circuit, and the gate of the MOS transistor is connected to the write enable signal EN, as shown in Figure 6. This structure is in the direction of the write power supply. The increase in the number of tubes leads to an increase in the power supply voltage required to maintain conduction, thereby increasing the MTJ writing power consumption. For this reason, an RS flip-flop based on an MTJ device described in the first specific embodiment is given. The RS flip-flop controls the writing clock by adding a control tube, which reduces the number of MOS transistors in the power supply voltage direction of the writing clock. To achieve the purpose of reducing write power consumption. The specific institutions are as follows:

Specific Embodiment 1: As shown in Figure 2, an RS flip-flop based on MTJ devices described in this embodiment includes: dual pre-charge sensitive amplifiers, CMOS dual-rail circuits, two pairs of MTJ devices and two write circuits , the two writing circuits are respectively used to write information to the two pairs of MTJ devices, and the dual pre-charging sensitive amplifier reads the information stored in the two pairs of MTJ devices through the CMOS dual-rail circuit.

The above two pairs of MTJ devices are respectively MTJ devices MTJ1-MTJ4, MTJ devices MTJ1 and MTJ2 form a pair, and MTJ devices MTJ3 and MTJ4 form another pair. The basic structure of an MTJ device is shown in Figure 1. Each MTJ device is a three-layer structure consisting of two ferromagnetic layers (CoFeB) and an oxide (MgO) barrier layer between the two ferromagnetic layers.

Depending on the relative magnetization of the ferromagnetic layers, an MTJ device can have two different resistance states. MTJ devices will exhibit low or high resistance characteristics. In Figure 1, when the relative magnetization of the ferromagnetic layers is parallel, the MTJ device will exhibit low resistance, and the device can be represented as a logic "1"; when the relative magnetization of the ferromagnetic layers is antiparallel, the MTJ device will exhibit high resistance , MTJ can be represented by logic "0". In order to change the MTJ state, it is necessary to change the relative magnetization of the ferromagnetic layers, that is, "write" to the MTJ. In general, the magnetization of one of the ferromagnetic layers is fixed, while the magnetization of the other ferromagnetic layer can be changed. In order to write to the MTJ, a large quasi-direction current (about 100uA) is required. To change the relative magnetization direction of the ferromagnetic layer.

和S的值；MTJ3和MTJ2内分别存储

和R的值。The application of MTJ storage unit in RS flip-flop can make full use of the non-volatile characteristics of MTJ, and store the input signal in MTJ. Within one clock cycle, the storage content in MTJ will not change, so it has strong resistance Interference ability. At the same time, the writing and reading speed of MTJ is very fast, which ensures the speed of flip-flop. In this embodiment, MTJ1 and MTJ2 store respectively

and the value of S; MTJ3 and MTJ2 respectively store

and the value of R.

Further, in order to control the switching of the RS flip-flops between normal working states, it is necessary to effectively write to the two pairs of MTJs according to timing. Therefore, in this embodiment, one writing circuit is designed for each of the two pairs of MTJ devices, and the two writing circuits have the same structure. MTJ devices MTJ1 and MTJ1 correspond to one writing circuit, and MTJ devices MTJ3 and MTJ4 correspond to another writing circuit. As shown in FIG. 4 , taking the MTJ device MTJ1 and the writing circuit corresponding to MTJ1 as an example, the writing circuit includes: NMOS transistors MN11 - MN16 , PMOS transistor MP11 and PMOS transistor MP12 .

The drain of the NMOS transistor MN13 is the first clock signal terminal of the writing circuit, the source of the NMOS transistor MN14 is the second clock signal terminal of the writing circuit, the drain of the NMOS transistor MN15 is the third clock signal terminal of the writing circuit, and the NMOS transistor MN15 is the third clock signal terminal of the writing circuit. The source of MN16 is the fourth clock signal terminal of the writing circuit. The clock signals at the first clock signal terminal and the fourth clock signal terminal are complementary clock signals, and the clock signals at the second clock signal terminal and the third clock signal terminal are complementary clock signals.

The gate of the NMOS transistor MN13 and the gate of the NMOS transistor MN16 are jointly used as the first writing control signal input end of the writing circuit, and the gate of the NMOS transistor MN14 and the gate of the NMOS transistor MN15 are jointly used as the second writing terminal of the writing circuit. into the control signal input terminal. The source of the NMOS transistor MN13 is connected to the gate of the PMOS transistor MP11, the drain of the NMOS transistor MN14 is connected to the gate of the NMOS transistor MN11, the source of the NMOS transistor MN15 is connected to the gate of the PMOS transistor MP12, and the drain of the NMOS transistor MN16 is connected to the NMOS Gate of tube MN12. The source of the PMOS transistor MP11 and the source of the PMOS transistor MP12 are commonly connected to the positive pole of the power supply of the writing circuit, and the sources of the NMOS transistor MN11 and the source of the NMOS transistor MN12 are commonly connected to the negative pole of the power supply of the writing circuit. The drain of the PMOS transistor MP11 and the drain of the NMOS transistor MN11 are jointly used as a writing current A connection terminal of the writing circuit, and the writing current A connection terminal is connected to a ferromagnetic layer of the MTJ device MTJ1 . The drain of the PMOS transistor MP12 and the drain of the NMOS transistor MN12 are jointly used as a write current B connection terminal of the write circuit, and the write current B connection terminal is connected to a ferromagnetic layer of the MTJ device MTJ2. Similarly, a ferromagnetic layer of the MTJ device MTJ3 is connected to the write current A connection terminal of another write circuit, and a ferromagnetic layer of the MTJ device MTJ4 is connected to the write current B connection terminal of the other write circuit.

Further, as shown in Figure 3, one pre-charging sensitive amplifier includes: PMOS transistor MP1, PMOS transistor MP2, PMOS transistor TP1, PMOS transistor TP2, NMOS transistor TN1, NMOS transistor TN2, capacitor C1 and capacitor C2; another pre-charging The sensitive amplifier includes: PMOS transistor MP3, PMOS transistor MP4, PMOS transistor TP3, PMOS transistor TP4, NMOS transistor TN3, NMOS transistor TN4, capacitor C3 and capacitor C4. The CMOS dual-rail circuit includes: NMOS transistors T1-T6 and NMOS transistors MN1-MN6.

输出端。PMOS管MP4的漏极、PMOS管TP4的漏极、NMOS管TN4的漏极、PMOS管TP3的栅极、NMOS管TN3的栅极和电容C4的一端相连、并共同作为RS触发器的

输出端。PMOS管MP3的漏极、PMOS管TP3的漏极、NMOS管TN3的漏极、PMOS管TP4的栅极、NMOS管TN4的栅极和电容C3的一端相连、并共同作为RS触发器的Q'输出端。电容C1～C4的另一端均连接电源地。NMOS管MN1～MN6的栅极均为CMOS双轨电路的时钟信号clk的输入端。NMOS管MN1的漏极连接Q输出端，NMOS管MN2的漏极连接

输出端，NMOS管MN3的漏极连接Q'输出端，NMOS管MN4的漏极连接

输出端。NMOS管MN4的源极同时连接NMOS管T1和T2的栅极，NMOS管MN3的源极连接NMOS管T3的栅极，NMOS管MN2的源极连接NMOS管T5的栅极，NMOS管MN1的源极连接NMOS管T4和T6的栅极。NMOS管T1的漏极连接NMOS管TN1的源极，NMOS管T4的漏极连接NMOS管TN4的源极，NMOS管TN2的源极同时连接NMOS管T2和T3的漏极，NMOS管TN3的源极同时连接NMOS管T5和T6的漏极。NMOS管T1的源极连接MTJ器件MTJ1的一个铁磁层，NMOS管T2和T3的源极同时连接MTJ器件MTJ2的一个铁磁层，NMOS管T4的源极连接MTJ器件MTJ3的一个铁磁层，NMOS管T5和T6的源极同时连接MTJ器件MTJ4的一个铁磁层。NMOS管MN5的漏极同时连接MTJ器件MTJ1和MTJ2的另一个铁磁层，NMOS管MN6的漏极同时连接MTJ器件MTJ3和MTJ4的另一个铁磁层。NMOS管MN5和MN6的源极同时连接RS触发器的电源负极。The gates of the PMOS transistors MP1-MP4 are all input terminals of the clock signal clk, and the sources of the PMOS transistors MP1-MP4 and the sources of the PMOS transistors TP1-TP4 are connected to the positive pole of the power supply of the RS flip-flop. The drain of the PMOS transistor MP1, the drain of the PMOS transistor TP1, the drain of the NMOS transistor TN1, the gate of the PMOS transistor TP2, the gate of the NMOS transistor TN2 are connected to one end of the capacitor C1, and together serve as the Q output of the RS flip-flop end. The drain of the PMOS transistor MP2, the drain of the PMOS transistor TP2, the drain of the NMOS transistor TN2, the gate of the PMOS transistor TP1, the gate of the NMOS transistor TN1 are connected to one end of the capacitor C2, and together serve as the RS flip-flop

output. The drain of the PMOS transistor MP4, the drain of the PMOS transistor TP4, the drain of the NMOS transistor TN4, the gate of the PMOS transistor TP3, the gate of the NMOS transistor TN3 are connected to one end of the capacitor C4, and together serve as the RS flip-flop

output. The drain of the PMOS transistor MP3, the drain of the PMOS transistor TP3, the drain of the NMOS transistor TN3, the gate of the PMOS transistor TP4, the gate of the NMOS transistor TN4 are connected to one end of the capacitor C3, and together serve as the Q' of the RS flip-flop output. The other ends of the capacitors C1 - C4 are all connected to the power ground. The gates of the NMOS transistors MN1 - MN6 are all input terminals of the clock signal clk of the CMOS dual-rail circuit. The drain of the NMOS transistor MN1 is connected to the Q output terminal, and the drain of the NMOS transistor MN2 is connected to

The output terminal, the drain of the NMOS transistor MN3 is connected to the Q' output terminal, and the drain of the NMOS transistor MN4 is connected to

output. The source of NMOS transistor MN4 is connected to the gates of NMOS transistors T1 and T2 at the same time, the source of NMOS transistor MN3 is connected to the gate of NMOS transistor T3, the source of NMOS transistor MN2 is connected to the gate of NMOS transistor T5, and the source of NMOS transistor MN1 The pole is connected to the gates of NMOS transistors T4 and T6. The drain of NMOS transistor T1 is connected to the source of NMOS transistor TN1, the drain of NMOS transistor T4 is connected to the source of NMOS transistor TN4, the source of NMOS transistor TN2 is connected to the drains of NMOS transistors T2 and T3, and the source of NMOS transistor TN3 The pole is connected to the drains of NMOS transistors T5 and T6 at the same time. The source of the NMOS transistor T1 is connected to a ferromagnetic layer of the MTJ device MTJ1, the sources of the NMOS transistors T2 and T3 are simultaneously connected to a ferromagnetic layer of the MTJ device MTJ2, and the source of the NMOS transistor T4 is connected to a ferromagnetic layer of the MTJ device MTJ3 , the sources of the NMOS transistors T5 and T6 are simultaneously connected to a ferromagnetic layer of the MTJ device MTJ4. The drain of the NMOS transistor MN5 is connected to the other ferromagnetic layer of the MTJ devices MTJ1 and MTJ2 at the same time, and the drain of the NMOS transistor MN6 is connected to the other ferromagnetic layer of the MTJ devices MTJ3 and MTJ4 at the same time. The sources of the NMOS transistors MN5 and MN6 are simultaneously connected to the negative pole of the power supply of the RS flip-flop.

The function table of the RS flip-flop is shown in Table 1:

时，如果触发器现态Qⁿ为0，则次态Qⁿ⁺¹为0；如果现态Qⁿ为0，则次态Qⁿ⁺¹也为0，此状态为置“0”态；1. When input

, if the current state Q ⁿ of the flip-flop is 0, then the next state Q ⁿ⁺¹ is 0; if the current state Q ⁿ is 0, then the next state Q ⁿ⁺¹ is also 0, and this state is the “0” state;

时，如果触发器现态Qⁿ为0，则次态Qⁿ⁺¹为1；如果现态Qⁿ为1，则次态Qⁿ⁺¹也为1，此状态置“1”态；2. When input

, if the current state Q ⁿ of the flip-flop is 0, then the next state Q ⁿ⁺¹ is 1; if the current state Q ⁿ is 1, then the next state Q ⁿ⁺¹ is also 1, and this state is set to "1"state;

和

时，如果触发器现态Qⁿ为0，则次态Qⁿ⁺¹为0；如果现态Qⁿ为1，则次态Qⁿ⁺¹也为1，此状态为保持态；3. When input

with

, if the current state Q ⁿ of the flip-flop is 0, then the next state Q ⁿ⁺¹ is 0; if the current state Q ⁿ is 1, then the next state Q ⁿ⁺¹ is also 1, and this state is a hold state;

和

时，触发器的次态不能确定，称为不定态。4. When input

with

When , the next state of the flip-flop cannot be determined, which is called an indeterminate state.

Table 1 RS flip-flop function table

和

的值；在输出模式下，触发器输出，实现RS触发器功能。The RS flip-flop based on the MTJ device described in this embodiment can work in two modes, ie input mode and output mode. In input mode, it is possible to write to the MTJ to set the input signal

with

The value of; in the output mode, the flip-flop output realizes the RS flip-flop function.

端拉到高电平。Input mode: when clk=0, it is the input mode. At this time, MN1~MN6 are turned off, MP1~MP4 are turned on, and the capacitors C1~C4 are charged, and Q and

terminal is pulled high.

和

的值得到触发器输出端Q和

的值，实现RS触发器功能。Output mode: when clk=1, it is the output mode, at this time MN1-MN6 are turned on, and MP3 and MP4 are turned off. According to the input signal

with

The value of flip-flop output Q and

value to implement the RS flip-flop function.

The working principle of the flip-flop in output mode is as follows:

Qⁿ＝0，则T1、T2和T5打开，T3、T4和T6关闭。此时在RS触发器中形成(T1-MTJ1)、(T2-MTJ2)、(T5-MTJ4)3条通路。由于MTJ1和MTJ4内存储内容为1，MTJ2内存储内容为0。存储内容为1的MTJ处于低阻态，通过的电流较大，所以Q端先到达低电平，稍后

到达高电平，输出Qⁿ⁺¹为0。1. If

Q ⁿ =0, then T1, T2 and T5 are turned on, and T3, T4 and T6 are turned off. At this time, three paths (T1-MTJ1), (T2-MTJ2), and (T5-MTJ4) are formed in the RS flip-flop. Since the storage content in MTJ1 and MTJ4 is 1, the storage content in MTJ2 is 0. The MTJ with the storage content of 1 is in a low resistance state, and the current passing through is relatively large, so the Q terminal reaches the low level first, and later

When it reaches a high level, the output Q ⁿ⁺¹ is 0.

Qⁿ＝1，则T3、T4和T6打开，T1、T2和T5关闭。此时在RS触发器中形成(T3-MTJ2)、(T4-MTJ3)、(T6-MTJ4)3条通路。由于MTJ1和MTJ4内存储内容为1，MTJ2和MTJ3内存储内容为0。存储内容为1的MTJ处于低阻态，通过的电流较大，所以Q'端先到达低电平，稍后

到达高电平。紧接着T1打开，形成(T1-MTJ1)通路，Q到达低电平，输出Qⁿ⁺¹为0。if

Q ⁿ =1, then T3, T4 and T6 are turned on, and T1, T2 and T5 are turned off. At this time, three paths (T3-MTJ2), (T4-MTJ3), and (T6-MTJ4) are formed in the RS flip-flop. Since the storage content in MTJ1 and MTJ4 is 1, the storage content in MTJ2 and MTJ3 is 0. The MTJ with the storage content of 1 is in a low-resistance state, and the current passing through it is relatively large, so the Q' terminal reaches the low level first, and later

reaches a high level. Immediately after T1 is turned on, a (T1-MTJ1) path is formed, Q reaches a low level, and the output Q ⁿ⁺¹ is 0.

The above states are set to "0".

Qⁿ＝0，则MOS管T1、T2和T5打开，T3、T4和T6关闭。此时在RS触发器中形成(T1-MTJ1)、(T2-MTJ2)、(T5-MTJ4)3条通路。由于MTJ2和MTJ3内存储内容为1，MTJ1和MTJ4内存储内容为0。存储内容为1的MTJ处于低阻态，通过的电流较大，所以

端先到达低电平，稍后Q到达高电平。紧接着T4打开，形成(T4-MTJ3)通路，

到达低电平，Q到达高电平，输出Qⁿ⁺¹为1。2. If

If Q ⁿ =0, then MOS transistors T1, T2 and T5 are turned on, and T3, T4 and T6 are turned off. At this time, three paths (T1-MTJ1), (T2-MTJ2), and (T5-MTJ4) are formed in the RS flip-flop. Since the storage content in MTJ2 and MTJ3 is 1, the storage content in MTJ1 and MTJ4 is 0. The MTJ whose storage content is 1 is in a low resistance state, and the current passing through is relatively large, so

Terminal reaches low level first, and Q reaches high level later. Immediately after T4 opens, the (T4-MTJ3) pathway is formed,

When it reaches the low level, Q reaches the high level, and the output Q ⁿ⁺¹ is 1.

Qⁿ＝1，则MOS管T3、T4和T6打开，T1、T2和T5关闭。此时在RS触发器中形成(T3-MTJ2)、(T4-MTJ3)、(T6-MTJ4)3条通路。由于MTJ2和MTJ3内存储内容为1，MTJ1和MTJ4内存储内容为0。存储内容为1的MTJ处于低阻态，通过的电流较大，所以

端和

端先到达低电平，稍后Q到达高电平，输出Qⁿ⁺¹为1。if

Q ⁿ =1, then MOS transistors T3, T4 and T6 are turned on, and T1, T2 and T5 are turned off. At this time, three paths (T3-MTJ2), (T4-MTJ3), and (T6-MTJ4) are formed in the RS flip-flop. Since the storage content in MTJ2 and MTJ3 is 1, the storage content in MTJ1 and MTJ4 is 0. The MTJ whose storage content is 1 is in a low resistance state, and the current passing through is relatively large, so

End and

Terminal first reaches the low level, and later Q reaches the high level, and the output Qn ⁺¹ is 1.

The above states are set to "1".

Qⁿ＝0，则MOS管T1、T2和T5打开，T3、T4和T6关闭。此时在RS触发器中形成(T1-MTJ1)、(T2-MTJ2)、(T5-MTJ4)3条通路。由于MTJ1和MTJ3内存储内容为1，MTJ2和MTJ4内存储内容为0。存储内容为1的MTJ处于低阻态，通过的电流较大，所以Q端先到达低电平。然后Q'到达低电平，

到达高电平，输出Qⁿ⁺¹为0。3. If

If Q ⁿ =0, then MOS transistors T1, T2 and T5 are turned on, and T3, T4 and T6 are turned off. At this time, three paths (T1-MTJ1), (T2-MTJ2), and (T5-MTJ4) are formed in the RS flip-flop. Since the storage content in MTJ1 and MTJ3 is 1, the storage content in MTJ2 and MTJ4 is 0. The MTJ whose storage content is 1 is in a low resistance state, and the current passing through is relatively large, so the Q terminal reaches the low level first. Then Q' goes low,

When it reaches a high level, the output Q ⁿ⁺¹ is 0.

Qⁿ＝1，则MOS管T3、T4和T6打开，T1、T2和T5关闭。此时在RS触发器中形成(T3-MTJ2)、(T4-MTJ3)、(T6-MTJ4)3条通路。由于MTJ1和MTJ3内存储内容为1，MTJ2和MTJ4内存储内容为0。存储内容为1的MTJ处于低阻态，通过的电流较大，所以

端先到达低电平，稍后Q'到达高电平。接着

到达低电平，Q到达高电平，输出Qⁿ⁺¹为1。if

Q ⁿ =1, then MOS transistors T3, T4 and T6 are turned on, and T1, T2 and T5 are turned off. At this time, three paths (T3-MTJ2), (T4-MTJ3), and (T6-MTJ4) are formed in the RS flip-flop. Since the storage content in MTJ1 and MTJ3 is 1, the storage content in MTJ2 and MTJ4 is 0. The MTJ whose storage content is 1 is in a low resistance state, and the current passing through is relatively large, so

Terminal first reaches the low level, and later Q' reaches the high level. then

When it reaches the low level, Q reaches the high level, and the output Q ⁿ⁺¹ is 1.

This state is on hold.

Qⁿ＝0，则MOS管T1、T2和T5打开，T3、T4和T6关闭。此时在RS触发器中形成(T1-MTJ1)、(T2-MTJ2)、(T5-MTJ4)3条通路。由于MTJ2和MTJ4内存储内容为1，MTJ1和MTJ3内存储内容为0。存储内容为1的MTJ处于低阻态，通过的电流较大，所以

和Q'都有可能先达到低电平，随后Q端和

到达高电平。4. If

If Q ⁿ =0, then MOS transistors T1, T2 and T5 are turned on, and T3, T4 and T6 are turned off. At this time, three paths (T1-MTJ1), (T2-MTJ2), and (T5-MTJ4) are formed in the RS flip-flop. Since the storage content in MTJ2 and MTJ4 is 1, the storage content in MTJ1 and MTJ3 is 0. The MTJ whose storage content is 1 is in a low resistance state, and the current passing through is relatively large, so

and Q' are likely to go low first, followed by the Q terminal and

reaches a high level.

Qⁿ＝1，则MOS管T3、T4和T6打开，T1、T2和T5关闭。此时在RS触发器中形成(T3-MTJ2)、(T4-MTJ3)、(T6-MTJ4)3条通路。由于MTJ2和MTJ4内存储内容为1，MTJ1和MTJ3内存储内容为0。存储内容为1的MTJ处于低阻态，通过的电流较大，所以

和Q'都有可能先达到低电平，随后Q端和

到达高电平。if

Q ⁿ =1, then MOS transistors T3, T4 and T6 are turned on, and T1, T2 and T5 are turned off. At this time, three paths (T3-MTJ2), (T4-MTJ3), and (T6-MTJ4) are formed in the RS flip-flop. Since the storage content in MTJ2 and MTJ4 is 1, the storage content in MTJ1 and MTJ3 is 0. The MTJ whose storage content is 1 is in a low resistance state, and the current passing through is relatively large, so

and Q' are likely to go low first, followed by the Q terminal and

reaches a high level.

This state is indeterminate.

In this embodiment, under the control of the working clock, combined with the writing circuit, the work is divided into two stages:

When clk is at a high level, the control writing circuit is in a blocking state, and the existence of the writing circuit at this time does not affect the normal function of the flip-flop. When clk is low level, the control circuit is turned on, and the MTJ can be written into. When the write clock clk1 is valid, MP11 and MN12 are turned on, forming a loop marked by a thick line, and providing a write current in the direction shown in FIG. 4 for the MTJ write operation. When the write clock clk2 is valid, MP12 and MN11 are turned on, forming a write current loop 2, which provides reverse current for MTJ "writing"; it is necessary to design the timing sequence of the write clock clk1 and clk2 to ensure that the clk is low. Write, and it is necessary to ensure that clk1 and clk2 cannot be valid at the same time, that is, two write channels cannot be opened at the same time. The magnitude of the writing current is realized by adjusting the width-to-length ratios of MP11, MP12, MN11, and MN12.

Figure 5 shows the function and read and write sequence diagram of the RS flip-flop in this design.

Claims (5)

1. A kind of RS flip-flop based on MTJ device, it is characterized in that, comprises: two-way precharge sensitive amplifier, CMOS dual-rail circuit, two pairs of MTJ devices and two-way write-in circuit, two-way write-in circuit is used for writing to two roads respectively Write information to the MTJ device, and the dual precharge sensitive amplifier reads the information stored in the two pairs of MTJ devices through the CMOS dual-rail circuit; The writing circuit includes: NMOS tubes MN11~MN16, PMOS tubes MP11 and PMOS tubes MP12, The drain of the NMOS transistor MN13 is the first clock signal terminal of the writing circuit, the source of the NMOS transistor MN14 is the second clock signal terminal of the writing circuit, the drain of the NMOS transistor MN15 is the third clock signal terminal of the writing circuit, and the NMOS transistor MN15 is the third clock signal terminal of the writing circuit. The source of MN16 is the fourth clock signal terminal of the writing circuit, the clock signals of the first clock signal terminal and the fourth clock signal terminal are complementary clock signals, and the clock signals of the second clock signal terminal and the third clock signal terminal are complementary clock signals Signal, The gate of the NMOS transistor MN13 and the gate of the NMOS transistor MN16 are jointly used as the first writing control signal input end of the writing circuit, and the gate of the NMOS transistor MN14 and the gate of the NMOS transistor MN15 are jointly used as the second writing terminal of the writing circuit. Into the control signal input terminal, The source of the NMOS transistor MN13 is connected to the gate of the PMOS transistor MP11, the drain of the NMOS transistor MN14 is connected to the gate of the NMOS transistor MN11, the source of the NMOS transistor MN15 is connected to the gate of the PMOS transistor MP12, and the drain of the NMOS transistor MN16 is connected to the NMOS the gate of tube MN12, The drain of the PMOS transistor MP11 and the drain of the NMOS transistor MN11 are jointly used as the writing current A connection end of the writing circuit, and the drain of the PMOS transistor MP12 and the drain of the NMOS transistor MN12 are jointly used as the writing current B connection of the writing circuit. end, The source of the PMOS transistor MP11 and the source of the PMOS transistor MP12 are connected to the positive pole of the power supply, and the sources of the NMOS transistor MN11 and the source of the NMOS transistor MN12 are connected to the negative pole of the power supply. 2. A kind of RS flip-flop based on MTJ device according to claim 1, is characterized in that, two pairs of MTJ devices are respectively MTJ devices MTJ1～MTJ4, Each MTJ device includes two ferromagnetic layers and an oxide barrier layer between the two ferromagnetic layers, MTJ devices MTJ1 and MTJ1 correspond to one writing circuit, and MTJ devices MTJ3 and MTJ4 correspond to another writing circuit. A ferromagnetic layer of the MTJ device MTJ1 is connected to a write current A connection end of a write circuit, and a ferromagnetic layer of the MTJ device MTJ2 is connected to a write current B connection end of a write circuit, A ferromagnetic layer of the MTJ device MTJ3 is connected to the write current A connection end of another write circuit, and a ferromagnetic layer of the MTJ device MTJ4 is connected to the write current B connection end of the other write circuit. 3 . The RS flip-flop based on MTJ device according to claim 2 , wherein the material of the ferromagnetic layer is CoFeB, and the material of the oxide barrier layer is MgO. 4. A kind of RS flip-flop based on MTJ device according to claim 2, it is characterized in that, one precharge sensitive amplifier comprises: PMOS transistor MP1, PMOS transistor MP2, PMOS transistor TP1, PMOS transistor TP2, NMOS transistor TN1, NMOS tube TN2, capacitor C1 and capacitor C2, Another pre-charge sensitive amplifier includes: PMOS transistor MP3, PMOS transistor MP4, PMOS transistor TP3, PMOS transistor TP4, NMOS transistor TN3, NMOS transistor TN4, capacitor C3 and capacitor C4, The gates of the PMOS transistors MP1-MP4 are all input terminals of the clock signal clk, the sources of the PMOS transistors MP1-MP4 and the sources of the PMOS transistors TP1-TP4 are connected to the positive pole of the power supply, The drain of the PMOS transistor MP1, the drain of the PMOS transistor TP1, the drain of the NMOS transistor TN1, the gate of the PMOS transistor TP2, the gate of the NMOS transistor TN2 are connected to one end of the capacitor C1, and together serve as the Q output of the RS flip-flop end, The drain of the PMOS transistor MP2, the drain of the PMOS transistor TP2, the drain of the NMOS transistor TN2, the gate of the PMOS transistor TP1, the gate of the NMOS transistor TN1 are connected to one end of the capacitor C2, and together serve as the RS flip-flop

output terminal, The drain of the PMOS transistor MP4, the drain of the PMOS transistor TP4, the drain of the NMOS transistor TN4, the gate of the PMOS transistor TP3, the gate of the NMOS transistor TN3 are connected to one end of the capacitor C4, and together serve as the RS flip-flop

output terminal, The drain of the PMOS transistor MP3, the drain of the PMOS transistor TP3, the drain of the NMOS transistor TN3, the gate of the PMOS transistor TP4, the gate of the NMOS transistor TN4 are connected to one end of the capacitor C3, and together serve as the Q' of the RS flip-flop output terminal, The other ends of the capacitors C1 - C4 are all connected to the power ground. 5. The RS flip-flop based on MTJ device according to claim 4, characterized in that, the CMOS dual-rail circuit comprises: NMOS transistors T1-T6 and NMOS transistors MN1-MN6, The gates of the NMOS transistors MN1-MN6 are all input terminals of the clock signal clk of the CMOS dual-rail circuit, The drain of the NMOS transistor MN1 is connected to the Q output terminal, and the drain of the NMOS transistor MN2 is connected to

The output terminal, the drain of the NMOS transistor MN3 is connected to the Q' output terminal, and the drain of the NMOS transistor MN4 is connected to

output terminal, The source of NMOS transistor MN4 is connected to the gates of NMOS transistors T1 and T2 at the same time, the source of NMOS transistor MN3 is connected to the gate of NMOS transistor T3, the source of NMOS transistor MN2 is connected to the gate of NMOS transistor T5, and the source of NMOS transistor MN1 The pole is connected to the gates of NMOS transistors T4 and T6, The drain of NMOS transistor T1 is connected to the source of NMOS transistor TN1, the drain of NMOS transistor T4 is connected to the source of NMOS transistor TN4, the source of NMOS transistor TN2 is connected to the drains of NMOS transistors T2 and T3, and the source of NMOS transistor TN3 The pole is connected to the drains of NMOS transistors T5 and T6 at the same time, The source of the NMOS transistor T1 is connected to a ferromagnetic layer of the MTJ device MTJ1, the sources of the NMOS transistors T2 and T3 are simultaneously connected to a ferromagnetic layer of the MTJ device MTJ2, and the source of the NMOS transistor T4 is connected to a ferromagnetic layer of the MTJ device MTJ3 , the sources of the NMOS transistors T5 and T6 are simultaneously connected to a ferromagnetic layer of the MTJ device MTJ4, The drain of the NMOS transistor MN5 is connected to another ferromagnetic layer of the MTJ devices MTJ1 and MTJ2 at the same time, and the drain of the NMOS transistor MN6 is connected to the other ferromagnetic layer of the MTJ devices MTJ3 and MTJ4 at the same time, The sources of the NMOS transistors MN5 and MN6 are simultaneously connected to the negative pole of the power supply.

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