CN113451347B - Display panel, display device and display panel manufacturing method - Google Patents
Display panel, display device and display panel manufacturing method Download PDFInfo
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- CN113451347B CN113451347B CN202010565662.9A CN202010565662A CN113451347B CN 113451347 B CN113451347 B CN 113451347B CN 202010565662 A CN202010565662 A CN 202010565662A CN 113451347 B CN113451347 B CN 113451347B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 78
- 239000012945 sealing adhesive Substances 0.000 claims description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000000565 sealant Substances 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 239000002041 carbon nanotube Substances 0.000 claims description 4
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910021389 graphene Inorganic materials 0.000 claims description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000002042 Silver nanowire Substances 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims 1
- 238000012423 maintenance Methods 0.000 abstract 1
- 230000008439 repair process Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910001111 Fine metal Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
- H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
- H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/036—Manufacture or treatment of packages
- H10H20/0364—Manufacture or treatment of packages of interconnections
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Abstract
本发明涉及微型发光二极管技术领域，具体涉及一种显示面板、显示装置及显示面板制作方法，该显示面板包括多个基板，每个基板上设置有多条信号线，该信号线在基板一边缘侧露出作为引脚；多个微型发光二极管，多个微型发光二极管固设于每个基板上，且与信号线电连接；以及透明走线层，透明走线层共同设置于多个基板的微型发光二极管上方，且通过至少一个导电材料与引脚电连接。本发明在顶层设计一层透明走线层，将微型发光二极管的信号线通过布置在透明走线层的透明导线进行连接，节省了扇出空间，缩小了拼接缝隙；使显示面板能够适用于大尺寸拼接，并且能够有效降低基板的检修次数，还能进一步减少多次修复对微型发光二极管芯片的影响。
The present invention relates to the technical field of miniature light-emitting diodes, in particular to a display panel, a display device and a method for manufacturing the display panel. The display panel includes a plurality of substrates, and each substrate is provided with a plurality of signal lines, and the signal lines are located at an edge of the substrate. side exposed as pins; a plurality of miniature light-emitting diodes, which are fixed on each substrate and are electrically connected with the signal lines; and a transparent wiring layer, which is jointly arranged on the microscopic above the light emitting diode and electrically connected to the pin through at least one conductive material. In the present invention, a transparent wiring layer is designed on the top layer, and the signal lines of the miniature light-emitting diodes are connected through the transparent wires arranged on the transparent wiring layer, which saves the fan-out space and reduces the splicing gap; Size splicing, and can effectively reduce the number of maintenance of the substrate, and can further reduce the impact of multiple repairs on the miniature light-emitting diode chip.
Description
Technical Field
The invention relates to the technical field of micro light-emitting diodes, in particular to a display panel, a display device and a display panel manufacturing method.
Background
Micro Light Emitting Diode (Micro LED) technology, that is, Light Emitting Diode (LED) Micro and matrixing technology, refers to a high-density Micro-sized LED array integrated on one chip; with the development of science and technology, the display device of the Micro LED has the advantages of good stability, service life and operation temperature, and simultaneously has the advantages of low power consumption, high color saturation, high reaction speed, high contrast and the like of the LED, so that the application of the display device is more and more extensive, and the manufacturing process is mature day by day.
However, in a large-size Micro LED display panel application scenario, a conventional Thin Film Transistor (TFT) driving panel has a fan-out (Fanout) area, which includes a data line, a clock signal trace, a Bonding Pin (Bonding Pin), and the like, and has a large area, and when two glass substrates are spliced, a large splicing gap may occur in an upper fan-out area and a lower fan-out area. How to realize the transparency of the fan-out and the splicing area becomes the key for solving the large-size transparent splicing technology at present.
Therefore, a wiring design and a process capable of overcoming the fan-out area and the bonding pin are urgently needed.
Disclosure of Invention
In view of the foregoing defects in the prior art, an object of the present application is to provide a display panel, a display device and a method for manufacturing the display panel, which omit a fan-out region and a splicing region, thereby reducing the size of a gap generated during splicing and improving the display effect of the display panel.
The purpose of the invention is realized by the following technical scheme:
the present invention provides a display panel including:
the circuit board comprises a plurality of substrates, a plurality of signal wires and a plurality of signal wires, wherein each substrate is provided with the signal wires, and the signal wires are exposed at one edge side of the substrate and used as pins;
the micro light-emitting diodes are fixedly arranged on each substrate and are electrically connected with the signal wires; and
and the transparent wiring layers are jointly arranged above the micro light-emitting diodes of the plurality of substrates and are electrically connected with the pins through at least one conductive material.
According to the display panel, based on the TFT glass substrate modular splicing technology, a transparent wiring layer is designed on the top layer, and signal wires of the micro light-emitting diodes are connected through transparent wires arranged on the transparent wiring layer, so that the fan-out space is saved, and the splicing gap is reduced; the display panel can be suitable for large-size splicing, the overhauling times of the substrate can be effectively reduced, and the influence of repeated repairing on the Micro LED chip can be further reduced.
Optionally, the transparent routing layer includes at least one transparent wire, and the transparent wire is one or more of a silver nanowire, a graphene wire, an indium tin oxide wire, or a carbon nanotube.
According to the invention, the transparent wiring layer is arranged, and the transparent wires are used for wiring in the transparent wiring layer, so that the wiring space of the display panel is increased, the light transmittance of the display light-transmitting area is improved, and the display effect of the display panel is improved.
Optionally, the signal line is routed in a high pin manner.
Each signal line inside the panel is directly wired on or directly under the panel, and the wiring layer is exposed from the top and the bottom to be used as a pin, so that the signal line is conveniently connected with the transparent wiring layer. Optionally, the light emitting diode package structure further comprises a sealing adhesive layer and a flat layer, wherein the sealing adhesive layer is arranged on the substrate and encapsulates the micro light emitting diode, and the flat layer is arranged on the sealing adhesive layer.
Optionally, the package structure further includes a laminated structure, and the laminated structure is correspondingly disposed in the encapsulant layer above the pins.
Optionally, a via is disposed on the stacked structure, the via penetrates to the pin, and a conductive material is filled in the via to electrically connect the transparent conductive wire with the pin.
Based on the same concept, the present invention provides a display device including a plurality of display panels as any one of the above.
According to the display panel, based on the TFT glass substrate modular splicing technology, a transparent wiring layer is designed on the top layer, and signal wires of the micro light-emitting diodes are connected through transparent wires arranged on the transparent wiring layer, so that the fan-out space is saved, and the splicing gap is reduced; the display panel can be suitable for large-size splicing, the overhauling times of the substrate can be effectively reduced, and the influence of repeated repairing on the Micro LED chip can be further reduced.
Based on the same conception, the invention provides a display panel manufacturing method, which comprises the following steps:
exposing a signal line in a substrate on one edge side to be used as a pin;
forming a stacked structure over a lead of the substrate;
a plurality of micro light-emitting diodes are fixedly arranged on each substrate and are electrically connected with the signal wires;
etching the laminated structure to form a guide hole;
and manufacturing a transparent wiring layer above the micro light-emitting diode, wherein the transparent wiring layer is electrically connected with the pins of the substrate through the conductive material filled in the guide holes.
According to the display panel, based on the TFT glass substrate modular splicing technology, a transparent wiring layer is designed on the top layer, and signal wires of the micro light-emitting diodes are connected through transparent wires arranged on the transparent wiring layer, so that the fan-out space is saved, and the splicing gap is reduced; the display panel can be suitable for large-size splicing, the overhauling times of the substrate can be effectively reduced, and the influence of repeated repairing on the Micro LED chip can be further reduced.
Optionally, the step of fixedly mounting the plurality of micro light emitting diodes on each of the substrates and electrically connecting the micro light emitting diodes to the signal lines further includes:
and forming a sealing adhesive layer on the substrate, wherein the micro light-emitting diode is encapsulated in the sealing adhesive layer, and a flat layer is formed on the sealing adhesive layer.
Optionally, the stacked structure is formed by etching by a chemical vapor deposition method.
Drawings
For the purpose of easy explanation, the present invention will be described in detail with reference to the following preferred embodiments and the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of a display panel according to the present invention;
FIG. 2 is a schematic view of a manufacturing process of a display panel according to the present invention;
FIG. 3 is a schematic diagram of a first manufacturing process of a display panel according to the present invention;
FIG. 4 is a schematic diagram of a second manufacturing process of the display panel according to the present invention;
FIG. 5 is a schematic diagram of a third process of fabricating a display panel according to the present invention;
FIG. 6 is a diagram illustrating a fourth process of fabricating a display panel according to the present invention.
Description of reference numerals:
10-a substrate; 100-pads; 101-a pin; 102-a laminated structure; 103-a light emitting unit; 104-a sealant layer; 105-a planarization layer; 106-transparent routing layer; 107-guide holes.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
An embodiment of a display panel according to the present invention is described below, as shown in fig. 1, where fig. 1 includes two display panels, and represents a control state when the two display panels are spliced, each display panel includes:
a compact array of substrates 10; in the embodiment, two substrates 10 are taken as an example, but the invention does not mean that only two substrates are implemented, and the number of the substrates 10 to be spliced is not limited; a plurality of signal lines are disposed in each of the substrates 10, and the signal lines include, but are not limited to, data lines, scan lines, power lines VSS/VDD, and the like. The signal lines in the substrate 10 are exposed as pins (pin pins) 101 on one edge side of the substrate 10; the leads 101 are located on the upper surface or the lower surface of the substrate 10.
A plurality of micro light emitting diodes 103, which are fixedly arranged on the substrate 10 and electrically connected with the signal lines; as an alternative embodiment, the micro light emitting diodes 103 arrayed on the substrate 10 are fixedly welded on the substrate 10 through a bonding Pad (Pad) 100;
and the transparent wiring layers 106, wherein the transparent wiring layers 106 are commonly arranged above the micro light emitting diodes 103 of the plurality of substrates 10, and are electrically connected with the pins 101 through at least one conductive material.
As an alternative embodiment, the transparent conductive wire includes but is not limited to fine metal wire, nano silver wire, graphene, indium tin oxide or carbon nanotube. As an alternative embodiment, the signal lines in the substrate are routed in the manner of High pins (High Pin). That is, each signal line inside the panel is routed on the panel in a straight-up or straight-down manner, and the routing layer is exposed from the uppermost side and the lowermost side to serve as a pin 101, which is conveniently connected with the transparent routing layer.
Further, the adhesive layer 104 and the flat layer 105 are sequentially included; specifically, the adhesive layer 104 is disposed on the substrate 10, the adhesive layer 104 encapsulates the micro light emitting diode 10, and the planarization layer 105 is disposed on the adhesive layer 104. The packaging structure further comprises a laminated structure 102, wherein the laminated structure 102 is formed by etching through a chemical vapor deposition method and is arranged in the sealant layer 104 in a penetrating manner, and the laminated structure 102 is correspondingly arranged at the pin 101 of the substrate 10.
As an alternative embodiment, a via 107 is made from the transparent wiring layer 106 to penetrate the laminated structure 102 from the transparent wiring layer 106 to the upper side of the lead 101, and then the via 107 may be filled with a conductive material to connect the transparent conductive wire with the lead 101. As an alternative embodiment, a transparent routing layer 106 is disposed above the flat layer 105, and the transparent routing layer 106 includes a plurality of transparent wires; according to the invention, the transparent wiring layer is arranged, and the transparent wires are used for wiring in the transparent wiring layer, so that the wiring space of the display panel is increased, the light transmittance of the display light-transmitting area is improved, and the display effect of the display panel is improved.
Bonding pins (Bonding pins) are left on the transparent wiring layer 106, and the IC is bonded to the Bonding pins to complete the fabrication of the display panel.
The invention provides a display device, which comprises a plurality of display panels which are spliced in a close array manner; in this embodiment, two display panels are spliced as an example, but the present invention does not mean that only two display panels are implemented, and the number of the spliced display panels is not limited in the present invention.
A display device includes a first display panel and a second display panel, the first display panel being the same as the second display panel; the first display panel and the second display panel are seamlessly spliced to form the display device; as an optional seamless splicing mode, the first display panel and the second display panel are arranged in an array manner, the frames of the first display panel and the second display panel are in close contact, and a splicing area is arranged between the first display panel and the second display panel; the display device also comprises a third display panel, and the third display panel completely covers the splicing area so that the splicing display device has a seamless splicing display effect.
Wherein the first display panel, as shown in fig. 1, includes:
a substrate 10; in the embodiment, two substrates 10 are taken as an example, but the invention does not mean that only two substrates are implemented, and the number of the substrates 10 to be spliced is not limited;
the substrate 10 and the micro light-emitting diodes 103 arrayed on the substrate 10, wherein the micro light-emitting diodes 103 are welded on the substrate 10 through a bonding Pad (Pad) 100; the substrate 10 has a plurality of signal lines therein, including but not limited to data lines, scan lines, power lines VSS/VDD, and the like. The signal lines in the substrate 10 are exposed as pins (pin pins) 101 on one edge side of the substrate; the leads 101 are located on the upper surface or the lower surface of the substrate 10. As an alternative embodiment, the signal lines in the substrate 10 are routed in a High Pin (High Pin) manner. That is, each signal line inside the panel is routed on the panel in a straight-up or straight-down manner, and the routing layer is exposed from the uppermost side and the lowermost side to serve as a pin 101, which is conveniently connected with the transparent routing layer.
Further, a sealant layer 104 and a planarization layer 105 are sequentially included on the substrate 10. The packaging structure further comprises a laminated structure 102, wherein the laminated structure 102 is penetratingly arranged in the sealant layer 104, and the laminated structure 102 is correspondingly arranged at the pins 101 of the substrate.
A transparent routing layer 106 is also arranged above the flat layer 105, and the transparent routing layer 106 comprises a plurality of transparent conducting wires; a via 107 is formed from the transparent wiring layer 106 to penetrate the laminated structure 102 from the transparent wiring layer 106 to the top of the lead 101, and then the via 107 may be filled with a conductive material to connect a transparent conductive wire with the lead 101.
Bonding pins (Bonding pins) are left on the transparent wiring layer 106, and the IC is bonded to the Bonding pins to complete the fabrication of the display panel.
Based on the same inventive concept, as shown in fig. 2, the present application further provides a display panel manufacturing method, which specifically includes the following steps:
as shown in fig. 3, the signal line in the substrate 10 is exposed on one edge side as a lead 101; the leads 101 are located on the upper surface or the lower surface of the substrate 10. The substrate 10 has a plurality of signal lines therein, including but not limited to data lines, scan lines, power lines VSS/VDD, and the like. As an alternative embodiment, the signal lines in the substrate 10 are routed in a High Pin (High Pin) manner. That is, each signal line inside the panel is routed on the panel in a straight-up or straight-down manner, and the routing layer is exposed from the uppermost side and the lowermost side to serve as a pin 101, which facilitates the contact of the later-described via.
As shown in fig. 4 and 5, a plurality of micro light emitting diodes 103 are fixedly disposed on each of the substrates 10 and electrically connected to the signal lines; specifically, the micro light emitting diode 103 is soldered on the substrate 10 through a bonding Pad (Pad) 100; as an optional implementation, further comprising forming an adhesive sealing layer 104 on the substrate 10, the adhesive sealing layer encapsulating the micro light emitting diode, and forming a flat layer 105 on the adhesive sealing layer; as shown in fig. 5, a laminated structure 102 is etched above the lead 101; specifically, the laminated structure 102 is disposed in the sealant layer 104 in a penetrating manner, and the laminated structure 102 is correspondingly disposed above the leads 101 of the substrate. As an alternative embodiment, the stacked structure 102 is formed by etching through a chemical vapor deposition process.
As shown in fig. 6, a transparent wiring layer 106 is formed on the micro light emitting diodes 103 of the plurality of substrates 10; the transparent wiring layer 106 comprises a plurality of transparent conducting wires; the transparent conducting wire comprises but is not limited to a fine metal wire, a nano silver wire, graphene, indium tin oxide or a carbon nanotube;
a via 107 penetrating to the lead 101 through the stacked structure 102 is formed, and then the via 107 may be filled with a conductive material to connect the transparent conductive line to the lead through the via;
the IC chip is bonded on the transparent wiring layer 106.
Based on the same inventive concept, the application also provides a manufacturing method of the display device, wherein the same first display panel and the same second display panel are seamlessly spliced to form the display device; as an alternative seamless splicing method:
the first display panel and the second display panel are arranged in an array mode, and the frames of the first display panel and the second display panel are in close contact;
a splicing area is included between the first display panel and the second display panel;
the display device also comprises a third display panel, and the third display panel completely covers the splicing area so that the splicing display device has a seamless splicing display effect.
According to the display panel, based on the TFT glass substrate modular splicing technology, the transparent wiring layer is designed on the top layer, and the signal wires of the micro light-emitting diodes are connected through the transparent wires arranged on the transparent wiring layer, so that the fan-out space is saved, and the splicing gap is reduced; the display panel can be suitable for large-size splicing, the overhauling times of the substrate can be effectively reduced, and the influence of repeated repairing on the Micro LED chip can be further reduced.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A display panel, comprising:
the circuit board comprises a substrate, a plurality of signal wires and a plurality of signal wires, wherein the signal wires are exposed out of one edge side of the substrate and used as pins;
the micro light-emitting diodes are fixedly arranged on the substrate and are electrically connected with the signal wires; and
and the transparent wiring layer is arranged above the micro light-emitting diode of the substrate and is electrically connected with the pins through at least one conductive material.
2. The display panel of claim 1, wherein the transparent wiring layer comprises at least one transparent conductive wire, and the transparent conductive wire is one or more of a silver nanowire, a graphene wire, an indium tin oxide wire, or a carbon nanotube.
3. The display panel of claim 1, wherein the signal lines are routed in a high pin manner.
4. The display panel of claim 2, further comprising an adhesive layer disposed on the substrate, the adhesive layer encapsulating the micro light emitting diode, and a planarization layer disposed over the adhesive layer.
5. The display panel of claim 4, further comprising a lamination structure correspondingly disposed in the sealant layer over the leads.
6. The display panel according to claim 5, wherein a via is formed on the stacked structure, the via penetrating to the lead, and a conductive material is filled in the via to electrically connect the transparent conductive line and the lead.
7. A display device comprising a plurality of display panels according to any one of claims 1 to 6.
8. A manufacturing method of a display panel is characterized by comprising the following steps:
exposing a signal line in a substrate on one edge side to be used as a pin;
forming a stacked structure over a lead of the substrate;
a plurality of micro light-emitting diodes are fixedly arranged on each substrate and are electrically connected with the signal wires;
etching the laminated structure to form a guide hole;
and manufacturing a transparent wiring layer above the micro light-emitting diode, wherein the transparent wiring layer is electrically connected with the pins of the substrate through the conductive material filled in the guide holes.
9. The method for manufacturing a display panel according to claim 8, wherein the step of fixing the micro light emitting diodes on each of the substrates and electrically connecting the micro light emitting diodes with the signal lines further comprises:
and forming a sealing adhesive layer on the substrate, wherein the micro light-emitting diode is encapsulated in the sealing adhesive layer, and a flat layer is formed on the sealing adhesive layer.
10. The display panel manufacturing method according to claim 9, wherein the laminated structure is formed by etching by a chemical vapor deposition method.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010565662.9A CN113451347B (en) | 2020-06-19 | 2020-06-19 | Display panel, display device and display panel manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010565662.9A CN113451347B (en) | 2020-06-19 | 2020-06-19 | Display panel, display device and display panel manufacturing method |
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| CN113451347B true CN113451347B (en) | 2022-04-01 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015196674A1 (en) * | 2014-06-25 | 2015-12-30 | 京东方科技集团股份有限公司 | Oled display device, contactless ic card and flexible display apparatus |
| CN205900547U (en) * | 2016-08-19 | 2017-01-18 | 京东方科技集团股份有限公司 | Illumination panel and lighting device |
| CN109888085A (en) * | 2019-03-11 | 2019-06-14 | 京东方科技集团股份有限公司 | Display panel and preparation method thereof |
-
2020
- 2020-06-19 CN CN202010565662.9A patent/CN113451347B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015196674A1 (en) * | 2014-06-25 | 2015-12-30 | 京东方科技集团股份有限公司 | Oled display device, contactless ic card and flexible display apparatus |
| CN205900547U (en) * | 2016-08-19 | 2017-01-18 | 京东方科技集团股份有限公司 | Illumination panel and lighting device |
| CN109888085A (en) * | 2019-03-11 | 2019-06-14 | 京东方科技集团股份有限公司 | Display panel and preparation method thereof |
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| CN113451347A (en) | 2021-09-28 |
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