CN113448379A

CN113448379A - Method, apparatus and computer-readable storage medium for frequency modulation of a chip

Info

Publication number: CN113448379A
Application number: CN202010225223.3A
Authority: CN
Inventors: 不公告发明人
Original assignee: Anhui Cambricon Information Technology Co Ltd
Current assignee: Anhui Cambricon Information Technology Co Ltd
Priority date: 2020-03-26
Filing date: 2020-03-26
Publication date: 2021-09-28
Anticipated expiration: 2040-03-26
Also published as: CN113448379B

Abstract

The present disclosure discloses a method, apparatus, and computer-readable storage medium for frequency tuning a chip. Wherein the frequency modulation device may be comprised in a combined processing means, which may further comprise a universal interconnect interface and other processing means. The equipment interacts with other processing devices to jointly complete the calculation operation designated by the user. The combined processing means may further comprise storage means connected to said device and to the other processing means, respectively, for storing data of said device and the other processing means. The scheme disclosed by the invention can be used for dynamically adjusting the working frequency of the chip by measuring the power consumption of the system in real time, so that the operational performance of the operation chip and the combined processing device is improved. The scheme has the advantages of convenience, flexibility, high frequency adjusting speed and the like.

Description

Method, apparatus and computer-readable storage medium for frequency modulation of a chip

Technical Field

The present disclosure relates generally to the field of chip control. And more particularly, to a method, apparatus, and computer-readable storage medium for frequency modulating a chip.

Background

In recent years, with the increase in data volume and the increase in computing power, a large number of chips are generally integrated in a computing device and a testing device for data operation. Because the difference between the working performance and the manufacturing process of various chips is large, the power consumption and the operational performance of the whole system can be directly influenced, and particularly, the working frequency of the operational chip can determine the power consumption and the working performance of the whole combined processing device. Therefore, how to dynamically adjust the actual required frequency of the chip has become an urgent problem to be solved.

Disclosure of Invention

In order to solve at least one or more of the problems described in the above background section, so as to improve the working performance of the whole combined processing device by adjusting the working frequency of the chips in one or more combined processing devices, the present disclosure proposes the following technical solutions and several embodiments thereof.

In one aspect, the present disclosure discloses a method for frequency tuning a chip, the method comprising obtaining real-time power consumption samples of at least one chip in operation; determining an error value between the real-time power consumption sampling value and the power consumption target value according to the real-time power consumption sampling value and the power consumption target value; and determining an adjustment amount for adjusting the clock frequency of the at least one chip with a PID control module based on the error value.

In another aspect, the present disclosure also discloses a method for frequency tuning a chip, the method comprising obtaining real-time power consumption samples of at least one chip in operation; determining whether the real-time power consumption sampling value is greater than or equal to a fast down-conversion threshold; when the real-time power consumption sampling value is larger than or equal to the quick frequency reduction threshold value, executing quick frequency reduction operation on the at least one chip; when the real-time power consumption sampling value is smaller than the rapid frequency reduction threshold value, determining an error value between the real-time power consumption sampling value and a power consumption target value according to the real-time power consumption sampling value and the power consumption target value; and determining an adjustment amount for adjusting the clock frequency of the at least one chip with a PID control module based on the error value.

In yet another aspect, the present disclosure further discloses an apparatus for frequency modulating a chip, the apparatus comprising: the acquisition module is configured to acquire a real-time power consumption sampling value when at least one chip operates; the PID control module is configured to determine an error value between the real-time power consumption sampling value and the power consumption target value according to the real-time power consumption sampling value and the power consumption target value; and determining an adjustment amount for adjusting the clock frequency of the at least one chip based on the error value.

In one aspect, the present disclosure discloses an apparatus for frequency modulating a chip, the apparatus comprising: the acquisition module is configured to acquire a real-time power consumption sampling value when at least one chip operates; a determination module configured to determine whether the real-time power consumption sample value is greater than or equal to a fast down-conversion threshold; a fast down-conversion module configured to perform a fast down-conversion operation on the at least one chip when the real-time power consumption sample value is greater than or equal to the fast down-conversion threshold; and a PID control module configured to perform, when the real-time power consumption sample value is less than the fast down threshold: determining an error value between the real-time power consumption sampling value and the power consumption target value according to the real-time power consumption sampling value and the power consumption target value; and determining an adjustment amount for adjusting a clock frequency of the at least one chip based on the error value.

In another aspect, the present disclosure also discloses an apparatus for frequency modulating a chip, the apparatus comprising: at least one processor; at least one memory for storing program instructions that, when executed by the at least one processor, cause the apparatus to perform the aforementioned method of frequency tuning a chip.

In yet another aspect, the present disclosure discloses a card for frequency modulating a chip, the card comprising any of the foregoing apparatus for frequency modulating a chip.

In one aspect, the present disclosure discloses an integrated circuit chip including a core for frequency tuning the chip, the core being configurable to perform the aforementioned method of frequency tuning the chip when the integrated circuit chip is in operation.

According to the method, apparatus and computer-readable storage medium of the present disclosure, the related chips can be frequency-modulated using an improved PID control technique. In some application scenarios, the scheme of the present disclosure for performing fm control on an associated chip through an external MCU ("Microcontroller Unit micro control Unit") may be directly applied to a chip with a modified frequency interface, thereby implementing dynamic fm. Meanwhile, in the frequency control process, local data can be directly managed and applied after being collected, so that the frequency modulation speed is higher. In addition, the technical scheme of the disclosure can also be flexibly adjusted, such as adjusting a proportionality coefficient, adjusting a timing emptying time, removing an integral term and the like, so as to adapt to different application requirements.

Drawings

The above-described features of the present disclosure may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The drawings in the following description are merely exemplary embodiments of the disclosure and other drawings may be derived by those skilled in the art without inventive effort, wherein:

FIG. 1 is a block diagram illustrating an operational flow of an example system for frequency tuning a chip in accordance with an embodiment of the present disclosure;

FIG. 2 is a general flow diagram illustrating a method for frequency tuning a chip according to an embodiment of the disclosure;

FIG. 3 is a detailed flow chart illustrating a method for frequency tuning a chip according to an embodiment of the present disclosure;

FIG. 4 is a flow chart illustrating a frequency modulation method of fast downconversion in accordance with an embodiment of the present disclosure;

FIG. 5 is an overall flow diagram illustrating a multi-level dynamic frequency modulation method according to an embodiment of the present disclosure;

FIG. 6 is a flow diagram illustrating a two-level dynamic frequency modulation method according to an embodiment of the present disclosure;

FIG. 7 is a flow diagram illustrating a three level dynamic frequency tuning method in accordance with an embodiment of the present disclosure;

FIG. 8 is a flow diagram illustrating a method of multi-level dynamic frequency modulation in accordance with an embodiment of the present disclosure;

FIG. 9 is a flow diagram illustrating a frequency modulation method with multiple stages and fast downconversion in accordance with an embodiment of the present disclosure;

FIG. 10 is a schematic block diagram illustrating frequency tuning of a chip using the apparatus of an embodiment of the present disclosure;

FIG. 11 is another schematic block diagram illustrating frequency tuning of a chip using the apparatus of an embodiment of the present disclosure;

FIG. 12 is a block diagram showing the structure of a combined processing device according to an embodiment of the present disclosure; and

fig. 13 is a block diagram illustrating a card for frequency tuning a chip according to an embodiment of the present disclosure.

Detailed Description

The technical scheme of the disclosure provides a method, equipment and a computer readable storage medium for frequency modulation of a chip. The integral working performance of the system is controlled by acquiring data such as power consumption of the chip in real time and performing incremental adjustment on the working frequency of the chip by using the PID control module. In some embodiments, aspects of the present disclosure use a single or single stage PID control module to incrementally adjust the operating frequency of a single or multiple chips. In other embodiments, the disclosed solution uses multiple cascaded PID control blocks to make finer adjustments to the frequency of the chip. By using the technical scheme disclosed by the invention, the increment adjustment of the working frequency of one or more chips in the combined processing device can be realized. In the process of frequency adjustment, the influence of overshoot can be weakened while the static error effect can be eliminated. Meanwhile, the frequency modulation scheme disclosed by the invention is stable and reliable, and the average power consumption of the actual board card can be controlled within +/-1W of the target power consumption under the condition that the service can reach the set target power consumption.

It should be understood that the present disclosure sets forth numerous specific details regarding the above-described scheme for chip tuning in order to provide a thorough understanding of the various embodiments of the present disclosure. However, one of ordinary skill in the art, with the teachings of the present disclosure, may practice the embodiments described in the present disclosure without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to unnecessarily obscure the embodiments described in this disclosure. Further, this description should not be taken as limiting the scope of the embodiments of the disclosure.

Technical solutions in embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating an operational flow 100 of an example system for frequency tuning a chip in accordance with an embodiment of the present disclosure. It should be noted that the system and its operational flow are merely exemplary and not limiting. The system may perform other operations in addition to the frequency tuning operations that will not be described in detail herein in order to unnecessarily obscure aspects of the present disclosure.

As shown in fig. 1, the system operation flow of the present disclosure includes performing an initialization operation on the system at step 101. For example, in the initialization operation, corresponding parameter settings may be performed for the system according to the actual application, and initial data may also be called in to prepare for the execution of the subsequent program.

After the initialization operation described above, the frequency modulation system of the present disclosure may perform the main loop operation and the dynamic frequency modulation operation in parallel or in series, respectively, at steps 102 and 103. Here, the main loop operation may be various kinds of operations or tasks that the system needs to perform in addition to the dynamic frequency modulation operation, such as machine learning-related operations directed to the field of artificial intelligence. In dynamic frequency modulation operation, the operating frequency of the chip may be adjusted using the PID control module, as previously described.

In one application scenario, under the control of the timer as shown in the figure, the MCU including the PID control module of the present disclosure may acquire at least one real-time power consumption sampling value when the chip operates at a fixed time interval (e.g., 1 ms), and determine an adjustment amount for adjusting the clock frequency of the chip by combining the power consumption target value. Thereafter, the adjustment amount may be utilized to implement a frequency tuning action on the clock frequency of one or more chips for the relevant situation in step 104, thereby further governing the power consumption of the overall device or system. The relevant situation here may be, for example, that the operating frequency of the chip is too high or too low, or other scenarios that require dynamic frequency modulation.

The operation flow of the system for frequency modulation of a chip according to the present disclosure is briefly described above with reference to fig. 1, and the flow method for frequency modulation of a chip, and the apparatus and device thereof will be further described with reference to fig. 2 to 13.

Fig. 2 is a general flow diagram illustrating a method 200 for frequency tuning a chip in accordance with an embodiment of the disclosure. It will be appreciated that the frequency modulation methods discussed herein may be performed in conjunction with the operational flow of the system of fig. 1.

As shown in fig. 2, at step 201, the method 200 may obtain real-time power consumption sample values of at least one chip in operation. Next, at step 202, the method 200 determines an error value between the real-time power consumption sample value (e.g., the chip power consumption taken within 1 millisecond) and a power consumption target value (e.g., the power consumption expected value of the chip). In one embodiment, the error value between the real-time power consumption sampling value and the power consumption target value can be obtained by calculating a difference value between the two. Next, at step 203, the method 200 determines an adjustment amount for adjusting the clock frequency of the at least one chip using the PID control module based on the error value. In one embodiment, the adjustment amount may be a relative increment based on the previous adjustment frequency. Therefore, the clock frequency of the chip after the current operation is adjusted can be obtained by adding the adjustment amount to the current clock frequency of the chip.

In order to better understand the technical solution of the present disclosure, the PID control algorithm used in the present disclosure will be described below.

The PID control algorithm is a control algorithm combining proportion (P), integral (I) and differential (D), and the essence of the control is to operate according to the function relation of proportion, integral and differential according to the input deviation value, and the operation result is used for controlling the output. The PID control algorithm of the present disclosure improves upon existing PID control algorithms in that the output value is an adjustment amount, and can be an increment relative to a previous adjustment amount, thereby distinguishing from the case where the output value of the existing PID control algorithm is an absolute value. In one embodiment, the PID control algorithm of the present disclosure may employ the following equation (1) to obtain the adjustment amount Δ u (t):

△u(t)＝k_p*e(t)+k_i*Σe(t)+k_d*(e(t)-e(t-1)) (1)

wherein k is_pIs a proportionality coefficient, k_iIs an integral coefficient, k_dIs a differential coefficient. e (t) is an error value, Σ e (t) is an accumulated sum of error values, and e (t-1) is a previous error value. k is a radical of_pE (t) is a proportional term, k_iΣ e (t) is an integral term, k_dAnd (e) (t) -e (t-1)) is a differential term.

According to different application scenarios, the scheme of the disclosure can obtain the adjustment amount through a proportional term, and also can obtain the adjustment amount through combining the proportional term with any one of an integral term and a differential term. Furthermore, the three parts can be combined to obtain the adjustment amount, and then the frequency modulation scheme of the chip is executed. In addition, through improvement on the basis of continuous actual measurement, the PID control algorithm disclosed by the invention expands the traditional PID algorithm only suitable for a quasi-linear system into a nonlinear system, and the actual measurement effect is good.

The scheme of the present disclosure and the PID control module used are described above in connection with fig. 2. Based on the above description, one skilled in the art can appreciate that the PID control module of the present disclosure can have a proportional control unit for determining the proportional term in terms of implementation. Optionally, it may further comprise at least one of an integral control unit for determining the integral term and a derivative control unit for determining the derivative term. By determining the adjustment amount by either a proportional term or a combination of a proportional term and at least one of an integral term and a derivative term, the present disclosure provides a number of flexible ways to frequency tune the chip.

Fig. 3 is a detailed flow diagram illustrating a method 300 for frequency tuning a chip in accordance with an embodiment of the present disclosure. Those skilled in the art will appreciate from the following description that fig. 3 is a further refinement of the method for frequency tuning the chip shown in fig. 2, and that the description with respect to fig. 2 applies equally to that shown in fig. 3.

As shown in fig. 3, at step 301, the method 300 obtains real-time power consumption sample values. In one embodiment, obtaining the real-time power consumption sample value comprises periodically (e.g., 1 millisecond) obtaining a plurality of the real-time power consumption sample values. The method 300 then proceeds to step 302 where an error value between the current real-time power consumption and the target power consumption is calculated. In one embodiment, determining an error value between each of the real-time power consumption samples and the power consumption target value may be determining a difference between the real-time power consumption samples and the power consumption target value (e.g., a user-defined expected power consumption of a chip or a board), and regarding the difference as the error value.

After obtaining the error value, the method 300 proceeds to step 303, where a scaling term may be derived from the error value. In one embodiment, where the PID control module is utilized to determine the adjustment amount, the proportional term can be obtained utilizing a proportional control unit in the PID control module based on the error value. In one implementation, obtaining the scaling term may include obtaining based on the error value, a selected scaling factor (e.g., a parameter adjusted based on measurements), and a dimension (e.g., hertz/watt). In one embodiment, a first adjustment amount for adjusting the clock frequency may be determined based on the proportional term. Next, as shown in fig. 3, the method 300 may proceed directly to perform a frequency tuning operation at step 310. Specifically, the clock frequency of one or more chips may be frequency-modulated according to the obtained first adjustment amount in combination with the previous adjustment of the clock frequency.

As an alternative to the above, at step 304, the method 300 determines whether a predetermined time period (e.g., a1 second time period) has been reached, which may be implemented, for example, by a timer as shown in fig. 1. When the predetermined time period has arrived, the method 300 performs step 305 of performing a zero clearing operation on the accumulated sum to restart the accumulation operation on the error value in the next predetermined time period. In accordance with aspects of the present disclosure, the zero out operation of the accumulated sum may clear cumulative effects that may be caused by power consumption adjustments. To facilitate explanation of this cumulative effect, assume in one implementation scenario that the target power consumption value (the expected power consumption value set by the user) is 75 watts and the chip is always idling for a predetermined period of time, such that the real-time power consumption sample value taken during the predetermined period of time is always 30 watts. In this case, when the accumulation operation is performed, the accumulated sum of error values in the predetermined period of time is relatively large. If the power consumption sampling value of the chip exceeds the target power consumption value (i.e. 75 w), the accumulated sum is too large, and the error value of the power consumption is neutralized (i.e. the accumulated effect mentioned above), so that the power consumption of the system exceeds the standard for a long time, which affects the performance of the system. In view of this, the disclosed solution therefore proposes to accumulate and perform a zero clearing operation on the error values within a predetermined time period to avoid the cumulative effect.

As an alternative to

steps

304 and 305, the method 300 may determine whether the predetermined time period has been reached in another manner. Specifically, a period of time during which one of the real-time power consumption sample values is acquired may be referred to as one sample period, and thus the predetermined period of time may be set to include a certain number of sample periods. When this number of sample periods arrives, the error value obtained for the earliest sample period may be cleared from the accumulated sum and the error value obtained for the latest sample period is added to the accumulated sum. For example, taking an example that the predetermined period includes 100 sampling cycles, starting from the 1 st sampling cycle, an error value between the real-time power consumption sampling value acquired by the sampling cycle and the target power consumption value is determined, and an accumulation operation is sequentially performed with the error value of the next cycle to obtain an accumulated sum. When the 100 th sampling period arrives, the method 300 may clear the error value for the earliest sampling period (i.e., the 1 st sampling period) of the predetermined number of sampling periods in the accumulated sum to perform an accumulation operation on the error value for the latest sampling period (i.e., the 101 th sampling period) to obtain an accumulated sum. That is, the updated accumulation and accumulation calculates the error value from the 2 nd sampling period to the 101 th sampling period. It can be seen that the present disclosure presents various schemes for how to determine the cumulative sum by differently setting the predetermined time period, thereby further enhancing the application flexibility of the present disclosure.

Conversely, when the predetermined period of time has not yet been reached, the method 300 proceeds to step 306, where the current error value is added to the accumulated sum. After obtaining the updated accumulated sum, the method 300 obtains an integral term from the accumulated sum at step 307. As previously described, obtaining the integral term may include obtaining the integral term based on the accumulated sum, a selected integral coefficient, and a dimension (e.g., hertz/watt). Next, at step 308, the integral term range is limited. In one embodiment, the integral term may be limited to a selected range to eliminate the effects of static error and avoid overshoot. The range may be, for example, an empirical statistic or an adjustment determined after multiple measurements. Thereafter, the method 300 proceeds to step 309, where a frequency adjustment parameter, such as an adjustment amount as referred to in this disclosure, may be obtained based on the proportional term and the integral term after the limit range. Thereafter, the method 300 proceeds to step 310, where the method 300 performs a frequency tuning action on the clock frequency of the at least one chip according to the obtained adjustment amount.

Alternatively or optionally, after obtaining the proportional term at step 303 or obtaining the proportional term and the limited integral term at step 309, the frequency adjustment parameter may be obtained by selecting and combining with the differential term according to the actual application scenario. In this case, the method 300 performs a subtraction operation based on the error value determined this time and the error value determined the previous time to obtain a differential difference value. Then, a derivative term is obtained with a derivative control unit in the PID control module based on the derivative difference. As previously described, obtaining a derivative term may include obtaining a derivative term based on the differential difference, a selected derivative coefficient, and a dimension (e.g., hertz/watt). Finally, at step 310, the method 300 may perform a frequency tuning action on the clock frequency of the chip according to an adjustment obtained by the proportional term and at least one of the integral term and the differential term. When the differential term is used in the process of determining the adjustment amount, a certain advance adjustment effect can be achieved on the frequency modulation, and the frequency modulation reaction speed can be increased.

From the above description in connection with step 304-310, those skilled in the art can understand that the present disclosure in one embodiment obtains a plurality of the real-time power consumption sample values periodically (e.g., 1 ms), and performs the determination of the error value between each of the real-time power consumption sample values and the power consumption target value for each of the real-time power consumption sample values within a predetermined time period (e.g., 1 s), and performs the accumulation operation on each determined error value to obtain the accumulated sum. Further, an integral term is obtained using an integral control unit in the PID control module based on the accumulated sum. Then, a second adjustment amount (with respect to the aforementioned first adjustment amount) for adjusting the clock frequency of the at least one chip may be determined based on the obtained proportional term and the integral term obtained with the integral control unit.

As previously described, in addition to the second adjustment amount described above, in one or more embodiments, the present disclosure may determine a third adjustment amount for adjusting the clock frequency of the at least one chip based on the obtained proportional term and the derivative term obtained with the derivative control unit. Similarly, a fourth adjustment amount for adjusting the clock frequency of the at least one chip may also be determined based on the proportional term, the integral term, and the differential term obtained as described above. In one application scenario, each of the second, third, and fourth adjustment amounts is an increment relative to a previous adjustment of the clock frequency. For the four exemplary adjustment amounts, a person skilled in the art can perform real-time adjustment according to the monitored actual frequency modulation effect, thereby implementing real-time frequency modulation operation on the chip.

The frequency modulation operation performed on the chip by the present disclosure when the power consumption of the chip is within a reasonable range is described above in conjunction with fig. 2 and 3. The operation of performing fast down-conversion on the chip in the case where the power consumption fluctuation of the chip becomes instantaneously larger than the conventional range will be described in detail below with reference to fig. 4.

Fig. 4 is a flow chart illustrating a frequency modulation method 400 of fast downconversion according to an embodiment of the present disclosure. As shown in fig. 4, at step 401, the method 400 obtains real-time power consumption sample values of at least one chip in operation. For example, real-time power consumption samples of at least one chip may be collected periodically (e.g., 1 millisecond). Next, at step 402, it is determined whether the real-time power consumption sample value is greater than or equal to the fast down threshold. In one application scenario, the fast down threshold may be determined according to product specification requirements, and its calculation formula may be as follows:

P_th＝U*I_max (2)

wherein U represents the operating voltage, I_maxRepresenting the maximum current allowed, P_thRepresents a fast down threshold, represents a product relationship.

In another embodiment, the fast down-conversion threshold may also be adjusted within a certain range according to the measured result based on the calculation result of the aforementioned formula, and the adjustment range may be determined according to an empirical value, for example.

When the real-time power consumption sample value is greater than or equal to the fast down threshold, the method 400 proceeds to step 403, where the method 400 performs a fast down operation on at least one chip. Before performing the fast down operation, in one or more embodiments, the target frequency value of the current adjustment of the chip may be determined. In one embodiment, the target frequency value may be determined by the following equation:

F_aim＝F_now*(P_aim-P_idle)/(P_now-P_idle) (3)

wherein F_aimIs a target frequency, F_nowFor the current frequency, P_aimFor a target power consumption, P_idleFor idle power consumption, P_nowFor the current power consumption, the product relationship is represented. It should be noted that at the instant of performing fast down-conversion, the linear relationship between power consumption and frequency can be approximately considered. The scheme of the disclosure can obtain a target frequency value by means of such a linear relationship, and the target frequency value can be used as the clock frequency of the current adjustment, so as to perform a corresponding frequency modulation action on at least one chip.

Conversely, when the real-time power consumption sample value is less than the fast down threshold, the method 400 performs a normal frequency tuning operation at step 404. For example, the method 400 may determine an error value between the real-time power consumption sample value and the power consumption target value. Next, the method 400 may determine, using the PID control module, an adjustment amount for adjusting the clock frequency of the at least one chip based on the error value. Thereby, a normal frequency modulation operation can be performed on the clock frequency of one or more chips in conjunction with the previous adjustment of the clock frequency in accordance with the obtained adjustment amount. It can be understood by those skilled in the art that the normal frequency modulation operation may be the frequency modulation operation performed in conjunction with fig. 3, and therefore the operation of frequency modulating the chip described in conjunction with fig. 3 is also applicable to the normal frequency modulation operation, and therefore the same or similar contents will not be described herein again.

In the above, the present disclosure describes the frequency modulation operation of performing a single-stage PID (e.g., the second stage shown in fig. 6, which is described in detail later) on the chip in conjunction with fig. 1-4, and the multi-stage PID frequency modulation operation of the present disclosure will be further explained in conjunction with fig. 5-9.

Fig. 5 is a general flow diagram illustrating a multi-level dynamic frequency modulation method 500 according to an embodiment of the disclosure. By using the method 500 to perform multi-level serial PID dynamic frequency modulation on the chip, the frequency adjustment can be more fine, and the Power consumption is allowed to exceed the TDP ("Thermal Design Power") Power consumption in a short time to a certain extent, thereby improving the system performance.

As shown in FIG. 5, at step 501, the method 500 obtains a real-time power consumption sample value and an average power consumption value over N-1 predetermined execution cycles of at least one chip operation, where N is a positive integer greater than or equal to 2. In one embodiment, N-1 predetermined execution cycles T₁，……T_N-1And the sampling period T of the real-time power consumption sampling value_NSatisfy the relation T₁(e.g., 1 second)>T₂(e.g., 500 milliseconds) … … T_N-1(e.g., 50 milliseconds)>T_N(e.g., 1 millisecond). Next, at step 502, the method 500 determines an adjustment amount for adjusting the clock frequency of the at least one chip using N PID control modules connected in series stage by stage based on the real-time power consumption sampling value, the average power consumption value, and the average power consumption reference value. In one implementation scenario, the average power consumption reference value of the present disclosure can be flexibly set according to actual situations. For example, the setting may be performed by a "Power clipping" function of the upper computer, which allows the user to limit the average Power consumption reference value within its specified range. Further, after modifying the average power consumption reference value, the average power consumption reference value is usedThe user does not need to adjust other parameters, and all the parameters related to the previous average power consumption reference value are automatically adjusted according to the new average power consumption reference value given by the user.

While the general flow of the multi-stage dynamic frequency modulation method 500 is briefly described above with reference to fig. 5, in order to further understand the multi-stage frequency modulation scheme of the present disclosure, the multi-stage dynamic frequency modulation method will be described in detail with reference to fig. 6 in a manner that two stage PID control modules are connected in series.

Fig. 6 is a block flow diagram illustrating a two-level dynamic frequency modulation method 600 in accordance with an embodiment of the present disclosure. As will be appreciated, the method 600 is the case when N is equal to 2 in the N-stage dynamic frequency modulation method described above with respect to fig. 5, i.e., the adjustment amount is determined using a primary PID control block and a final PID control block in series and output from the final PID control block.

As shown in FIG. 6, the method 600 may obtain the predetermined execution period T of the primary PID control module of at least one chip respectively₁A first average power consumption value 601 (e.g., 1 second) and an average power consumption reference value 602 associated with the primary PID control module. The method 600 may then input the first average power consumption value and the average power consumption reference value into the primary PID control module 603. Further, the method 600 may input the output value of the primary PID control module 603, i.e. the current adjustment amount and the real-time power consumption target value of the previous adjustment operation, into a processing module for calculation, and the output of the processing module is the real-time power consumption target value 604 of the current adjustment operation. Thereafter, the method 600 may input it to the final PID control block 606. Next, the adjustment amount is output by the final stage PID control block 606 based on the real-time power consumption sampling value 605 and the real-time power consumption target value 604 of the present adjustment operation. The working flow of inputting the real-time power consumption target value and the real-time power consumption sampling value to the final stage PID control module is the same as or similar to the method for performing single-stage frequency modulation on the chip described above with reference to fig. 3, and will not be described again here.

Finally, at step 607, the method 600 may adjust the clock frequency of the previous chip adjust operation based on the last stage PID control block 606 output value and the clock frequency of the previous chip adjust operationAnd acquiring the clock frequency of the current adjustment operation of the chip, and executing corresponding frequency modulation action according to the clock frequency. As previously mentioned, the adjustment amount may be an increment relative to the previous adjustment of the clock frequency. In one embodiment, the predetermined execution period T of the primary PID control module₁(e.g., 1 second) greater than the sample period T of the real-time power consumption sample value_N(e.g., 1 millisecond).

Fig. 7 is a block flow diagram illustrating a three-level dynamic frequency modulation method 700 in accordance with an embodiment of the present disclosure. Further details of the scheme of the present disclosure are provided herein on the basis of fig. 5-6, and thus the description of the multi-level dynamic frequency modulation made with respect to fig. 5-6 is also applicable to the operation of fig. 7. As shown in fig. 7, the case when N is equal to 3 in the N-stage dynamic frequency modulation method is depicted here, that is, the adjustment amount is determined by using the primary PID control block, the second stage PID control block, and the final stage PID control block connected in series, and is output from the final stage PID control block.

Specifically, the method 700 obtains the predetermined execution periods T of the primary PID control modules of the at least one chip, respectively₁A first average power consumption value 701 (e.g., 1 second) and an average power consumption reference value 702 associated with the primary PID control module are input to the primary PID control module 703 to cause it to output an adjusted value for a second average power consumption target value associated with the secondary PID control module 706. Next, the method 700 obtains a predetermined execution period T for the second stage PID control module₂A second average power consumption value 705 and input to a second stage PID control module 706. Further, the second average power consumption target value is adjusted by using the adjustment value to obtain an adjusted second average power consumption target value 704, and the adjusted second average power consumption target value is input to the second stage PID control module 706.

Further, the real-time power consumption target value 707 of the present adjustment operation is obtained based on the output value of the second stage PID control block 706 and the real-time power consumption target value of the previous adjustment operation, and is input to the final stage PID control block 709. Next, the adjustment amount is output by the final stage PID control block 709 based on the real-time power consumption sampling value 708 and the real-time power consumption target value 707 of the current adjustment operation. In one embodimentThe sampling period of the real-time power consumption sampling value is T_NAnd a predetermined execution period T of the second stage PID control block₂Satisfy the relation T₁(e.g., 1 second)>T₂(e.g., 200 milliseconds)>T_N(e.g., 1 millisecond). In one exemplary implementation scenario, when the average power consumption reference value as the input value of the primary PID control module is TDP power consumption (e.g., 75 watts), if the first average power consumption value is lower than the average power consumption reference value (i.e., TDP power consumption) within a predetermined execution period (e.g., 1 second), the input value of the next-stage PID control module (e.g., the second-stage PID control module) may be raised such that the average power consumption target value is reduced by the power consumption suppressing strength; on the contrary, when the first average power consumption value is higher than the average power consumption reference value (i.e. TDP power consumption), the average power consumption target value of the next stage PID control module may be reduced to increase the power consumption suppression.

After obtaining the clock frequency adjustment amount of the at least one chip, as shown in fig. 6, in step 710, the method 700 may obtain the clock frequency of the current adjustment operation of the chip based on the output value of the last PID control module 709 and the clock frequency of the previous adjustment operation of the chip, and perform a corresponding frequency modulation action according to the clock frequency.

Fig. 8 is a block flow diagram illustrating a method 800 of multi-level dynamic frequency modulation in accordance with an embodiment of the present disclosure. Further details of the scheme of the present disclosure are provided herein on the basis of fig. 5-7, and thus the description of the multi-level dynamic frequency modulation made with respect to fig. 5-7 is also applicable to the operation of fig. 8.

As shown in fig. 8, it shows the case when N is greater than or equal to 4 in the N-stage dynamic frequency modulation method, that is, the adjustment amount is determined by using the primary PID control block, the second stage PID control block, … …, the N-1 th stage PID control block, and the final stage PID control block connected in series, and is output from the final stage PID control block.

First, the method 800 acquires the primary 803 to N-1 stage PID control modules 809 for their respective predetermined execution periods T₁，……T_N-1The first average power consumption value 801, the second average power consumption value 805 to the N-1 average power consumption value 808 are respectively inputInto the primary stage PID control module 803, the secondary stage PID control modules 806, … … through the N-1 stage PID control module 809. In one embodiment, the respective predetermined execution periods T of the primary to N-1 stage PID control modules₁，……T_N-1And the sampling period T of the real-time power consumption sampling value_NSatisfy the relation T₁(e.g., 1 second)>T₂(e.g., 500 milliseconds) … … T_N-1(e.g., 50 milliseconds)>T_N(e.g., 1 millisecond). Next, the first average power consumption value 801 and the average power consumption reference value 802 associated with the primary PID control module are input to the primary PID control module 803, and the outputs of the primary PID control module through the N-2 th stage PID control module, each of which is an adjustment value for the average power consumption target value associated with the corresponding subsequent stage PID control module, are input to the respective subsequent stage PID control modules. Further, the average power consumption target value of the corresponding next stage is adjusted by each adjustment value to obtain the adjusted second average power consumption target values 804, … … and the N-1 th average power consumption target value 807, and the adjusted second average power consumption target values and the adjusted N-1 th average power consumption target values are input to the corresponding second stage PID control modules 806, … … to N-1 th PID control modules 809, respectively.

Further, the real-time power consumption target value 810 of the present adjustment operation is obtained based on the output value of the N-1 stage PID control block 809 and the real-time power consumption target value of the previous adjustment operation, and is input to the final stage PID control block 812. And outputting the adjustment amount by using a final stage PID control block 812 based on the real-time power consumption sampling value 811 and the real-time power consumption target value 810 of the current adjustment operation. The working flow of inputting the real-time power consumption sampling value and the real-time power consumption target value to the final stage PID control module is the same as or similar to the method for performing single-stage frequency modulation on the chip described above with reference to fig. 3, and will not be described again here. Finally, at step 813, the method 800 may obtain the clock frequency of the current adjusting operation of the chip based on the output value of the last PID control module 812 and the clock frequency of the previous adjusting operation of the chip, and perform a corresponding frequency modulation action according to the clock frequency.

The foregoing of the present disclosure describes the acquisition power consumption and its frequency modulation scheme in connection with at least one chip. However, the scheme of the present disclosure is also applicable to collecting power consumption of a board including one or more chips. In other words, the object of the present disclosure to collect power consumption may be either a chip or a board including a chip. The method of frequency modulation will be further described with reference to fig. 9 by taking the power consumption of the whole board of the acquisition board as an example.

Fig. 9 is a block flow diagram illustrating a frequency modulation method 900 with multiple stages and fast down conversion in accordance with an embodiment of the present disclosure. It can be understood by those skilled in the art that the technical solution of fig. 9 is a frequency modulation method after combining the fast down-conversion and the multi-stage PID frequency modulation shown in fig. 4-8. Therefore, the technical details described in relation to fig. 4-8 are equally applicable in fig. 9.

As shown in fig. 9, at step 901, the end of the last frequency modulation action, i.e. during the process of frequency modulating the chip by the output of the final stage PID, is waited. Since the frequency modulation action takes a certain time from the beginning to the completion of the execution, after the frequency modulation begins, in the time period from the time when the frequency modulation is finished to the time when the frequency modulation is finished, the scheme of the disclosure also allows other tasks (such as the task executed by the main loop 102 shown in fig. 1) to be executed in parallel, so that the efficiency of the dynamic frequency modulation can be improved. Until the previous frequency tuning action is completed, the method 900 proceeds to step 902, where the power consumption of the entire board, which may be a board card including one or more chips to be tuned, may be obtained. In an actual scene, for example, the power consumption of the whole board can be collected in real time through a sensor on the board card to obtain a real-time power consumption sampling value during the operation of the whole board, and the power consumption of the chip can also be collected in real time through the sensor on the board card to obtain a real-time power consumption sampling value during the operation of at least one chip, so that the real-time power consumption sampling value of the whole board is obtained. Next, at step 903, after each time one whole board real-time power consumption sampling value is obtained, the method 900 determines whether the whole board real-time power consumption sampling value is greater than or equal to a whole board fast down-conversion threshold. In one embodiment, the fast down threshold may be calculated according to the aforementioned equation (2). In another embodiment, the threshold may also be adjusted in a certain range according to the measured result based on the value calculated by the foregoing formula (2), and the adjustment range may be determined according to an empirical value.

When the whole board real-time power consumption sample value is less than the whole board fast down threshold, the method 900 proceeds to step 904 where an average power consumption value over a predetermined time period (e.g., 1 second) is calculated. Next, at step 905, the method 900 performs a multi-stage dynamic frequency modulation operation, i.e., the multi-stage PID frequency modulation operation described above in conjunction with fig. 6-8. Finally, at step 906, the method 900 adjusts the clock frequency of the previous operation according to the determined adjustment amount and the chip to obtain the frequency modulation parameter (i.e., the clock frequency) adjusted by the current operation of the chip.

Conversely, when the whole-board real-time power consumption sample value is greater than or equal to the whole-board fast down-conversion threshold, then the method 900 calculates a target frequency value for the whole-board fast down-conversion at step 908. This situation may occur, for example, when the instantaneous power consumption of the whole board is detected to be large (e.g., more than 1.2 times TDP), and then a fast down-conversion operation is performed to reduce the chip frequency in a short time to meet the demand of the board power consumption. Before the fast down-conversion operation is performed, the target frequency value to be adjusted by the chip needs to be determined. In one or more embodiments, the target frequency value may be calculated according to equation (3) previously described.

Finally, after adjusting the clock frequency of the operation according to the chip obtained in

step

906 or 908, in step 907, the method 900 performs a corresponding frequency adjustment operation according to the clock frequency. Based on the above description in conjunction with fig. 1-9, those skilled in the art will appreciate that a method for chip frequency adjustment illustrated in fig. 1-9 may also be implemented in one or more devices in various forms. These implementations may include, but are not limited to, the following four forms: 1) the chip hardware has or supports certain dynamic frequency modulation capability, and the PID module disclosed by the invention is constructed by a hardware analog circuit and/or a digital circuit to realize the frequency modulation operation of the chip hardware; 2) the data such as locally acquired power consumption or chip occupancy rate related to the power consumption is processed by an upper layer driver or an operating system kernel in a manner similar to the PID module of the disclosure, so that the chip is subjected to dynamic frequency modulation control; 3) performing frequency modulation operation on the chip through equipment arranged outside the chip; 4) and carrying out frequency modulation operation on the chip through equipment arranged in the chip. With regard to the 3 rd and 4 th implementation forms herein, the following will be specifically explained in conjunction with fig. 10 and 11.

Fig. 10 shows a schematic block diagram of frequency modulation of a chip using the apparatus of an embodiment of the present disclosure, while fig. 11 shows another schematic block diagram of frequency modulation of a chip using the apparatus of an embodiment of the present disclosure. As can be seen from the two figures, the device of the present disclosure can be placed either outside or inside the chip for frequency-modulated operation of at least one chip.

As shown in fig. 10, device 1001 performs frequency modulation operations on chip 1004 externally to the chip. The apparatus 1001 comprises an obtaining module 1003 configured to obtain at least one real-time power consumption sample value when the chip is operating and an average power consumption value over N-1 predetermined execution cycles, where N is a positive integer greater than or equal to 2. In one embodiment, the acquisition module may be a sensor. The apparatus 1001 may further include a PID control module 1002, which may be, for example, a single stage or N progressive serial PID control modules, to perform a dynamic frequency tuning operation on the chip 1004. In one embodiment, the PID control module 1002 may be implemented on an MCU ("Microcontroller Unit micro control Unit"). Thus, the device 1001 may be an MCU.

Although not shown in fig. 10, it is also conceivable that the above-mentioned apparatus may further include, in order to implement the scheme of fast down-conversion, based on the foregoing description in conjunction with fig. 4 to 9, by those skilled in the art: a determination module configured to determine whether the real-time power consumption sample value is greater than or equal to a fast down-conversion threshold; and the fast frequency-reducing module is configured to execute fast frequency-reducing operation on the at least one chip when the real-time power consumption sampling value is greater than or equal to the fast frequency-reducing threshold value.

For the way of frequency modulation control by the external device shown in fig. 10, the chip receiving the dynamic frequency modulation may be configured as an interface with a modified frequency, and the external device may implement the dynamic frequency modulation on the chip only by modifying or upgrading the firmware thereof, so that the operation is convenient and flexible. In addition, the local data is managed directly after being collected (for example, at a board), so that the data processing speed is faster than that of an upper driver or an operating system kernel.

As shown in fig. 11, the device for frequency modulation of the present disclosure may also be placed inside a chip to implement the frequency modulation operation on the chip, i.e., chip 1102 internally contains device 1101, which is used to perform the frequency modulation operation on the chip. In some application scenarios, the device 1101 may be embodied as software code (e.g., instructions for various scenarios) that resides within a chip. Since the descriptions of fig. 2-9 regarding single-stage, multi-stage, and fast down conversion of the chip are also applicable to the apparatus of fig. 11, they will not be described herein again.

In addition to the exemplary device block diagrams shown in fig. 10 and 11, aspects of the present disclosure may also be implemented in an integrated circuit chip that includes a device 1101 for frequency tuning the chip. In some scenarios, the aforementioned device 1101 may be a core of a chip. When the integrated circuit chip is in operation, the core may be configured to perform the above-described method for frequency tuning a chip. The Integrated Circuit chip may be implemented by hardware such as a CPLD ("Complex Programmable Logic Device"), an FPGA ("Field Programmable Gate Array"), an ASIC (Application Specific Integrated Circuit) for a dedicated Application, an MPU (Microprocessor Unit), and a CPU (Central Processing Unit).

In addition, those skilled in the art will also appreciate that aspects of the present disclosure may also be implemented in a device or board. In particular, the apparatus comprises at least one processor; at least one memory storing program instructions that, when executed by the at least one processor, cause the apparatus to perform the above-described method for frequency tuning a chip. Further, the board card comprises the above device for frequency modulation of the chip. In another aspect, when the frequency tuning operation of the present disclosure is implemented by program instructions, the present disclosure also discloses a computer readable storage medium storing program instructions for tuning a chip, which when executed by a processor, performs the above-described frequency tuning operation.

Fig. 12 is a block diagram illustrating a structure of a combined processing device 1200 according to an embodiment of the present disclosure. As shown in fig. 12, the combined processing apparatus 1200 includes a frequency modulation apparatus 1201 having the foregoing architecture, which can be configured to perform the frequency modulation method described in conjunction with the foregoing figures. In addition, the combined processing device also includes a general interconnect interface 1202 and other processing devices 1203. The frequency modulation apparatus 1201 according to the present disclosure may interact with other processing apparatus 1203 through the universal interconnection interface 1202 to jointly complete the related operations specified by the user.

According to aspects of the present disclosure, the other processing devices may include one or more types of general and/or special purpose processors such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a neural network processor, etc., and the number thereof may be determined not by limitation but by actual needs. In one or more embodiments, the other processing device may serve as an interface for the frequency modulation device of the present disclosure to external data and control, and perform basic control including, but not limited to, data handling, completing the turning on, turning off, etc. of the frequency modulation device; other processing devices can cooperate with the frequency modulation device to complete the operation task.

According to aspects of the present disclosure, the universal interconnect interface may be used to transmit data and control commands between the frequency modulation device and other processing devices. For example, the fm device may obtain required input data from other processing devices via the universal interconnect interface, and write the input data into a storage device (or memory) on the fm device chip. Further, the frequency modulation device can obtain control instructions from other processing devices through the universal interconnection interface and write the control instructions into a control cache on a frequency modulation device chip. Alternatively or optionally, the universal interconnect interface may also read data in a memory module of the frequency modulation device and transmit the data to other processing devices.

Optionally, the combined processing device may further include a storage device 1204, which may be connected to the frequency modulation device and the other processing device, respectively. In one or more embodiments, the memory device may be used to store data for the frequency modulation device and the other processing devices, particularly data that may not be stored in its entirety in an internal or on-chip memory device of the frequency modulation device or other processing devices.

According to different application scenes, the combined processing device disclosed by the invention can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, the core area of a control part is effectively reduced, the processing speed is increased, and the frequency of a chip is adjusted so as to reduce the overall power consumption. In this case, the general interconnection interface of the combined processing apparatus is connected with some components of the device. Some of these components may be, for example, a camera, a display, a mouse, a keyboard, a network card, or a Wifi interface.

In some embodiments, the disclosure also discloses a chip comprising the frequency modulation device or the combined processing device. In other embodiments, the present disclosure also discloses a chip packaging structure, which includes the above chip.

In some embodiments, the present disclosure also discloses a board card including the above chip package structure. Referring to fig. 13, the aforementioned exemplary board is provided, and the board may include other accessories besides the chip 1301, including but not limited to: a memory device 1302, an interface device 1303 and a control device 1304.

The memory device is connected with the chip in the chip packaging structure through a bus and used for storing data. The memory device may include multiple sets of

memory cells

1305 and 1306. Each group of the storage units is connected with the chip through a bus. It is understood that each group of the memory cells may be a DDR SDRAM ("Double Data Rate SDRAM," Double Data synchronous dynamic random access memory, "DDR for short).

The DDR described above can double the transmission speed of the SDRAM without increasing the clock frequency. DDR allows data to be transferred on both the rising and falling edges of a clock pulse. DDR has twice the transmission speed of standard SDRAM. In one embodiment, the memory device may include 4 groups of the memory cells. Each group of the memory cells may include a plurality of DDR4 particles (chips). In one embodiment, the chip may internally include 4 72-bit DDR4 controllers, and 64 bits of the 72-bit DDR4 controller are used for data transmission, and 8 bits are used for ECC check. It can be understood that when DDR4-3200 particles are adopted in each group of memory cells, the theoretical bandwidth of data transmission of a single memory cell can reach 25600 MB/s.

In one embodiment, each group of the memory cells includes a plurality of double rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. And a controller for controlling DDR is arranged in the chip and is used for controlling data transmission and data storage of each memory unit.

The interface device is electrically connected with a chip in the chip packaging structure. The interface means are used to enable data transmission between the chip and an external device 1307, such as a server or computer. For example, in one embodiment, the interface device may be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface, so as to implement data transfer. Preferably, when PCIE 3.0X 16 interface transmission is adopted, the theoretical bandwidth can reach 16000 MB/s. In another embodiment, the interface device may also be another interface, and the disclosure does not limit the concrete expression of the other interface, and the interface unit may implement the switching function. In addition, the calculation result of the chip is still transmitted back to an external device (e.g., a server) by the interface device.

The control device is electrically connected with the chip. The control device is used for monitoring the state of the chip. Specifically, the chip and the control device may be electrically connected through an SPI interface. The control device may include a CPU or a single chip microcomputer. In one or more embodiments, the chip may include a plurality of processing chips, a plurality of processing cores, or a plurality of processing circuits, which may carry a plurality of loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can regulate and control the working states of a plurality of processing chips, a plurality of processing cores and/or a plurality of processing circuits in the chip.

In some embodiments, the present disclosure also discloses an electronic device or apparatus, which includes the above board card. According to different application scenarios, the electronic device or apparatus may include a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a vehicle data recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be in an electrical, optical, acoustic, magnetic or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the scheme of the embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.

The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. With this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product stored in a memory, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U disk, a Read-Only Memory ("ROM"), a Random Access Memory ("RAM"), a removable hard disk, a magnetic or optical disk, and the like.

In the above embodiments of the present disclosure, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments. The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The foregoing may be better understood in light of the following clauses:

clause a1, a method for frequency tuning a chip, comprising:

acquiring a real-time power consumption sampling value when at least one chip is operated;

determining an error value between the real-time power consumption sampling value and the power consumption target value according to the real-time power consumption sampling value and the power consumption target value; and

determining, with a PID control module, an adjustment amount for adjusting a clock frequency of the at least one chip based on the error value.

Clause a2, the method of clause a1, wherein the PID control module comprises a proportional control unit, wherein determining the adjustment amount with the PID control module comprises:

obtaining a proportional term with the proportional control unit based on the error value; and

a first adjustment amount for adjusting the clock frequency is determined based on the proportional term.

Clause A3, the method of clause a2, wherein obtaining the proportional term includes obtaining the proportional term as a function of the error value and a selected scaling factor.

Clause a4, the method of clause a2 or A3, wherein the first adjustment amount is a first increment relative to a previous adjustment of the clock frequency.

Clause a5, the method of clause a1, wherein the PID control module comprises a proportional control unit and at least one of an integral control unit and a derivative control unit, wherein determining the adjustment amount with the PID control module comprises:

determining a second adjustment amount for adjusting the clock frequency of the at least one chip based on the proportional term and an integral term obtained by the integral control unit; or

Determining a third adjustment amount for adjusting the clock frequency of the at least one chip based on the proportional term and a differential term obtained with the differential control unit; or

Determining a fourth adjustment amount for adjusting the clock frequency of the at least one chip based on the proportional term, the integral term, and the differential term.

Clause a6, the method of clause a5, wherein each of the second, third, and fourth adjustment amounts is an increment relative to a previous adjustment of the clock frequency.

Clause a7, the method of clause a5, wherein obtaining the real-time power consumption sample value comprises periodically obtaining a plurality of the real-time power consumption sample values, wherein determining the integral term comprises performing, for each of the real-time power consumption sample values, for a predetermined period of time:

determining an error value between each real-time power consumption sampling value and the power consumption target value;

performing an accumulation operation on the error value determined each time to obtain an accumulated sum; and

an integral term is obtained with the integral control unit based on the accumulated sum.

Clause A8, the method of clause a7, wherein obtaining the integral term comprises obtaining the integral term according to the accumulated sum and a selected integral coefficient.

Clause a9, the method of clause A8, further comprising limiting the integral term to a selected range so as to clear the effects of stiction and avoid overshoot operation.

Clause a10, the method of clause a7, wherein when the predetermined time period arrives, the method further comprises:

and performing zero clearing operation on the accumulated sum so as to perform the accumulation operation in the next preset time period.

Clause a11, the method of clause a7, wherein when a predetermined number of sampling cycles within the predetermined time period arrives, the method further comprises:

clearing the error value of the earliest sampling period in the predetermined number of sampling periods in the accumulation sum so as to perform the accumulation operation on the error value of the latest sampling period.

Clause a12, the method of clause a5, wherein determining the adjustment amount with the derivative control unit in the PID control module comprises:

performing a subtraction operation on the error value determined this time and the error value determined last time to obtain a differential difference value; and

obtaining a derivative term with the derivative control unit based on the derivative difference.

Clause a13, the method of clause a12, wherein obtaining the derivative term comprises obtaining the derivative term as a function of the derivative difference and a selected derivative coefficient.

Clause a14, a method for frequency tuning a chip, comprising:

determining whether the real-time power consumption sampling value is greater than or equal to a fast down-conversion threshold;

when the real-time power consumption sampling value is larger than or equal to the quick frequency reduction threshold value, executing quick frequency reduction operation on the at least one chip;

when the real-time power consumption sampling value is smaller than the fast frequency reduction threshold value, executing:

Clause a15, an apparatus for frequency tuning a chip, comprising:

the acquisition module is configured to acquire a real-time power consumption sampling value when at least one chip operates;

a PID control module configured to:

determining an adjustment amount for adjusting a clock frequency of the at least one chip based on the error value.

Clause a16, an apparatus for frequency tuning a chip, comprising:

a determination module configured to determine whether the real-time power consumption sample value is greater than or equal to a fast down-conversion threshold;

a fast down-conversion module configured to perform a fast down-conversion operation on the at least one chip when the real-time power consumption sample value is greater than or equal to the fast down-conversion threshold; and

a PID control module configured to perform, when the real-time power consumption sample value is less than the fast down threshold:

an adjustment amount for adjusting a clock frequency of the at least one chip is determined based on the error value.

Clause a17, an apparatus for frequency tuning a chip, comprising:

at least one processor;

at least one memory storing program instructions that, when executed by the at least one processor, cause the apparatus to perform the method of any of claims 1-14.

Clause a18, a board for frequency tuning a chip, comprising the apparatus according to any one of claims 15-17.

Clause a19, an integrated circuit chip comprising a core for frequency tuning the chip, the core being configurable to perform the method of any one of claims 1-14 when the integrated circuit chip is in operation.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if it is determined [ a described condition or event ]" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ a described condition or event ]" or "in response to detecting [ a described condition or event ]".

The foregoing detailed description of the embodiments of the present disclosure has been presented for purposes of illustration and description and is intended to be exemplary only and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Meanwhile, a person skilled in the art should, according to the idea of the present disclosure, change or modify the embodiments and applications of the present disclosure. In view of the above, this description should not be taken as limiting the present disclosure.

Claims

1. A method for frequency modulating a chip, comprising:

2. The method of claim 1, wherein the PID control module comprises a proportional control unit, wherein determining the adjustment amount with the PID control module comprises:

3. The method of claim 2, wherein obtaining the scaling term comprises obtaining the scaling term as a function of the error value and a selected scaling factor.

4. A method as claimed in claim 2 or 3, wherein the first adjustment amount is a first increment of the clock frequency relative to a previous adjustment.

5. The method of claim 1, wherein the PID control module comprises a proportional control unit and at least one of an integral control unit and a derivative control unit, wherein determining the adjustment amount with the PID control module comprises:

6. The method of claim 5, wherein each of the second, third, and fourth adjustment amounts is an increment relative to a previous adjustment of the clock frequency.

7. The method of claim 5, wherein obtaining the real-time power consumption sample value comprises periodically obtaining a plurality of the real-time power consumption sample values, and wherein determining the integral term comprises performing, for each of the real-time power consumption sample values, for a predetermined period of time:

8. The method of claim 7, wherein obtaining the integral term comprises obtaining the integral term based on the accumulated sum and a selected integral coefficient.

9. The method of claim 8, further comprising limiting the integral term to a selected range to clear out effects of static and avoid overshoot operation.

10. The method of claim 7, wherein when the predetermined time period is reached, the method further comprises:

11. The method of claim 7, wherein when a predetermined number of sampling cycles within the predetermined time period arrives, the method further comprises:

12. The method of claim 5, wherein determining the adjustment amount with the derivative control unit in the PID control module comprises:

13. The method of claim 12, wherein obtaining the differentiation term comprises obtaining the differentiation term as a function of the differential difference and a selected differentiation coefficient.

14. A method for frequency modulating a chip, comprising:

15. An apparatus for frequency modulating a chip, comprising:

a PID control module configured to:

16. An apparatus for frequency modulating a chip, comprising:

17. An apparatus for frequency modulating a chip, comprising:

at least one processor;

18. A board for frequency modulation of a chip comprising a device according to any one of claims 15-17.

19. An integrated circuit chip comprising a core for frequency tuning the chip, the core being configurable to perform the method of any one of claims 1-14 when the integrated circuit chip is in operation.