CN113443602B - Wafer level packaging structure of micro-electromechanical system chip and manufacturing process thereof - Google Patents

Abstract

The present invention relates to the field of wafer level packaging of chips, and more particularly, to wafer level packaging of mems chips susceptible to package stress and related fabrication processes. The wafer-level packaging structure comprises a substrate and a cover plate, wherein the substrate is a micro-electromechanical system chip to be packaged, and a concave part is formed on the cover plate. The cover plate and the base plate are bonded to form a sealed cavity, and the base plate in the cavity is provided with a micro-electromechanical element. The cover plate can be divided into a plurality of mutually insulated elastic electric pins through scribing. The bottom of the electric pin is smaller than the top, and the electric pin is in a mushroom-shaped structure and has the effect of releasing packaging stress. The wafer level package can reduce package stress, thereby improving the performance of the micro-electromechanical system chip. In addition, the wafer-level packaged micro-electromechanical system chip has smaller volume and low packaging cost, meets the requirement of flip-chip ball bonding, and is beneficial to improving the integration level of the micro-electromechanical system.

Description

MEMS chip wafer level packaging structure and its manufacturing process

Technical field

The present invention relates to chip wafer level packaging, in particular to a wafer level packaging structure and manufacturing process of a microelectromechanical system chip that is easily affected by packaging stress.

Background technique

In the production process of integrated circuit chips, chip packaging is a very important link. Since the feature size on the chip is very small, it is difficult for the metal contacts to be directly connected to the wires on the circuit board. It is necessary to use packaging technology to establish a connection between the contacts on the chip and the circuit board. In addition, in actual use, chips generally need to be protected to prevent accidental damage. The traditional chip packaging technology is to fix the pre-processed and divided single chip in the packaging tube, use wire bonding technology to electrically connect the contacts on the chip to the electrical pins on the packaging tube, and finally to the packaging tube. The shell is filled with insulating packaging material or sealed with a cover plate. Commonly used packaging shells and packaging materials include plastics, ceramics, metals, etc. With the development of semiconductor manufacturing processes, wafer level packaging (Wafer Lever Packaging, WLP) has been developed to improve integration and reduce chip manufacturing costs. Wafer-level packaging technology first packages the silicon wafer, sets metal solder balls on each contact on the wafer, and finally divides the wafer into individual chips. The divided individual chips are directly electrically connected to the circuit board through flip-chip ball bonding technology, eliminating the need for packaging tubes and their leads and pins, which is beneficial to reducing parasitic coupling. Since the chip itself is a package, this packaging process is also called Chip Scale Package (CSP). Compared with traditional shell-level packaging, wafer-level packaging chips are smaller and have lower manufacturing costs. They are also more suitable for use in small mobile applications or highly integrated systems.

In recent years, Micro-Electro-Mechanical Systems (MEMS) have been widely used in various fields. Micron-level mechanical structures and electrodes are processed on microelectromechanical system chips, which can realize the transmission or sensing of physical, acoustic, optical, magnetic and other signals, and thus make a variety of sensors and actuators, such as pressure gauges, Accelerometer, gyroscope, microphone, micromirror, magnetometer, etc. The packaging technology of micro-electromechanical system chips draws on many of the packaging technologies of the above-mentioned integrated circuit chips, and on this basis, it puts forward more additional requirements. Since microelectromechanical components are very fragile and easily damaged by external pollutants or particles, they generally need to be sealed with a cover plate for protection. In addition, the gaps between microstructures in microelectromechanical components are also on the micron scale. Therefore, any deformation caused by packaging stress will have a great impact on the performance of the microelectromechanical system. Currently, the shell materials used for microelectromechanical system chip packaging are still mainly plastics, ceramics or metals. However, since MEMS chips are mostly composed of single crystal silicon, the mismatch in Young's modulus and thermal expansion coefficient between the package material and single crystal silicon will introduce packaging stress, which is often transmitted to the MEMS chips. Stress-sensitive structures thus lead to reduced chip performance. In addition, tube and shell packaging also has the disadvantages of higher cost and larger packaging volume. Wafer-level packaging technology is also suitable for microelectromechanical system chip packaging. Generally, the cover silicon wafer and the microelectromechanical system silicon wafer are bonded first, thereby achieving the wafer-level sealing requirements and also avoiding the need for The problem of mismatch between Young's modulus and thermal expansion coefficient between different materials. Compared with shell-level packaging, wafer-level packaging has a smaller package size and lower cost. However, if the wafer-level packaged MEMS chip is welded to the circuit board through flip-chip ball bonding technology, there will also be a mismatch between the Young's modulus and the thermal expansion coefficient between the circuit board and the chip. At the same time, external stress can also be transmitted to the MEMS chip through the circuit board, causing the MEMS structure inside to deform, greatly affecting the performance of the MEMS system. Therefore, conventional wafer-level packaging technology cannot effectively reduce the impact of packaging stress on MEMS chips.

Contents of the invention

The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a micro-electromechanical system chip packaging method that can release packaging stress, has high integration, high reliability, low manufacturing cost, and is suitable for wafer-level packaging.

A microelectromechanical system chip wafer level packaging structure, including a substrate and a cover plate bonded to each other; the cover plate is made of single crystal silicon; a recessed portion is formed on one side of the cover plate, and the recessed portion is in contact with The substrates are bonded to form a sealed cavity; microelectromechanical components are arranged on the substrate in the cavity; the cover plate and the substrate are bonded to separate a plurality of mutually independent elastic components by dicing. Electrical pins, each elastic electrical pin is electrically connected to the micro-electromechanical element on the substrate through an ohmic contact.

The present invention also has the following additional features:

The cross-sectional area of one end of the elastic electrical pin connected to the micro-electromechanical component is not greater than the cross-sectional area of the other end.

One end of the elastic electrical pin is provided with a metal solder ball.

The cavity is a vacuum sealed cavity.

The ohmic contact includes: aluminum-germanium alloy-silicon ohmic contact, and ohmic contact formed by other metals or alloys and silicon, etc.

A microelectromechanical system chip wafer level packaging process, the packaging process includes the following steps:

In the first step, the substrate silicon wafer pre-processed with micro-electromechanical components is aligned with the pre-processed cover silicon wafer;

In the second step, the aligned cover silicon wafer and substrate silicon wafer are bonded;

The third step is to form solder balls on the top surface of the bonded cover silicon wafer;

The fourth step is to divide the cover silicon wafer by dicing to form an elastic electrical pin structure;

The fifth step is to divide the bonded silicon wafer by dicing to form a sealed, wafer-level packaged MEMS chip with a flexible electrical pin structure.

The processing of the cover silicon wafer in the packaging process also includes the following steps:

In the first step, alignment marks are formed on the top surface of the cover silicon wafer through photolithography and etching;

In the second step, a recessed portion is formed on the bottom surface of the cover silicon wafer through photolithography and etching;

The third step is to deposit metal on the top surface of the cover silicon wafer;

The fourth step is to deposit metal or germanium, preferably germanium, on the bottom surface of the cover silicon wafer.

The cover silicon wafer and the substrate silicon wafer are bonded by one or more of the following bonding methods: aluminum-germanium bonding, metal bonding, eutectic bonding, solder bonding, Silicon wafer bonding is performed by glass powder bonding, silicon-silicon direct fusion bonding, or other hot-pressure bonding methods.

The etching method is one or more of the following methods: dry etching or wet etching. The dry etching includes: deep reactive ions of silicon, reactive ions, and gaseous difluoride. Xenon etching and reactive ion, plasma, and gaseous hydrogen fluoride etching of silicon oxide.

The etchant used for wet etching the silicon layer is one or a combination of more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution .

The etchant used for wet etching the silicon oxide layer is one or a combination of more of the following etchants: hydrofluoric acid and buffered hydrofluoric acid.

The packaging cover of the present invention is basically composed of single crystal silicon and is consistent with the microelectromechanical system chip substrate. Therefore, there will be no packaging stress caused by the mismatch between Young's modulus and thermal expansion coefficient between the substrate and the substrate. The cover can completely protect the microelectromechanical components of the microelectromechanical system chip in the cavity, and external foreign matter cannot contact the fragile microelectromechanical components. The cavity has a sealing function and can provide a stable working environment for the micro-electromechanical components. The elastic electrical pins of this package structure include conductive silicon pillars with a smaller cross-sectional area and a top cover with a larger cross-sectional area, in the form of a mushroom-shaped structure. The conductive silicon pillars with smaller cross-sectional areas are electrically connected to the microelectromechanical components on the substrate through ohmic contacts, which can transmit electrical signals from the substrate to the electrical pin top covers, while the top covers with larger cross-sectional areas are large enough to accommodate metal soldering. balls, so that the micro-electromechanical system chip can be directly electrically connected to the circuit board through flip-chip ball soldering technology. Wafer-level packaging and flip-chip ball bonding technology eliminate the need for packaging leads and pins in general shell-level packaging, significantly reducing parasitic coupling that affects chip performance and greatly reducing package volume. Welding MEMS chips onto circuit boards using flip-chip ball bonding technology will generate packaging stress at the welding location. If this packaging stress is transmitted to stress-sensitive areas of MEMS components on the substrate, it will adversely affect chip performance. The conductive silicon pillars in the present invention play a role in releasing packaging stress: the conductive silicon pillars will be deformed by the packaging stress. With the deformation of the conductive silicon pillars, the packaging stress has been completely released in the conductive silicon pillar structure, thereby ensuring Stress-sensitive areas of MEMS structures on the substrate are not affected by packaging stresses. Although the packaging cover of the present invention has a sealing cavity, conductive silicon pillars, and a ball-welded top cover with various structures with different functions, the side walls of the sealing cavity and the conductive silicon pillars can be formed by only one etching process during the processing process. structure. The elastic electrical pins composed of conductive silicon pillars and top covers are naturally formed during the process of dividing a single chip after completing the wafer-level packaging. There is no need to add additional processing steps. The manufacturing process is very simple and does not require additional steps. manufacturing cost.

Description of the drawings

Figure 1 is a three-dimensional schematic diagram of a wafer-level packaged MEMS chip.

Figure 2 is a three-dimensional schematic cross-section along line AA' in Figure 1.

Figure 3 shows the layout design of the bottom of the cover plate.

Figure 4 shows the layout design of the top of the substrate.

Figure 5 is a schematic diagram of the first and second steps of the manufacturing process of the cover plate.

Figure 6 is a schematic diagram of the third and fourth steps of the manufacturing process of the cover plate.

Figure 7 is a schematic diagram of the first step of the wafer-level packaging process.

Figure 8 is a schematic diagram of the second step of the wafer-level packaging process.

Figure 9 is a schematic diagram of the third step of the wafer level packaging process.

Figure 10 is a schematic diagram of the fourth and fifth steps of the wafer-level packaging process.

Figure 11 is a schematic diagram of the working principle of elastic electrical pins to release package stress.

Figure 12 shows the simulation results of elastic electrical pins releasing package stress.

Cover plate 1, substrate 2, elastic electrical pin 3, cavity 4, microelectromechanical component 5, aluminum 6, germanium 7, silicon oxide 8, aluminum-germanium alloy 9, solder ball 10, circuit board 11, alignment mark 12 , recessed portion 13, electrical connection area 14, packaging stress 15.

Detailed ways

The present invention will be described in detail below with reference to the embodiments and drawings. It should be noted that the described embodiments are only intended to facilitate the understanding of the present invention and do not limit it in any way.

Referring to Figures 1 and 2, an embodiment of a micro-electromechanical system chip wafer-level packaging is provided according to the present invention. In this embodiment, the cover plate 1 and the substrate 2 are bonded to each other. The cover plate 1 is usually made of monocrystalline silicon. The substrate 2 can be selected from single crystal silicon wafers, SOI silicon wafers, etc. according to the final chip structure and manufacturing process. A recessed portion 13 is formed on one side of the cover plate 1 . After the cover plate 1 and the substrate 2 are bonded, a cavity is formed between the recessed portion 13 and the substrate 2 . A plurality of micro-electromechanical components 5 are provided on the substrate 2 in the cavity. The cavity is preferably a vacuum sealed cavity, thereby reducing the impact of foreign matter and temperature on the microelectromechanical component 5 . The substrate 1 is also provided with a metal plate 6. The metal plate 6 is electrically connected to the microelectromechanical element 5 to transmit detection signals. A plurality of independent elastic electrical pins 3 are separated on the cover 1 . Each elastic electrical pin 3 is independent and electrically insulated from each other. Each elastic electrical pin 3 is electrically connected to the metal plate 6 on the substrate 2 respectively, and is further electrically connected to the micro-electromechanical element 5 through the ohmic contact and electrical connection area 14 . For this reason, when bonding the cover 1 and the substrate 2, it is necessary to use a conductive bonding material. Preferably, germanium 7 is provided on the bonding surface of the cover plate 1 , and an aluminum metal plate 6 is provided on the bonding surface of the substrate 2 . When the cover plate 1 and the substrate 2 are bonded, the aluminum 6 and germanium 7 will form an aluminum-germanium alloy 9 at high temperature, and at the same time achieve the function of connecting and conducting electricity between the cover plate 1 and the substrate 2. The main advantage of using the aluminum-germanium alloy bonding method is that after heating, aluminum 6 and germanium 7 become molten, which can overcome the unevenness between the bonding surfaces and achieve an airtight bonding effect. At the same time, the aluminum-germanium alloy 9 has low resistivity and can form ohmic contact with single crystal silicon, which can provide an electrical path for micro-electromechanical system chips. Therefore, when the cover plate 1 and the substrate 2 are combined together through aluminum-germanium bonding, the cover plate 1 can form an electrical connection with the area on the substrate 2 where aluminum 6 is deposited. In addition, the cover plate 1 can be diced to form a plurality of mutually independent elastic electrical pins 3. The tops of these elastic electrical pins 3 are provided with aluminum 6 and may also be provided with solder balls 10. Therefore, the electrical signal detected by the micro-electromechanical system chip can be directly transmitted to the top surface of the cover through the elastic electrical pin 3, and electrically connected to the circuit board 11 through flip-chip ball soldering, eliminating the need for wires, effectively reducing parasitic coupling and The packaging volume is significantly reduced. Figure 3 shows the layout design of the cover plate 1. The blank portion in the figure will be formed with a recessed portion 13 through an etching process, while the unetched bonding portion will be deposited with germanium 7. Correspondingly, Figure 4 shows the layout design of the substrate 2. The part where the metal aluminum 6 is deposited in the figure is bonded to the part where the germanium 7 is deposited on the cover plate 1 during the chip bonding process to form an aluminum-germanium alloy. 9 and combine the cover plate 1 and the base plate 2 into one body.

In addition, in the flip-chip ball bonding package, the micro-electromechanical system chip is welded on the circuit board 11 through flip-chip bonding technology. The circuit board 11 is generally made of plastic or ceramics. Due to the mismatch in the Young's modulus and thermal expansion coefficient of the plastic or ceramic and the silicon material of the MEMS chip, the packaging stress generated by external force or temperature changes will be directly transferred to the MEMS chip, thereby affecting the performance of the MEMS components. accuracy. Different from this, the elastic electrical pin 3 of the present invention is made of silicon and will elastically deform when it is stressed, thereby releasing the packaging stress. In addition, preferably, the cross-sectional area of the connecting end of the elastic electrical pin 3 and the substrate 1 is no larger than the cross-sectional area of the connecting end of the elastic electrical pin 4 and the circuit board 11 . As shown in Figure 11, the packaging stress 15 generated by external force or temperature change will be exerted on the elastic electrical pin 3 to cause it to deform. As the elastic electrical pin 3 is deformed by force, it is distributed among the elastic electrical pin 3. The packaging stress on the microelectromechanical system chip will gradually decrease along the vertical direction until most of the packaging stress has been released when it reaches the surface of the substrate 2, thereby avoiding the stress-sensitive areas on the micro-electromechanical system chip from being affected by the packaging stress and improving the measurement accuracy of the chip. Spend. Figure 12 shows the simulation results of the wafer-level packaged micro-electromechanical system chip affected by packaging stress using the present invention. It shows that when the elastic electrical pin 3 of the micro-electromechanical system chip is subjected to a packaging stress of 250 MPa, the center position of the substrate 2 changes. The amount of stress caused by the package. The abscissa is the side length of the cross section of the elastic electrical pin 3, that is, the thickness of the elastic electrical pin 3; the ordinate is the package stress in the center of the substrate 2. It can be seen that when the side length of the cross-section of the elastic electrical pin 3 is less than 100 microns, the deformation of the elastic electrical pin 3 is enough to release the packaging stress, so that the packaging stress in the stress-sensitive area in the center of the substrate 2 is approximately equal to zero. This simulation result shows that the elastic electrical pin 3 can effectively eliminate the impact of packaging stress on the stress-sensitive area of the substrate 2, and also improves the overall detection accuracy of the chip.

Next, the manufacturing process of wafer-level packaging will be further described with reference to FIGS. 7 to 10 . Its manufacturing steps include:

In the first step, the substrate silicon wafer 2 pre-processed with microelectromechanical components and the pre-processed cover silicon wafer 1 are aligned through the alignment marks 12 .

In the second step, the substrate silicon wafer 2 and the cover silicon wafer 1 are bonded to form a sealed cavity 4. The bonding technology may be one or more of the following: aluminum-germanium bonding, metal bonding, solder bonding, glass powder bonding, silicon-silicon direct melt bonding, or other hot-pressure bonding methods. Silicon wafer bonding.

In the third step, solder balls 10 are formed on the top of the bonded cover silicon wafer 1 .

In the fourth step, the cover silicon wafer 1 is divided by dicing to form multiple independent elastic electrical pin structures.

The fifth step is to divide the bonded silicon wafer as a whole by dicing, including the cover plate and the substrate; thereby forming a sealed, wafer-level packaged micro-electronic chip with elastic electrical pins 3 Electromechanical system chip.

The wafer level packaging method in Figures 7 to 10 also includes pre-processing of the cover silicon wafer 1. Referring to Figures 5 and 6, the processing steps include:

In the first step, photolithography is performed on the top surface of the cover silicon wafer 1, and then deep reactive ion etching or other dry or wet etching is used to form a pattern on the top surface of the cover silicon wafer 1. Align mark 12.

In the second step, photolithography is performed on the bottom surface of the cover silicon wafer 1, and then deep reactive ion etching or other dry or wet etching is used to form a recessed portion on the bottom surface of the cover silicon wafer 1. 13.

In the third step, metal, preferably aluminum 6, is deposited on the top surface of the cover silicon wafer 1.

In the fourth step, a bonding material is deposited on the bottom surface of the cover silicon wafer 1, and the bonding material is preferably germanium 7.

Wherein, the etching method is one or more of the following methods: dry etching or wet etching. The dry etching includes: deep reactive ions, reactive ions, and gaseous reactive ions of silicon. Xenon difluoride etching and reactive ion, plasma, and gaseous hydrogen fluoride etching of silicon oxide.

The etchant used for wet etching the silicon layer is one or a combination of more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution .

The etchant used for wet etching the silicon oxide layer is hydrofluoric acid or buffered hydrofluoric acid.

The package cover of the present invention is basically composed of single crystal silicon like most microelectromechanical system chips, so it does not introduce package stress caused by Young's modulus or thermal expansion coefficient mismatch. The recessed portion of the cover plate is bonded to the substrate to form a sealed cavity, which can effectively protect the microelectromechanical components on the microelectromechanical system chip. After completing the wafer-level packaging, multiple independent elastic electrical pins 3 can be formed on the chip at the same time during the single chip segmentation process. Each elastic electrical pin 3 consists of a thin conductive silicon pillar and a large top cover. Composed into a mushroom-like structure. The elastic electrical pin 3 takes advantage of the conductive properties of silicon and can directly transmit the electrical signal of the micro-electromechanical system chip to the solder ball 10 provided on the top cover of the elastic electrical pin 3, making advanced chip packaging technology such as flip-chip ball soldering possible. Possibly, the volume of the wafer-level packaged micro-electromechanical system of the present invention is much smaller than that of the conventional package-packaged micro-electromechanical system. At the same time, during the packaging process, the elastic electrical pin 3 can release most of the packaging stress through deformation, reducing the impact of packaging stress on the stress-sensitive MEMS components on the MEMS chip, making the chip Accuracy is further improved.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art will understand that , the technical solution of the present invention may be modified or equivalently substituted without departing from the essence and scope of the technical solution of the present invention.

Claims (10)

1. A wafer level packaging structure of a micro-electromechanical system chip comprises a substrate and a cover plate which are bonded with each other; the method is characterized in that: the cover plate is made of monocrystalline silicon; a concave part is formed on one surface of the cover plate, and a sealed cavity is formed after the concave part is bonded with the substrate; a micro-electromechanical element is arranged on the substrate in the cavity; the cover plate is divided into a plurality of mutually independent elastic electric pins through scribing, and each elastic electric pin is electrically connected with the micro-electromechanical element on the substrate through ohmic contact; the elastic electric pin consists of a thin conductive silicon column and a top cover with a larger area, and the cross section area of one end of the elastic electric pin connected with the micro-electromechanical element is smaller than that of the other end.

2. The package structure of claim 1, wherein: one end of the elastic electric pin is provided with a metal solder ball.

3. The package structure of claim 1, wherein the cavity is a vacuum sealed cavity.

4. The package structure of claim 1, wherein the ohmic contact comprises: aluminum-germanium ohmic contacts, aluminum-germanium alloy-silicon ohmic contacts, gold-Jin Oum contacts, silicon-silicon fusion bonding contacts, and solder contacts.

5. A wafer level packaging process for a micro-electro-mechanical system chip, which is characterized in that: the packaging process is used for packaging the wafer-level packaging structure of the micro-electromechanical system chip of any one of claims 1 to 4, and comprises the following steps:

the method comprises the steps of firstly, aligning a substrate silicon wafer with a micro-electromechanical element which is processed in advance with a cover plate silicon wafer which is processed in advance;

bonding the aligned cover plate silicon wafer and the substrate silicon wafer;

thirdly, forming solder balls on the top surface of the bonded cover plate silicon wafer;

fourthly, dividing the cover plate silicon wafer by scribing to form an elastic electric pin structure;

and fifthly, dividing the bonded silicon wafer by scribing to form a sealed micro-electromechanical system chip which is packaged in a wafer level and has an elastic electric pin structure.

6. The mems chip wafer level packaging process of claim 5, wherein: the processing of the cover plate silicon wafer further comprises the following steps:

forming an alignment mark on the top surface of the cover plate silicon wafer through photoetching and etching;

step two, forming a concave part on the bottom surface of the cover plate silicon wafer through photoetching and etching;

thirdly, depositing metal on the top surface of the cover plate silicon wafer;

and fourthly, depositing metal or germanium on the bottom surface of the cover plate silicon wafer.

7. The mems chip wafer level packaging process of claim 5, wherein: the cover plate silicon wafer and the substrate silicon wafer are bonded by one or more of the following bonding methods: the bonding of the silicon wafer is performed by an aluminum-germanium bonding, a metal bonding, a eutectic bonding, a solder bonding, a glass powder bonding, a silicon-silicon direct fusion bonding, or a thermal compression bonding method.

8. The manufacturing process as set forth in claim 6, wherein: the etching method is one or more of the following methods: a dry etch or a wet etch, the dry etch comprising: deep reactive ions of silicon, reactive ions, and gaseous xenon difluoride etching and reactive ions of silicon oxide, plasma, and gaseous hydrogen fluoride etching.

9. The manufacturing process as set forth in claim 6, wherein: the etchant for wet etching the silicon layer is one or a combination of more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution.

10. The manufacturing process as set forth in claim 6, characterized in that: the etchant for wet etching the silicon oxide layer is one or a combination of a plurality of the following etchants: hydrofluoric acid and buffered hydrofluoric acid.