CN113437045A

CN113437045A - Circuit structure

Info

Publication number: CN113437045A
Application number: CN202110492976.5A
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-05-07
Filing date: 2021-05-07
Publication date: 2021-09-24

Abstract

An embodiment of the present invention provides a circuit structure, including: a first dielectric layer having a first opening; a first metal layer in the first opening, a sidewall of the first metal layer being spaced apart from the first dielectric layer; and a second dielectric layer on the first dielectric layer, wherein a portion of the second dielectric layer is located between the sidewall of the first metal layer and the inner wall of the first opening. The invention aims to improve the yield of a circuit structure.

Description

Circuit structure

Technical Field

Embodiments of the invention relate to a wiring structure.

Background

In the conventional layer stacking technology (e.g., via-to-via, line-to-line), most of the processes are performed by first preparing a metal layer/Metallization layer (Metallization layer), a back-cover dielectric layer/Isolation layer (Isolation layer), and then performing a mechanical chemical polishing (CMP) or a mechanical polishing (Grinding), which is generally called a Dual Damascene (Dual Damascene) process, so as to obtain a planarized (Planarization) multi-layer stack structure, but finally, many tiny defects (e.g., scratches, polishing residues, etc.) are often found on the polished surface.

In addition, CMP or mechanical grinding currently accounts for approximately 20% to 30% of the total cost, especially in higher-level products (e.g., 2.5D integrated chips, 3D integrated chips, fan-out packages).

Disclosure of Invention

In view of the problems in the related art, an object of the present invention is to provide a circuit structure and a method for forming the same, so as to improve the yield of the circuit structure.

To achieve the above object, an embodiment of the present invention provides a circuit structure, including: a first dielectric layer having a first opening; a first metal layer in the first opening, a sidewall of the first metal layer being spaced apart from the first dielectric layer; and a second dielectric layer on the first dielectric layer, wherein a portion of the second dielectric layer is located between the sidewall of the first metal layer and the inner wall of the first opening.

In some embodiments, a top surface of a portion of the second dielectric layer between the first metal layer sidewall and the inner wall of the first opening has a gap.

In some embodiments, the top surface of the first metal layer is lower than the top surface of the second dielectric layer.

In some embodiments, in a top view, the second dielectric layer is configured to surround the first metal layer.

In some embodiments, further comprising: and the pad structure is positioned in the first dielectric layer, and the first opening is positioned on the pad structure.

In some embodiments, a lateral dimension of the first opening is smaller than a lateral dimension of the pad structure.

In some embodiments, the second dielectric layer has a second opening over the first metal layer, the second metal layer being located in the second opening, a sidewall of the second metal layer being spaced apart from an inner wall of the second opening.

In some embodiments, further comprising: and the third dielectric layer is positioned on the second dielectric layer and is also positioned between the side wall of the second metal layer and the inner wall of the second opening.

In some embodiments, a first seed layer and a second seed layer are disposed below the first metal layer and the second metal layer, respectively, the first metal layer and the second metal layer separated by the second seed layer.

In some embodiments, the first metal layer and the second metal layer are similar in shape in a top view.

In some embodiments, the first metal layer and the second metal layer partially overlap.

An embodiment of the present application provides a method of forming a line structure, including: forming a first opening in the first dielectric layer; forming a first mask layer on the first dielectric layer and in the first opening; removing part of the first mask layer to form a first opening in the first opening, wherein the first opening does not expose the inner wall of the first opening; forming a first metal layer in the first opening; removing the first mask layer; a second dielectric layer is formed between the inner wall of the first opening and the first metal layer and on the first dielectric layer.

In some embodiments, the second dielectric layer has a gap at a top surface of a portion between an inner wall of the first opening and the first metal layer.

In some embodiments, the first metal layer is formed by electroplating.

In some embodiments, during the electroplating, the thickness of the first metal layer is controlled such that the height of the first metal layer does not exceed the top surface of the first dielectric layer.

In some embodiments, after forming the first opening, and after forming the first mask layer, a first seed layer is formed on the first dielectric layer and in the first opening.

In some embodiments, after removing the first mask layer, the first seed layer is patterned using the first metal layer as a mask.

In some embodiments, after forming the second dielectric layer, the second dielectric layer has a second opening over the first metal layer, and a second seed layer is formed over the second dielectric layer and in the second opening.

In some embodiments, further comprising: forming a second mask layer on the second seed layer; the second mask layer is partially removed to form a second opening in the second opening exposing the second seed layer, an inner wall of the second opening being unexposed.

In some embodiments, further comprising: forming a second metal layer in the second opening; removing the second mask layer;

patterning the second seed layer with the second mask layer as a mask; and forming third dielectric layers between the second metal layer and the inner wall of the second opening and between the second dielectric layers.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A to 1C illustrate a related art process of forming a line structure.

Fig. 2-21 illustrate steps of forming a line structure according to an embodiment of the present application.

Fig. 22 to 26 show different embodiments of the line structure of the present application.

Detailed Description

In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In the application of the circuit layer stacking technique, referring to fig. 1A and 1B, a seed layer 17 and a metal layer 12 are typically plated in a via hole (exposing a pad 15) of a lower dielectric layer 10 [ e.g., Polyamide (PA) ] on a chip 13, and then an upper dielectric layer 14 [ e.g., Polyimide (PI) or silicon dioxide ] is covered, since the metal layer 12 is typically higher than the lower dielectric layer 10, thereby generating a protruding surface on the upper dielectric layer 14, and in order to stack the next circuit layer, a planarization process 11 is used to remove the protruding surface, as shown in fig. 1C. Planarization is usually accomplished by a Chemical Mechanical Polishing (CMP) process, which uses an abrasive material (e.g., a grinding wheel or a gauze) and a dielectric material (e.g., a grinding slurry) to leave micro scratches 16 on the ground surface or cracks 18 between the metal layer 12 and the top dielectric layer 14, so that the ground material is easily left in the stack, and therefore other materials must be used to remove the residual material during the subsequent process, which directly impacts the reliability of the product if the residual material cannot be completely removed and remains on the product.

The circuit structure and the method for forming the same of the present application will be described in detail with reference to the accompanying drawings.

Referring to fig. 2, a first dielectric layer 202 is formed on the semiconductor device 200, in an embodiment, the first dielectric layer 202 is an isolation layer, and the semiconductor device 200 is a chip, wafer, or core layer (PNL). A first opening 26 exposing a first pad 204 of the semiconductor device 200 is formed in the first dielectric layer 202.

Referring to fig. 3, a first seed layer 30 is formed in the first opening 26 and on the first dielectric layer 202, in an embodiment, the first seed layer 30 is formed using a physical deposition Process (PVD).

Referring to fig. 4, a first mask layer 40 is formed on the first seed layer 30, and in an embodiment, the first mask layer 40 may include a Photoresist (PR) material, and a first exposure process 41 is performed to cure the first mask layer 40.

Referring to fig. 5, the first mask layer 40 is patterned to expose the first seed layer 30. And a first metal layer 50 is formed on the exposed first seed layer 30.

Referring to fig. 6, the upper half of fig. 6 is a top view and the lower half of fig. 6 is a cross-sectional view, the patterned first mask layer 40 is removed, and a portion of the first seed layer 30 is removed by a first etching process 61 using the first metal layer 50 as a mask. In an embodiment, the first etching process 61 is a chemical etch.

Referring to fig. 7, a second dielectric layer 70 is formed on the first metal layer 50 and the first dielectric layer 202, the second dielectric layer 70 fills the remaining space of the first opening 26, i.e., is formed between the first metal layer 50, the first seed layer 30, and the sidewall of the first opening 26, and a portion of the second dielectric layer 70 between the inner wall of the first opening 70 and the first metal layer 50 has a gap 72 at the top surface thereof.

Referring to fig. 8, an intermediate mask layer 80 is formed on the second dielectric layer 70, the intermediate mask layer 80 also being formed in the gap 72. In an embodiment, the intermediate mask layer 80 may include a Photoresist (PR) material, and a second exposure process 81 is performed to cure the intermediate mask layer 80.

Referring to fig. 9, the intermediate mask layer 80 is patterned to form a fourth opening 92 exposing the notch 72, and a third opening 90 exposing a portion of the second dielectric layer 70 is also formed beside the fourth opening 92, and a second etching process is performed to remove a portion of the second dielectric layer 70 exposed by the fourth opening 92 and the third opening 90. In an embodiment, the second etching process 91 is a dry etching process using an etching gas, for example.

Referring to fig. 10, after the second etching process 91, the second dielectric layer 70 remains between the sidewalls of the first opening 26 and the first seed layer 30, the first metal layer 50, and the second dielectric layer 70 forms a second opening 104 in the first opening 26. The second gap 102 formed as a result of the gap 72 remains at the top surface of the portion of the second dielectric layer 70 between the sidewalls of the first opening 26 and the first seed layer 30, the first metal layer 50. A second seed layer 100 is formed on the second dielectric layer 70, the second seed layer 100 being formed in the second gap 102.

Referring to fig. 11, a second mask layer 110 is formed on the second seed layer 100, and in an embodiment, the second mask layer 110 may include a Photoresist (PR) material, and a third exposure process 111 is performed to cure the second mask layer 110.

Referring to fig. 12, the second mask layer 110 is patterned to expose the second seed layer 100 in the second opening 104 and the third opening 90, and a second metal layer 120 is formed on the exposed second seed layer 100.

Referring to fig. 13, the upper half of fig. 13 is a top view and the lower half of fig. 13 is a cross-sectional view, the patterned second mask layer 110 is removed, and a portion of the second seed layer 100 is removed by a third etching process 131 using the second metal layer 120 as a mask. In an embodiment, the third etch process 131 is a chemical etch.

Referring to fig. 14, a third dielectric layer 140 is formed on the second metal layer 120, the third dielectric layer 140 being formed between the sidewalls of the second metal layer 120 and the inner walls of the second opening 104. A third dielectric layer 140 is also formed in the second opening 102.

Referring to fig. 15, the above steps are repeated to form a fifth opening 150 in the third dielectric layer 140, a third seed layer 152 located in the fifth opening 150, a third metal layer 154, and a fourth dielectric layer 156 located between the third seed layer 152 and the third metal layer 154 and the inner wall of the fifth opening 150, the fourth dielectric layer 156 also being formed on the third dielectric layer 140. A third mask layer 158 is formed on the fourth dielectric layer 156, in an embodiment, the third mask layer 158 may include a Photoresist (PR) material, and a fourth exposure process 151 is performed to cure the third mask layer 158.

Referring to fig. 16, third masking layer 158 is patterned to form a sixth opening 160 that exposes a portion of fourth dielectric layer 156 located over the previously formed metal layer, and a fourth etch process 161 is performed to remove the portion of fourth dielectric layer 156 exposed by sixth opening 160. In an embodiment, the fourth etching process 161 is a dry etching process using an etching gas, for example.

Referring to fig. 17, the remaining third mask layer 158 is removed and a fourth seed layer 170 is formed in the sixth opening 160 and on the fourth dielectric layer 156.

Referring to fig. 18, a fourth mask layer 180 is formed on the fourth dielectric layer 156, in an embodiment, the fourth mask layer 180 may include a Photoresist (PR) material, and a fifth exposure process 181 is performed to cure the fourth mask layer 180.

Referring to fig. 19, the fourth mask layer 180 is patterned to form a seventh opening 190, the seventh opening 190 is positioned over the previously formed metal layers and the seventh opening 190 exposes a portion of the fourth sub-layer 170, and a fourth metal layer 192 is formed on the exposed fourth sub-layer 170.

Referring to fig. 20, the upper half of fig. 20 is a top view and the lower half is a cross-sectional view, the patterned fourth mask layer 180 is removed, and a portion of the fourth sub-layer 170 is removed by a fifth etch process 201 using the fourth metal layer 192 as a mask. In an embodiment, the fifth etch process 201 is a chemical etch.

Referring to fig. 21, a fifth dielectric layer 210 is formed on the fourth metal layer 192 and on the fourth dielectric layer 156, the fifth dielectric layer 210 also being formed in the remaining space of the seventh opening 190. A chip 212 is formed on the fifth dielectric layer 210 and is electrically connected to the underlying fourth metal layer 192. Up to this point, the line structure 2100 of the present application is not limited to being formed to fig. 21, and the line structure 2100 of the present application may be a line structure shown by a step before fig. 21.

The circuit structure of the present application has a specific material structure, for example, nano-twin, nano-crystal and general crystalline materials, and each metal layer may be, for example, copper, silver, gold, nickel, aluminum, etc.

The line structure of the present application is inexpensive to manufacture and does not have defects (e.g., micro-scratches, byproducts, and/or micro-cracks) around the wire due to the unnecessary CMP or mechanical grinding processes.

The line structure of the present application avoids thermal and/or electrical diffusion problems by providing a seed layer as a barrier layer (e.g., Ti, Ni, W alloy) between metal layers (e.g., via, line-to-line).

In some embodiments, the second dielectric layer 70 and the third dielectric layer 140 are different materials and are disposed in pairs. In an embodiment, the second dielectric layer 70 is an active material and the third dielectric layer 140 is a passive material. In other embodiments, the second dielectric layer 70 is a passive material and the third dielectric layer 140 is an active material.

In some embodiments, the fourth dielectric layer 156 and the fifth dielectric layer 210 are different materials and are disposed in pairs. In an embodiment, the fourth dielectric layer 156 is an active material and the fifth dielectric layer 210 is a passive material. In other embodiments, the fourth dielectric layer 156 is a passive material and the fifth dielectric layer 210 is an active material.

The organic dielectric layer and the inorganic dielectric layer which are arranged in pairs provide the best stress balance, and the problem of warping is effectively solved. The application also enhances the processability and filling capability of each dielectric layer. For the organic dielectric layer and the inorganic dielectric layer provided in a pair, in order to minimize warpage, the stress between the two layers satisfies the following formula σ 1 ═ σ 2(σ 1 ═ E1 · T1 · CTE1 · Δ T, σ 2 ═ E2 · T2 · CTE2 · Δ T), where σ 1 denotes the stress of the first layer, σ 2 denotes the stress of the second layer, E1 denotes the elastic modulus of the material of the first layer, CTE1 denotes the coefficient of thermal expansion of the first layer, CTE2 denotes the coefficient of thermal expansion of the second layer, and Δ T denotes the temperature difference between the two layers. Thus, the thickness between the two layers satisfies the following relation: t2/t1 ═ E2. CTE 2/E1. CTE 1. In some embodiments, the inorganic material may be silicon, glass, ceramic, oxide (e.g., SiOx, TaOx), nitride (e.g., SiNx), and the organic material may be Polyimide (PI), epoxy (epoxy), Polybenzoxazole (PBO), flame retardant grade 4 material (FR4), prepreg (PP), Ajinomotobuild-up film (ABF), bismaleimide triazine resin (BT).

In some embodiments, the metal layer of the present application is made of copper, gold, aluminum, silver, platinum, or palladium, the seed layer of the present application is made of Ni, Ti, W, or an alloy thereof, and the bonding pad of the chip of the present application is made of copper, gold, aluminum, silver, platinum, or palladium.

Fig. 22 shows a different embodiment of the line structure of the present application, wherein an isolation layer 220 is further formed between the chip 200 and the first dielectric layer, and an embedded conductive line 222 is further formed between the chip 200 and the isolation layer 220.

Fig. 23A and 23B show the shape of any two metal layers adjacent up and down of the present application in a plan view. For example, in the embodiment, as shown in fig. 23A, the first metal layer 50 is formed as a via hole, and the second metal layer 120 is formed as a wire. In an embodiment, as shown in fig. 23B, the first metal layer 50 is formed as a conductive line, and the second metal layer 120 is formed as a conductive line.

Fig. 24 illustrates a different embodiment of the present line structure, wherein the top half is a top view taken along line AA' of the bottom half, wherein the first metal layer 50 of the present application is formed as two vias.

Fig. 25 shows a different embodiment of the line structure of the present application, wherein the upper half is a top view taken along line AA' of the lower half, wherein the first metal layer 50 of the present application is formed as one via and two wires.

In some embodiments, the chip 200 of the present application may also be replaced with an organic substrate. In some embodiments, as shown in fig. 26, the chip 200 may be replaced by a connector 260 contacting the pad 204.

The defect that grinding brought has been avoided in the preparation of the line structure of this application, therefore the interface between each layer all is the finish machining surface, provides good mixed bonding interface, and each metal level of this application can be formed through Physical Vapor Deposition (PVD), and the metal level that the PVD technology formed is applicable to and carries out the straight and less lateral wall surface of roughness that the photoetching formed to PR. Because the metal layer formed by the PVD process has strong adhesiveness, the metal layer has good adhesiveness with the dielectric layer formed on the metal layer. The metal layer does not have a protruding structure when the metal layer is plated, so that the protruding surface can not be caused when the second dielectric layer is covered, and the planarization process is avoided.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A wiring structure, comprising:

a first dielectric layer having a first opening;

a first metal layer in the first opening, a sidewall of the first metal layer being spaced apart from the first dielectric layer;

a second dielectric layer on the first dielectric layer, and a portion of the second dielectric layer is between the sidewall of the first metal layer and an inner wall of the first opening.

2. The line structure of claim 1, wherein a top surface of the portion of the second dielectric layer between the sidewall of the first metal layer and the inner wall of the first opening has a gap.

3. The wiring structure of claim 1, wherein the top surface of the first metal layer is lower than the top surface of the second dielectric layer.

4. The circuit structure of claim 1, wherein the second dielectric layer is configured to surround the first metal layer in a top view.

5. The wiring structure according to claim 1, further comprising:

a pad structure in the first dielectric layer, the first opening being on the pad structure.

6. The wiring structure of claim 5, wherein a lateral dimension of the first opening is smaller than a lateral dimension of the pad structure.

7. The line structure of claim 1, wherein the second dielectric layer has a second opening over the first metal layer, a second metal layer located in the second opening, and sidewalls of the second metal layer spaced from inner walls of the second opening.

8. The wiring structure according to claim 7, further comprising:

and the third dielectric layer is positioned on the second dielectric layer and is also positioned between the side wall of the second metal layer and the inner wall of the second opening.

9. The circuit structure of claim 7, wherein a first seed layer and a second seed layer are disposed below the first metal layer and the second metal layer, respectively, and the first metal layer and the second metal layer are separated by the second seed layer.

10. The wiring structure of claim 7, wherein the first metal layer and the second metal layer are similar in shape in top view.