CN113436568B - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN113436568B CN113436568B CN202110739656.5A CN202110739656A CN113436568B CN 113436568 B CN113436568 B CN 113436568B CN 202110739656 A CN202110739656 A CN 202110739656A CN 113436568 B CN113436568 B CN 113436568B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The embodiment of the invention discloses an array substrate and a display device, wherein the array substrate comprises a drive control circuit and an input control circuit, the drive control circuit comprises a first signal input end, the input control circuit comprises a first signal output end, and the first signal input end is electrically connected with the first signal output end; a first supply line for transmitting a first non-constant voltage signal; the output voltage signal is transmitted to the first signal output end through the input control circuit, and the output voltage signal is kept to be positive voltage or negative voltage. In the embodiment of the invention, the first power supply line provides the first non-constant voltage signal, the first non-constant voltage signal can be converted into a positive or negative output voltage signal through the input control circuit, the first power supply line cannot transmit a single-polarity voltage signal for a long time, parasitic capacitance between the first power supply line and other signal lines or structures can be weakened, signal transmission precision is improved, influence on the performance of the array substrate is reduced, and display effect is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate and a display device.
Background
With the progress and development of science and technology, the living standard of people is improved, and the use of display panels has deepened into each electronic product. Therefore, the display panel is manufactured in large quantities, and the display performance of the display panel is required to be higher and higher.
In the current manufacturing process of display panels, how to improve the display performance of the display panels becomes a problem to be solved urgently.
Disclosure of Invention
The embodiment of the invention provides an array substrate and a display device, and aims to improve the display performance of the display device.
An embodiment of the present invention provides an array substrate, including:
the input control circuit comprises a first signal output end, and the first signal input end is electrically connected with the first signal output end;
a first supply line for transmitting a first non-constant voltage signal; and transmitting an output voltage signal to the first signal output end through the input control circuit, wherein the output voltage signal is kept as a positive voltage or a negative voltage.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the array substrate as described above.
In the embodiment of the invention, the signal provided by the first power supply line to the input control circuit is a first non-constant voltage signal, the first non-constant voltage signal is not a direct current fixed level signal, and the first non-constant voltage signal can be converted into a positive output voltage signal and a negative output voltage signal, so that the voltage signal transmitted by the first power supply line is switched between positive and negative, and the first power supply line does not transmit a single-polarity voltage signal for a long time. Therefore, parasitic capacitance between the first power supply line and other signal lines or structures can be weakened, signal transmission precision is improved, influence on performance of the array substrate is reduced, and display effect is improved.
Drawings
To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description, although being some specific embodiments of the present invention, can be extended and extended to other structures and drawings by those skilled in the art according to the basic concepts of the device structure, the driving method and the manufacturing method disclosed and suggested by the various embodiments of the present invention, without making sure that these should be within the scope of the claims of the present invention.
Fig. 1 is a schematic view of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic view of another array substrate according to an embodiment of the present invention;
FIG. 3 is a schematic view of another array substrate according to an embodiment of the present invention;
FIG. 4 is a schematic view of another array substrate according to an embodiment of the present invention;
FIG. 5 is a schematic view of another array substrate according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a power supply signal according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another power supply signal provided by an embodiment of the invention;
FIG. 8 is a schematic view of another array substrate according to an embodiment of the present invention;
FIG. 9 is a schematic view of another array substrate according to an embodiment of the present invention;
fig. 10 is a schematic view of another array substrate according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described through embodiments with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the basic idea disclosed and suggested by the embodiments of the present invention, fall within the scope of protection of the present invention.
Referring to fig. 1, a schematic view of an array substrate according to an embodiment of the invention is shown. The array substrate provided by the embodiment comprises: the driving control circuit 100 comprises a first signal input end IN, the input control circuit 200 comprises a first signal output end OUT, and the first signal input end IN is electrically connected with the first signal output end OUT; a first power supply line S1, the first power supply line S1 being for transmitting a first non-constant voltage signal; the output voltage signal is transmitted to the first signal output terminal OUT through the input control circuit 200, and is maintained as a positive voltage or maintained as a negative voltage.
In this embodiment, the array substrate is an array substrate of a display panel. The display panel comprises a display area and a non-display area, wherein the display area of the display panel is provided with a plurality of pixels, the non-display area of the display panel is provided with a drive control circuit 100, the drive control circuit 100 is specifically positioned in the array substrate, and the drive control circuit 100 is used for driving the pixels of the display area to emit light.
The driving control circuit 100 includes a first signal input terminal IN receiving a voltage signal with a fixed polarity. It is understood that, with reference to 0V, in the present embodiment, the voltage higher than 0V is a positive voltage, and the polarity is positive; voltages lower than 0V are negative voltages, and the polarity is negative. Then the first signal input terminal IN the selectable display panel is the low potential power terminal; alternatively, in other display panels, the first signal input terminal may be a high voltage power supply terminal. For a display panel with the first signal input terminal IN as a low-potential power supply terminal, the voltage signal received by the first signal input terminal IN is always negative voltage. For a display panel with a first signal input terminal being a high potential power supply terminal, a voltage signal received by the first signal input terminal is always a positive voltage.
IN this embodiment, the non-display area of the array substrate further includes an input control circuit 200, and the input control circuit 200 includes a first signal output terminal OUT connected to the first signal input terminal IN of the driving control circuit 100. The input control circuit 200 provides an output voltage signal to a first signal input terminal IN of the driving control circuit 100 through a first signal output terminal OUT.
The first signal input terminal IN of the display panel may be fixed to a low voltage power terminal or a high voltage power terminal, and the polarities of the output voltage signals input to the control circuit 200 are different according to the port property of the first signal input terminal IN. If the first signal input terminal IN of the display panel is a low potential power terminal, the output voltage signal of the input control circuit 200 is kept as a negative voltage; alternatively, in another display panel, if the first signal input terminal is the high potential power source terminal, the output voltage signal of the input control circuit is maintained at a positive voltage.
In this embodiment, the non-display area of the array substrate further includes a first power supplying line S1, the first power supplying line S1 is connected to the input terminal of the input control circuit 200, and the first power supplying line S1 transmits a first non-constant voltage signal to the input control circuit 200. The input control circuit 200 receives the first non-constant voltage signal, converts the first non-constant voltage signal into an output voltage signal with a fixed polarity, and provides the output voltage signal to the first signal input terminal IN of the driving control circuit 100, so that the first signal input terminal IN receives the voltage signal with the fixed polarity.
It should be noted that, in the working process of the display panel, the polarity of the output voltage signal is fixed, but the voltage amplitude of the output voltage signal may be the same or different in different time periods. For example, if the first signal input terminal IN is a low-potential power supply terminal, the output voltage signal is kept at a negative voltage; optionally, during the time period t1, the output voltage signal may be-5V; during the time period t2, the output voltage signal may be-3V.
It will be appreciated that the first supply line S1 provides a first non-constant voltage signal. If the first signal input terminal IN is a low potential power terminal, the first non-constant voltage signal needs to be converted into a negative output voltage signal through the input control circuit 200; if the first signal input terminal IN is a high voltage power terminal, the first non-constant voltage signal needs to be converted into a positive output voltage signal by the input control circuit 200. Therefore, it is unambiguous that the first non-constant voltage signal includes a positive voltage signal and a negative voltage signal. The first non-constant voltage signal with the voltage polarity jumping between the positive and negative is converted into an output voltage signal with a fixed voltage polarity through the input control circuit 200, and then transmitted to the first signal input terminal IN, and the output voltage signal is kept as a positive voltage or a negative voltage.
In this embodiment, the signal provided by the first power supply line to the input control circuit is a first non-constant voltage signal, the first non-constant voltage signal is not a dc fixed level signal, and the first non-constant voltage signal can be converted into a positive output voltage signal and a negative output voltage signal, so that the voltage signal transmitted by the first power supply line switches between positive and negative, and the first power supply line does not transmit a unipolar voltage signal for a long time. Therefore, parasitic capacitance between the first power supply line and other signal lines or structures can be weakened, signal transmission precision is improved, influence on performance of the array substrate is reduced, and display effect is improved.
The first signal input end can be selected as a low-potential power supply end, and the output voltage signal is less than 0V; or, the first signal input end is a high-potential power supply end, and the output voltage signal is greater than 0V.
In the prior art, the power supply line for supplying power to the first signal input terminal is at a low potential for a long time, and is prone to corrosion. The reason for this is that:
for isolated steam, can set up inorganic water barrier in the display panel, inorganic water barrier's main material is silicon nitride, however silicon nitride can not bear the bend radius of bending structure in the display panel, consequently, bending structure place region (pad bonding region) can't set up inorganic water barrier, the regional line of walking of bending this moment can only be wrapped by organic material, organic material does not insulate steam, lead to bending regional line can receive the influence of steam, and the power supply line that supplies power for drive control circuit can extend in the pad bonding region and pass through.
Currently, display panels, such as OLED display panels, mostly adopt aluminum process panels, that is, the constituent materials of conductive structures such as signal lines and the like mostly contain aluminum elements. It will be appreciated that the supply lines supplying the drive control circuitry comprise aluminium metal. Aluminum is a reactive metal, and is likely to corrode when a low-level signal is applied thereto for a long time, and in order to avoid corrosion, a protective film made of a dense oxide, which is aluminum oxide, is often formed on the surface of the feeder line.
For a feed line without silicon nitride protection in the pad bonding area. If the signal that this power supply line transmitted is positive voltage signal, then aluminium element is electrified to be positive potential in the power supply line, and then aluminium and steam take place oxidation reaction for aluminium becomes aluminium oxide, has thickened the aluminium oxide protection film of power supply line, so can avoid the power supply line to corrode. If the signal transmitted by the power supply line is a negative voltage signal, the aluminum element in the power supply line is charged to a negative potential, so that the aluminum does not generate a reduction reaction, but hydrogen ions in water vapor entering the power supply line generate a reduction reaction to generate gas (hydrogen), and the gas is generated between the aluminum Al in the power supply line and the interface of the aluminum oxide protective film, so that the aluminum oxide protective film is broken.
It can be seen from the corrosion mechanism that, in the case where moisture cannot be isolated, Al element in the power supply line is at a low potential for a long time, and moisture thereon is easily subjected to a reduction reaction, so that the protective film of the power supply line is broken, resulting in corrosion of the power supply line.
In this embodiment, the first signal input terminal of the driving control circuit in the display panel is the low-potential power terminal. The power supply line transmits a first non-constant voltage signal with switched positive and negative polarities, the input control circuit converts the first non-constant voltage signal into a negative output voltage signal smaller than 0V and transmits the negative output voltage signal to the first signal input end, and in other embodiments, the negative output voltage signal can be selected to be smaller than or equal to 0V. Therefore, the voltage signal of the first power supply line is not in a negative voltage state for a long time, but the first non-constant voltage signal is switched between positive and negative, so that hydrogen ions in water vapor entering the power supply line do not have sufficient reduction reaction time, reduction reaction cannot occur, gas cannot be generated, an aluminum oxide protective film of the power supply line is protected, the risk of cracking of the aluminum oxide protective film is reduced, the power supply line is prevented from being corroded, and the service life of the display panel is prolonged.
In the display panel, the first signal input terminal of the driving control circuit may be a high potential power supply terminal. The power supply line transmits a first non-constant voltage signal with positive and negative polarity switching, and the input control circuit converts the first non-constant voltage signal into a positive output voltage signal larger than 0V and transmits the positive output voltage signal to the first signal input end. The first non-constant voltage signal transmitted by the first power supply line is switched between positive and negative, so that parasitic capacitance between the first power supply line and other electrodes or signal lines can be weakened, signal transmission pressure difference is reduced, and signal transmission precision is improved.
The first non-constant voltage signal transmitted by the selectable first supply lines includes a first low voltage signal VGL1 less than 0V and a first high voltage signal VGH1 greater than 0V; the first signal input end is a low-potential power supply end, and the output voltage signal is VGL1 or-VGH 1; or, the first signal input terminal is a high-potential power supply terminal, and the output voltage signal is-VGL 1 or VGH 1.
The first non-constant voltage signal transmitted by the first supply line may be a voltage signal containing two different levels, for example, the first non-constant voltage signal includes a first low voltage signal VGL1 less than 0V and a first high voltage signal VGH1 greater than 0V, i.e., the first non-constant voltage signal transitions between VGL1 and VGH 1. In other embodiments, it is also optional that the first non-constant voltage signal transmitted by the first power supply line can be an alternating current signal.
The first signal input terminal is a low-potential power terminal, and if the first non-constant voltage signal is a first low-voltage signal VGL1 smaller than 0V, the VGL1 is directly output to the first signal input terminal; if the first non-constant voltage signal is the first high voltage signal VGH1 greater than 0V, the inverted signal is generated as-VGH 1, and then output to the first signal input terminal.
If the first non-constant voltage signal is a first low voltage signal VGL1 smaller than 0V, the first non-constant voltage signal is inverted to generate-VGL 1, and the inverted-VGL 1 is output to the first signal input end; if the first non-constant voltage signal is the first high voltage signal VGH1 greater than 0V, then VGH1 is directly output to the first signal input terminal.
The magnitude of the first low voltage signal VGL1 and the magnitude of the first high voltage signal VGH1 of the selectable first non-constant voltage signals are equal. For example VGL1 is-5V and VGH1 is 5V; alternatively, VGL1 was-1.8V and VGH1 was 1.8V. Not limited thereto. The related practitioner can reasonably design the amplitude of the first low voltage signal VGL1 and the amplitude of the first high voltage signal VGH1 in the first non-constant voltage signal according to the product requirement, and the amplitudes may be equal or different.
Fig. 2 is a schematic view of another array substrate according to an embodiment of the present invention. As shown in fig. 2, the input control circuit 200 includes a first switching unit 210 and a second switching unit 220; the input terminal IN1 and the control terminal CK1 of the first switching unit 210 are respectively connected to a first power line S1, and the output terminal OUT1 of the first switching unit 210 is connected to a first signal output terminal OUT; the input terminal IN2 and the control terminal CK2 of the second switching unit 220 are respectively connected to the first power line S1, and the output terminal OUT2 of the second switching unit 220 is connected to the first signal output terminal OUT; the first power supplying line S1 controls the first switching unit 210 and the second switching unit 220 to be turned on in time-sharing, the first switching unit 210 converts the first non-constant voltage signal into the first output voltage signal in a turned-on state, and the second switching unit 220 converts the first non-constant voltage signal into the first output voltage signal in a turned-on state.
In this embodiment, the operation phase of the input control circuit 200 includes a first output phase and a second output phase that are cyclically and alternately operated, and if the polarities of the first non-constant voltage signals in the first output phase and the second output phase are different, the first switch unit 210 is turned on in the first output phase and the second switch unit 220 is turned on in the second output phase. The voltage signals output by the two switching units are voltage signals of the polarity required by the first signal input terminal IN, and are both positive voltages or both negative voltages, for example.
In the first output stage, the first power supplying line S1 outputs a first polarity voltage signal, which can control the first switch unit 210 to be turned on, so that the first non-constant voltage signal enters the first switch unit 210 and is converted into a first output voltage signal, and then is transmitted to the first signal output terminal OUT.
In the second output stage, when the first power supplying line S1 outputs the second polarity voltage signal, the second switch unit 220 can be controlled to be turned on, and the first non-constant voltage signal enters the second switch unit 220 and is converted into the first output voltage signal, and then is transmitted to the first signal output terminal OUT.
It should be noted that the first polarity voltage signal is a positive voltage, and the second polarity voltage signal is a negative voltage; alternatively, the first polarity voltage signal is a negative voltage, and the second polarity voltage signal is a positive voltage. The first output voltage signals of the two output stages have the same polarity and the same or different amplitudes. The polarity of the first output voltage signal is fixed, but the amplitude may vary at different output stages.
The first non-constant voltage signal transmitted by the optional first supply line S1 includes a first low voltage signal VGL1 that is less than 0V and a first high voltage signal VGH1 that is greater than 0V. If the first signal input terminal IN is the low voltage power terminal, the first output voltage signal is VGL1 or-VGH 1, and the amplitudes of the two may be the same or different. Alternatively, if the first signal input terminal IN is a high voltage power terminal, the first output voltage signal is-VGL 1 or VGH1, and the amplitudes of the two may be the same or different.
The input control circuit 200 receives the first non-constant voltage signal transmitted by the first power supplying line S1, and transmits the first output voltage signal to the first signal input terminal IN at different operation stages. The voltage signal transmitted by the first power supplying line S1 is switched between positive and negative, and the first power supplying line S1 does not transmit a unipolar voltage signal for a long time. Therefore, parasitic capacitance between the first power supply line S1 and other signal lines or structures can be weakened, signal transmission precision is improved, influence on the performance of the array substrate is reduced, and display effect is improved.
Fig. 3 is a schematic view of another array substrate according to an embodiment of the present invention. As shown in fig. 3, the optional first switching unit 210 includes a first transistor M1, an input terminal and a control terminal of the first transistor M1 are respectively connected to a first power supplying line S1, and an output terminal of the first transistor M1 is connected to a first signal output terminal OUT; the second switching unit 220 includes a second transistor M2 and a first inverter U1, an input terminal and a control terminal of the second transistor M2 are connected to a first power supplying line S1, respectively, an output terminal of the second transistor M2 is connected to an input terminal of the first inverter U1, and an output terminal of the first inverter U1 is connected to a first signal output terminal OUT; the first transistor M1 and the second transistor M2 are each one of NMOS and PMOS and are different from each other. The first signal input terminal IN is selected to be a low voltage power terminal, the first transistor M1 is PMOS and the second transistor M2 is NMOS.
IN this embodiment, the first signal input terminal IN can be selected as a low-potential power terminal, and the first output voltage signal received by the first signal input terminal IN at any stage is a negative voltage.
When the first non-constant voltage signal output by the first power line S1 is a low level signal, the first switch unit 210 is turned on and the second switch unit 220 is turned off, so that the low level signal IN the first non-constant voltage signal enters the first signal output terminal OUT through the turned-on first transistor M1 and is transmitted to the first signal input terminal IN. The first signal input terminal IN receives a negative first output voltage signal.
When the first non-constant voltage signal output by the first power line S1 is a high level signal, the first switch unit 210 is turned off and the second switch unit 220 is turned on, so that the high level signal IN the first non-constant voltage signal enters the input terminal of the first inverter U1 through the turned-on second transistor M2, is inverted by the first inverter U1 and is output as a low level signal, and the negative first output voltage signal is transmitted to the first signal input terminal IN. The first signal input terminal IN receives a negative first output voltage signal.
In other embodiments, the first signal input terminal may be a high voltage power terminal, the first transistor may be an NMOS and the second transistor may be a PMOS. Fig. 4 is a schematic view of another array substrate according to an embodiment of the present invention. As shown IN fig. 4, the first signal input terminal IN can be selected as the high voltage power terminal, and the first output voltage signal received by the first signal input terminal IN is always positive voltage.
When the first non-constant voltage signal output by the first power line S1 is a high level signal, the first switch unit 210 is turned on and the second switch unit 220 is turned off, so that the high level signal IN the first non-constant voltage signal enters the first signal output terminal OUT through the turned-on first transistor M1 and is transmitted to the first signal input terminal IN. The first signal input IN receives a positive first output voltage signal.
When the first non-constant voltage signal output by the first power supply line S1 is a low level signal, the first switch unit 210 is turned off and the second switch unit 220 is turned on, so that the low level signal IN the first non-constant voltage signal enters the input terminal of the first inverter U1 through the turned-on second transistor M2, is inverted by the first inverter U1 and is output as a high level signal, and the positive first output voltage signal is transmitted to the first signal input terminal IN. The first signal input IN receives a positive first output voltage signal.
It should be noted that, in the first non-constant voltage signal, the NMOS transistor needs to be turned on by a high-level signal, and the PMOS transistor needs to be turned on by a low-level signal, and the specific voltage amplitude is not limited.
As described above, the input control circuit has a simple structure, and can convert the first non-constant voltage signal supplied from the first power supply line and having positive and negative switching into the first output voltage signal having a constant polarity and transmit the first output voltage signal to the first signal input terminal of the drive control circuit. The drive control circuit normally implements pixel drive.
Fig. 5 is a schematic view of another array substrate according to an embodiment of the present invention. As shown in fig. 5, the optional array substrate further includes: a second power supply line S2, the second power supply line S2 for transmitting a second non-constant voltage signal; the output voltage signal comprises a first output voltage signal and a second output voltage signal; the first supply line S1 transmits the first output voltage signal to the first signal output terminal OUT through the input control circuit 200, the second supply line S2 transmits the second output voltage signal to the first signal output terminal OUT through the input control circuit 200, and both the first output voltage signal and the second output voltage signal are positive voltage or negative voltage.
In this embodiment, the first power supplying line S1 is used to transmit a first non-constant voltage signal, the second power supplying line S2 is used to transmit a second non-constant voltage signal, the first non-constant voltage signal is switched between positive and negative voltages, and the second non-constant voltage signal is switched between positive and negative voltages.
Assuming that the first signal input terminal IN is a low potential power source terminal, the input control circuit 200 may convert the first non-constant voltage signal into a negative first output voltage signal or convert the second non-constant voltage signal into a negative second output voltage signal to provide the negative voltage signal to the first signal input terminal IN. Assuming that the first signal input terminal IN is a high potential power source terminal, the input control circuit 200 may convert the first non-constant voltage signal into a positive first output voltage signal or convert the second non-constant voltage signal into a positive second output voltage signal to provide the positive voltage signal to the first signal input terminal IN. It is understood that the first output voltage signal and the second output voltage signal may be the same or different in magnitude.
The first signal input end IN can be selected as a low-potential power end, and the negative first output voltage signal and the negative second output voltage signal are transmitted to the first signal output end IN a time-sharing manner; or, the first signal input terminal IN is a high-potential power terminal, and the positive first output voltage signal and the positive second output voltage signal are transmitted to the first signal output terminal IN a time-sharing manner.
When the first signal input terminal IN is the low-potential power supply terminal, and the first signal input terminal IN needs to continuously receive the negative voltage signal, the input control circuit 200 may convert the first non-constant voltage signal into a negative first output voltage signal IN the first output stage, so as to provide the negative voltage signal to the first signal input terminal IN; IN a second output phase, the second non-constant voltage signal is converted into a negative second output voltage signal to provide a negative voltage signal to the first signal input terminal IN. The operation phase of the input control circuit 200 is cyclically alternated between the first output phase and the second output phase.
Similarly, when the first signal input terminal IN is the high voltage power terminal, the input control circuit 200 may transmit the positive first output voltage signal or the positive second output voltage signal to the first signal input terminal IN a time-sharing manner. The first signal input terminal IN may continuously receive the negative voltage signal to implement the driving of the driving control circuit 100.
The selectable first non-constant voltage signals include a first low voltage signal VGL1 less than 0V and a first high voltage signal VGH1 greater than 0V; the second non-constant voltage signal includes a second low voltage signal VGL2 that is less than 0V and a second high voltage signal VGH2 that is greater than 0V. The first signal input terminal IN can be selected as a low-potential power supply terminal, the first output voltage signal is VGL1, and the second output voltage signal is VGL 2; alternatively, the first signal input terminal IN is a high voltage power terminal, the first output voltage signal is VGH1, and the second output voltage signal is VGH 2. The magnitude of the first low voltage signal VGL1 in the selectable first non-constant voltage signal and the magnitude of the second low voltage signal VGL2 in the second non-constant voltage signal are equal; the magnitude of the first high voltage signal VGH1 in the first non-constant voltage signal and the magnitude of the second high voltage signal VGH2 in the second non-constant voltage signal are equal.
The first non-constant voltage signal may be a voltage signal including two levels, negative VGL1 and positive VGH1, respectively; the second non-constant voltage signal may be a voltage signal including two levels, negative VGL2 and positive VGH2, respectively. In other embodiments, the first non-constant voltage signal and the second non-constant voltage signal may also be selected to be alternating current signals that switch between positive and negative polarities.
The first and second non-constant voltage signals are switched between positive and negative polarities, so that the first and second power supply lines S1 and S2 do not operate at a low level for a long time, and corrosion of the power supply lines can be prevented.
Fig. 6 is a schematic diagram of a power supply signal according to an embodiment of the present invention. As shown in fig. 6, the first signal input terminal may be selected as a low-potential power terminal; at least a partial period of the output period of the first low voltage signal VGL1 overlaps with the output period of the second high voltage signal VGH 2; at least a partial period of the output period of the second low voltage signal VGL2 overlaps with the output period of the first high voltage signal VGH 1.
In the present embodiment, the first non-constant voltage signal transmitted by the first power supplying line S1 includes a first low voltage signal VGL1 less than 0V and a first high voltage signal VGH1 greater than 0V, and the second non-constant voltage signal transmitted by the second power supplying line S2 includes a second low voltage signal VGL2 less than 0V and a second high voltage signal VGH2 greater than 0V.
The first signal input terminal IN is a low potential power terminal. If the first signal input terminal IN receives the first output voltage signal, it is VGL 1. Namely, VGL1 IN the first non-constant voltage signal of the first power line is input to the first signal input terminal IN, at this time, the output time period of the first low voltage signal VGL1 covers the output time period of the second high voltage signal VGH2, and the second high voltage signal VGH2 of the second power line S2 is not output to the first signal input terminal, thereby ensuring the normal operation of the driving control circuit.
If the first signal input terminal IN receives the second output voltage signal, it is VGL 2. Namely, VGL2 IN the second non-constant voltage signal of the second power line is input to the first signal input terminal IN, at this time, the output time period of the second low voltage signal VGL2 covers the output time period of the first high voltage signal VGH1, and the first high voltage signal VGH1 of the first power line S1 is not output to the first signal input terminal, thereby ensuring the normal operation of the driving control circuit.
Referring to fig. 7, a schematic diagram of another power supply signal provided in the embodiment of the present invention is shown. As shown IN fig. 7, the first signal input terminal IN can be selected as a high-potential power terminal; at least a partial period of the output period of the first high voltage signal VGH1 overlaps with the output period of the second low voltage signal VGL 2; at least a partial period of the output period of the second high voltage signal VGH2 overlaps with the output period of the first low voltage signal VGL 1.
In the present embodiment, the first non-constant voltage signal transmitted by the first power supplying line S1 includes a first low voltage signal VGL1 less than 0V and a first high voltage signal VGH1 greater than 0V, and the second non-constant voltage signal transmitted by the second power supplying line S2 includes a second low voltage signal VGL2 less than 0V and a second high voltage signal VGH2 greater than 0V.
The first signal input terminal IN is a high voltage power supply terminal. If the first signal input terminal IN receives the first output voltage signal, it is VGH 1. Namely, VGH1 IN the first non-constant voltage signal of the first power supply line is input to the first signal input terminal IN, at this time, the output time period of the first high voltage signal VGH1 covers the output time period of the second low voltage signal VGL2, and the second low voltage signal VGL2 of the second power supply line S2 is not output to the first signal input terminal, thereby ensuring the normal operation of the driving control circuit.
If the first signal input terminal IN receives the second output voltage signal, it is VGH 2. Namely, VGH2 IN the second non-constant voltage signal of the second power supply line is input to the first signal input terminal IN, at this time, the output time period of the second high voltage signal VGH2 covers the output time period of the first low voltage signal VGL1, and the first low voltage signal VGL1 of the first power supply line S1 is not output to the first signal input terminal, thereby ensuring the normal operation of the driving control circuit.
In other embodiments, the output period of the first low voltage signal VGL1 may also be selected to overlap with the output period of the second high voltage signal VGH 2; the output period of the second low voltage signal VGL2 overlaps with the output period of the first high voltage signal VGH 1.
Fig. 8 is a schematic view of another array substrate according to an embodiment of the present invention. As shown in fig. 8, the optional input control circuit 200 includes a first switching unit 210 and a second switching unit 220; the input terminal IN1 and the control terminal CK1 of the first switching unit 210 are respectively connected to a first power line S1, and the output terminal OUT1 of the first switching unit 210 is connected to a first signal output terminal OUT; the input terminal IN2 and the control terminal CK2 of the second switching unit 220 are connected to a second power supply line S2, respectively, and the output terminal OUT2 of the second switching unit 220 is connected to the first signal output terminal OUT; the first and second power supplying lines S1 and S2 control the first and second switching units 210 and 220 to be turned on in time division, the first switching unit 210 converts the first non-constant voltage signal into a first output voltage signal in a turned-on state, and the second switching unit 220 converts the second non-constant voltage signal into a second output voltage signal in a turned-on state.
In this embodiment, the first power supplying line S1 controls whether the first switch unit 210 is turned on or not, and when the first switch unit 210 is turned on, the first non-constant voltage signal is converted into the first output voltage signal and transmitted to the first signal output terminal OUT. The second power supplying line S2 controls whether the second switching unit 220 is turned on or not, and when the second switching unit 220 is turned on, the second non-constant voltage signal is converted into a second output voltage signal and transmitted to the first signal output terminal OUT.
The first and second power supplying lines S1 and S2 control the first and second switching units 210 and 220 to be turned on in a time-sharing manner, i.e., the first power supplying line S1 controls the first switching unit 210 to be turned on and the second power supplying line S2 controls the second switching unit 220 to be turned off in a previous output stage; in the latter output phase, the first power supplying line S1 controls the first switching unit 210 to be turned off and the second power supplying line S2 controls the second switching unit 220 to be turned on. Thus, the first non-constant voltage signal can be converted into the first output voltage signal IN a time-sharing manner and provided to the first signal input terminal IN of the driving control circuit 100; alternatively, the second non-constant voltage signal is converted into a second output voltage signal and supplied to the first signal input terminal IN of the drive control circuit 100.
Fig. 9 is a schematic view of another array substrate according to an embodiment of the invention. As shown in fig. 9, the optional first switch unit 210 includes a third transistor M3, the input terminal and the control terminal of the third transistor M3 are respectively connected to the first power supplying line S1, and the output terminal of the third transistor M3 is connected to the first signal output terminal OUT; the second switching unit 220 includes a fourth transistor M4, an input terminal and a control terminal of the fourth transistor M4 are respectively connected to the second power supplying line S2, and an output terminal of the fourth transistor M4 is connected to the first signal output terminal OUT; the third transistor M3 and the fourth transistor M4 are both NMOS or both PMOS.
The first signal input terminal IN may be selected as a low voltage power terminal, and the third transistor M3 and the fourth transistor M4 may be both PMOS transistors.
In this embodiment, the first power supplying line S1 controls the third transistor M3 to be turned on or off, and the second power supplying line S2 controls the fourth transistor M4 to be turned on or off.
When the first signal input terminal IN is the low potential power terminal, the first signal output terminal OUT outputs a negative voltage signal. The first non-constant voltage signal transmitted by the first power supplying line S1 is a low level signal, which can control the third transistor M3 to be turned on, and then the low level signal is transmitted to the first signal output terminal OUT, and the second non-constant voltage signal transmitted by the second power supplying line S2 is a high level signal to control the fourth transistor M4 to be turned off. When the second non-constant voltage signal transmitted by the second power supplying line S2 is a low level signal, the fourth transistor M4 can be controlled to be turned on, and the low level signal is transmitted to the first signal output terminal OUT, and at this time, the first non-constant voltage signal transmitted by the first power supplying line S1 is a high level signal to control the third transistor M3 to be turned off.
It can be appreciated that the first non-constant voltage signal transmitted by the first power supply line S1 and the second non-constant voltage signal transmitted by the second power supply line S2 are in opposite timing. The output voltage signals with the same polarity can be provided to the first signal input end in a time-sharing mode.
In other embodiments, the first signal input terminal may be a high voltage power terminal, and the third transistor and the fourth transistor are both NMOS. The first non-constant voltage signal transmitted by the first power supplying line is a high level signal and can control the third transistor to be turned on, and the second non-constant voltage signal transmitted by the second power supplying line is a low level signal and can control the fourth transistor M4 to be turned off. Similarly, the fourth transistor M4 can be controlled to be turned on when the second non-constant voltage signal transmitted by the second power supplying line S2 is a high level signal, and the first non-constant voltage signal transmitted by the first power supplying line S1 is a low level signal to control the third transistor M3 to be turned off.
Fig. 10 is a schematic view of another array substrate according to an embodiment of the present invention. As shown in fig. 10, the optional drive control circuit 100 includes a multi-stage shift register 110, the shift register 110 including a first signal input terminal INi; the first power supply line S1 is electrically connected to each first signal input terminal INi through the input control circuit 200.
In this embodiment, the driving control circuit 100 includes a plurality of stages of shift registers 110, and the shift registers 110 are used for providing scanning driving signals for the pixels of the display area, and in other embodiments, the shift registers are further selected to provide light emitting driving signals for the pixels of the display area.
The shift register 110 includes a first signal input terminal INi, and the selectable driving control circuit 100 IN this embodiment includes n stages of shift registers 110, where the first signal input terminals of the n stages of shift registers 110 are sequentially labeled as IN1, IN2, …, INn. The first supply line S1 provides an output voltage signal to each first signal input terminal INi through the input control circuit 200.
One time sequence driving period of the selectable array substrate comprises S frames of refreshing pictures, wherein S is more than 0; the S frame refresh picture includes a voltage signal write frame, at least a portion of a time period of the voltage signal write frame multiplexed as an output time period of the first non-constant voltage signal.
In this embodiment, in the S-frame refresh frames, one frame is multiplexed into a voltage signal write frame, the first power supplying line supplies the first non-constant voltage signal during at least a part of the time period of the voltage signal write frame, and the first power supplying line can directly supply the voltage signal with the polarity required by the first signal input terminal during other time periods. Therefore, the level switching frequency of the signal transmitted by the first power supply line is reduced, and the power consumption of the display panel is reduced.
The selectable display panel also comprises a second power supply line, and the second power supply line and the first power supply line supply the output voltage signal to the first signal input end in a time sharing mode.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, where the display device provided in this embodiment includes the array substrate according to any of the above embodiments. The display device may be selected to be an organic light emitting display device.
The selectable display device comprises a bending area and a non-bending area, wherein the non-bending area is provided with an isolation protection layer. The isolation protective layer is mainly used for isolating water vapor. The bending radius of the bending area is too large, and the isolation protection layer cannot bear the bending radius of the bending area, so that the isolation protection layer is not arranged in the bending area. Under the condition that water vapor can not be isolated, metal elements in the power supply line are at a low potential for a long time, and water vapor on the metal elements is easy to generate reduction reaction, so that a protective film of the power supply line is broken, and the power supply line is corroded.
In this embodiment, the power supply line of the array substrate is configured to transmit the voltage signal with the switched polarity to prevent the power supply line from being at a low potential for a long time, and the metal element, especially aluminum, in the power supply line does not have sufficient reduction reaction time with the moisture, thereby preventing the protection film from being damaged due to corrosion of the moisture. In addition, the signal provided by the power supply line to the input control circuit in the display panel is a non-constant voltage signal, and the switching between the positive and negative is performed, so that the parasitic capacitance between the first power supply line and other signal lines or structures can be weakened, the signal transmission precision is improved, the influence on the performance of the array substrate is reduced, and the display effect is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (17)
1. An array substrate, comprising:
the input control circuit comprises a first signal output end, and the first signal input end is electrically connected with the first signal output end;
a first supply line for transmitting a first non-constant voltage signal; transmitting an output voltage signal to the first signal output terminal through the input control circuit, the output voltage signal being maintained as a positive voltage or maintained as a negative voltage;
the first non-constant voltage signal transmitted by the first supply line includes a first low voltage signal VGL1 less than 0V and a first high voltage signal VGH1 greater than 0V; the first signal input end is a low-potential power supply end, and the output voltage signal is VGL1 or-VGH 1; or, the first signal input end is a high-potential power supply end, and the output voltage signal is-VGL 1 or VGH 1;
and/or the presence of a gas in the gas,
the input control circuit comprises a first switch unit and a second switch unit; the input end and the control end of the first switch unit are respectively connected to the first power supply line, and the output end of the first switch unit is connected to the first signal output end; the input end and the control end of the second switch unit are respectively connected to the first power supply line, and the output end of the second switch unit is connected to the first signal output end; the first power line controls the first switch unit and the second switch unit to be conducted in a time-sharing manner, the first switch unit converts the first non-constant voltage signal into a first output voltage signal in a conducting state, and the second switch unit converts the first non-constant voltage signal into the first output voltage signal in the conducting state;
and/or the presence of a gas in the gas,
a second supply line for transmitting a second non-constant voltage signal; the output voltage signal comprises a first output voltage signal and a second output voltage signal; the first power supply line transmits the first output voltage signal to the first signal output end through the input control circuit, the second power supply line transmits the second output voltage signal to the first signal output end through the input control circuit, and the first output voltage signal and the second output voltage signal are both positive voltage or negative voltage;
and/or the presence of a gas in the gas,
the drive control circuit comprises a multi-stage shift register, and the shift register comprises a first signal input end; the first power supply line is electrically connected with each first signal input end through the input control circuit;
and/or the presence of a gas in the atmosphere,
one time sequence driving period of the array substrate comprises S frames of refreshing pictures, wherein S is more than 0; the S-frame refresh picture includes a voltage signal write frame, at least a portion of a time period of the voltage signal write frame being multiplexed as an output time period of the first non-constant voltage signal.
2. The array substrate of claim 1, wherein the first signal input terminal is a low-potential power terminal, and the output voltage signal is less than 0V; or,
the first signal input end is a high-potential power supply end, and the output voltage signal is greater than 0V.
3. The array substrate of claim 1, wherein the first non-constant voltage signal transmitted by the first supply line comprises a first low voltage signal VGL1 less than 0V and a first high voltage signal VGH1 greater than 0V;
the first signal input end is a low-potential power supply end, and the output voltage signal is VGL1 or-VGH 1; or,
the first signal input end is a high-potential power supply end, and the output voltage signal is-VGL 1 or VGH 1;
the first low voltage signal VGL1 and the first high voltage signal VGH1 of the first non-constant voltage signals have equal amplitudes.
4. The array substrate of claim 1, wherein the input control circuit comprises a first switch unit and a second switch unit;
the input end and the control end of the first switch unit are respectively connected to the first power supply line, and the output end of the first switch unit is connected to the first signal output end;
the input end and the control end of the second switch unit are respectively connected to the first power supply line, and the output end of the second switch unit is connected to the first signal output end;
the first power line controls the first switch unit and the second switch unit to be conducted in a time-sharing manner, the first switch unit converts the first non-constant voltage signal into a first output voltage signal in a conducting state, and the second switch unit converts the first non-constant voltage signal into the first output voltage signal in the conducting state;
the first switching unit comprises a first transistor, an input end and a control end of the first transistor are respectively connected to the first power supply line, and an output end of the first transistor is connected to the first signal output end;
the second switch unit comprises a second transistor and a first phase inverter, wherein the input end and the control end of the second transistor are respectively connected to the first power supply line, the output end of the second transistor is connected to the input end of the first phase inverter, and the output end of the first phase inverter is connected to the first signal output end;
the first transistor and the second transistor are respectively one of NMOS and PMOS and are different from each other.
5. The array substrate of claim 4, wherein the first signal input terminal is a high voltage power terminal, the first transistor is NMOS and the second transistor is PMOS; or,
the first signal input end is a low-potential power supply end, the first transistor is a PMOS, and the second transistor is an NMOS.
6. The array substrate of claim 1, further comprising: a second supply line for transmitting a second non-constant voltage signal;
the output voltage signal comprises a first output voltage signal and a second output voltage signal;
the first power supply line transmits the first output voltage signal to the first signal output end through the input control circuit, the second power supply line transmits the second output voltage signal to the first signal output end through the input control circuit, and the first output voltage signal and the second output voltage signal are both positive voltage or negative voltage;
the first signal input end is a low-potential power supply end, and a negative first output voltage signal and a negative second output voltage signal are transmitted to the first signal output end in a time-sharing manner; or,
the first signal input end is a high-potential power end, and a positive first output voltage signal and a positive second output voltage signal are transmitted to the first signal output end in a time-sharing mode.
7. The array substrate of claim 1, further comprising: a second supply line for transmitting a second non-constant voltage signal;
the output voltage signal comprises a first output voltage signal and a second output voltage signal;
the first power supply line transmits the first output voltage signal to the first signal output end through the input control circuit, the second power supply line transmits the second output voltage signal to the first signal output end through the input control circuit, and the first output voltage signal and the second output voltage signal are both positive voltage or negative voltage;
the first non-constant voltage signal includes a first low voltage signal VGL1 less than 0V and a first high voltage signal VGH1 greater than 0V;
the second non-constant voltage signal includes a second low voltage signal VGL2 less than 0V and a second high voltage signal VGH2 greater than 0V.
8. The array substrate of claim 7, wherein the first signal input terminal is a low potential power terminal, the first output voltage signal is VGL1, the second output voltage signal is VGL 2; or,
the first signal input terminal is a high-potential power supply terminal, the first output voltage signal is VGH1, and the second output voltage signal is VGH 2.
9. The array substrate of claim 7, wherein the first non-constant voltage signal VGL1 has an amplitude equal to the second non-constant voltage signal VGL 2;
the magnitude of the first high voltage signal VGH1 in the first non-constant voltage signal and the magnitude of the second high voltage signal VGH2 in the second non-constant voltage signal are equal.
10. The array substrate of claim 7, wherein the first signal input terminal is a low-potential power terminal;
at least a partial period of the output period of the first low voltage signal VGL1 overlaps with the output period of the second high voltage signal VGH 2;
at least a partial period of the output period of the second low voltage signal VGL2 overlaps with the output period of the first high voltage signal VGH 1.
11. The array substrate of claim 7, wherein the first signal input terminal is a high potential power terminal;
at least a partial period of the output period of the first high voltage signal VGH1 overlaps with the output period of the second low voltage signal VGL 2;
at least a partial period of the output period of the second high voltage signal VGH2 overlaps with the output period of the first low voltage signal VGL 1.
12. The array substrate of claim 10 or 11, wherein an output period of the first low voltage signal VGL1 overlaps with an output period of the second high voltage signal VGH 2;
an output period of the second low voltage signal VGL2 overlaps with an output period of the first high voltage signal VGH 1.
13. The array substrate of claim 1, further comprising: a second supply line for transmitting a second non-constant voltage signal;
the output voltage signal comprises a first output voltage signal and a second output voltage signal;
the first power supply line transmits the first output voltage signal to the first signal output end through the input control circuit, the second power supply line transmits the second output voltage signal to the first signal output end through the input control circuit, and the first output voltage signal and the second output voltage signal are both positive voltage or negative voltage;
the input control circuit comprises a first switch unit and a second switch unit;
the input end and the control end of the first switch unit are respectively connected to the first power supply line, and the output end of the first switch unit is connected to the first signal output end;
the input end and the control end of the second switch unit are respectively connected to the second power supply line, and the output end of the second switch unit is connected to the first signal output end;
the first power supply line and the second power supply line control the first switching unit and the second switching unit to be turned on in a time-sharing manner, the first switching unit converts the first non-constant voltage signal into the first output voltage signal in a turned-on state, and the second switching unit converts the second non-constant voltage signal into the second output voltage signal in a turned-on state.
14. The array substrate of claim 13,
the first switching unit includes a third transistor, an input terminal and a control terminal of which are connected to the first power supply line, respectively, and an output terminal of which is connected to the first signal output terminal;
the second switching unit comprises a fourth transistor, an input end and a control end of the fourth transistor are respectively connected to the second power supply line, and an output end of the fourth transistor is connected to the first signal output end;
the third transistor and the fourth transistor are both NMOS or PMOS.
15. The array substrate of claim 14, wherein the first signal input terminal is a high potential power terminal, and the third transistor and the fourth transistor are both NMOS; or,
the first signal input end is a low-potential power supply end, and the third transistor and the fourth transistor are both PMOS transistors.
16. A display device comprising the array substrate according to any one of claims 1 to 15.
17. The display device according to claim 16, wherein the display device comprises a bending region and a non-bending region, and the non-bending region is formed with an isolation protection layer.
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| US4830467A (en) * | 1986-02-12 | 1989-05-16 | Canon Kabushiki Kaisha | A driving signal generating unit having first and second voltage generators for selectively outputting a first voltage signal and a second voltage signal |
| JPH10142575A (en) * | 1996-11-07 | 1998-05-29 | Citizen Watch Co Ltd | Display device drive circuit |
| JP4453475B2 (en) * | 2004-08-05 | 2010-04-21 | ソニー株式会社 | Level conversion circuit, power supply voltage generation circuit, and display device |
| JP5074223B2 (en) * | 2008-02-06 | 2012-11-14 | ルネサスエレクトロニクス株式会社 | Level shift circuit and driver and display device using the same |
| KR102231774B1 (en) * | 2014-09-24 | 2021-03-25 | 삼성디스플레이 주식회사 | Display device compensating variation of power supply voltage |
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