CN113409872B - Method and device for inhibiting flash over-erasure, electronic equipment and storage medium - Google Patents
Method and device for inhibiting flash over-erasure, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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Abstract
The invention discloses a method, a device, electronic equipment and a storage medium for inhibiting flash over-erasure, wherein the method comprises the following steps: when the data reading or checking operation is carried out on the selected storage units with the over-erasing problem in the chip, negative pressure is applied to Bulk ends of the selected storage units and/or negative pressure is applied to word line ends of unselected storage units on the same bit line and/or positive pressure is applied to source ends of the selected storage units; the method provides three basic processing modes of negative pressure application to Bulk end of a selected memory cell, negative pressure application to word end of an unselected memory cell on the same bit line and positive pressure application to source end of the selected memory cell, so as to inhibit leakage behavior of over-erased memory cell during data reading and checking, further the erased memory cell can be normally used under the condition of no repair, and the three basic processing modes can be independently or randomly matched for use, thus having the characteristic of diversity.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method, an apparatus, an electronic device, and a storage medium for inhibiting over-erasure of a flash memory.
Background
When the Nor flash is in erasing operation, because of inconsistent erasing difficulty of the memory cells, over-erasing phenomenon is caused by that part of the memory cells are still erased after erasing is completed, the threshold voltage of the over-erased memory cells is extremely low, and in the process of reading data of the memory cells, under the condition of non-selection grid voltage (usually 0V), a plurality of cells have electric leakage, so that the problem that correct data cannot be read on a word line is caused, and in particular, the uncertainty of the threshold voltage is increased after a plurality of erasing cycles.
Therefore, in order to save these over-erased memory cells, in order to compromise the performance and reliability of the erase operation, the conventional nor flash generally adds over-erase checking and repairing processes at the end of the erase operation, which results in a relatively complex process of the erase operation algorithm and also sacrifices part of the data retention capability.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
An objective of the embodiments of the present application is to provide a method, an apparatus, an electronic device, and a storage medium for inhibiting over-erasure of a flash memory, so as to inhibit leakage behavior of an over-erased storage unit in a reading process, and further enable the erased storage unit to be normally used without repairing.
In a first aspect, an embodiment of the present application provides a method for inhibiting over-erase of a Flash memory, configured to inhibit an over-erase phenomenon of a memory cell in a Nor Flash, where the method includes: when the data reading or checking operation is carried out on the selected memory cells with the over-erasing problem in the chip, negative pressure is applied to the Bulk end of the selected memory cells and/or negative pressure is applied to the word line ends of unselected memory cells on the same bit line and/or positive pressure is applied to the source end of the selected memory cells.
The method for inhibiting over-erasure of the flash memory comprises the step of applying negative pressure to Bulk ends of selected memory cells to be-0.75 to-0.25V.
The method for inhibiting over-erasure of the flash memory comprises the step of applying negative pressure to word line ends of unselected memory cells on the same bit line to be minus 0.75 to minus 0.25V.
The method for inhibiting over-erasure of the flash memory comprises the step of applying positive pressure to a source end of a selected storage unit to be 0.25-0.75V.
When negative pressure is applied to the Bulk end of a selected memory cell, negative pressure is applied to the word line end of an unselected memory cell on the same bit line, positive pressure is applied to the source end of the selected memory cell, the voltage value of the negative pressure applied to the Bulk end of the selected memory cell is equal to the voltage value of the negative pressure applied to the word line end of the unselected memory cell on the same bit line, and the absolute value of the negative pressure applied to the word line end of the unselected memory cell on the same bit line is equal to the absolute value of the positive pressure applied to the source end of the selected memory cell.
In the method for inhibiting over-erasure of flash memory, after negative pressure is applied to Bulk end of a selected memory cell and/or negative pressure is applied to word end of an unselected memory cell on the same bit line and/or positive pressure is applied to source end of the selected memory cell, gate trigger voltage of the memory cell with over-erasure problem is lower than or equal to 0V.
In a second aspect, an embodiment of the present application further provides an apparatus for inhibiting over-erase of a Flash memory, where the apparatus is configured to inhibit an over-erase phenomenon of a memory cell in a Nor Flash, including:
the acquisition module is used for reading or checking the data of the storage unit in the chip;
the voltage operation module is used for applying voltage to the end line of the memory cell in the chip;
the voltage operation module can apply negative pressure to the Bulk end of the selected storage unit and/or negative pressure to the word line end of the unselected storage unit on the same bit line and/or positive pressure to the source end of the selected storage unit when the acquisition module performs data reading or checking operation on the selected storage unit with over-erasure problem in the chip.
The device for inhibiting over-erasure of flash memory comprises a voltage operation module, a first voltage module, a second voltage module and a third voltage module, wherein the voltage operation module comprises the first voltage module, the second voltage module and the third voltage module, and when the acquisition module performs reading or verifying data operation on a memory unit which is selected in a chip and has an over-erasure problem, the first voltage module, the second voltage module and the third voltage module simultaneously apply negative pressure to the Bulk end of the selected memory unit, apply negative pressure to the word line end of an unselected memory unit on the same bit line and apply positive pressure to the source end of the selected memory unit.
In a third aspect, embodiments of the present application also provide an electronic device comprising a processor and a memory storing computer readable instructions which, when executed by the processor, perform the steps of the method as provided in the first aspect above.
In a fourth aspect, embodiments of the present application also provide a storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method as provided in the first aspect above.
As can be seen from the foregoing, the method, the device, the electronic apparatus and the storage medium for inhibiting over-erasure of flash memory provided in the embodiments of the present application provide three basic processing methods, namely, applying negative pressure to Bulk end of a selected storage unit, applying negative pressure to word line end of an unselected storage unit on the same bit line, and applying positive pressure to source end of a selected storage unit, to inhibit leakage behavior of over-erased storage unit during data reading and checking, so that the erased storage unit can be normally used without repair, and the three basic processing methods can be used independently or in any combination, and have a diversity characteristic.
Drawings
Fig. 1 is a schematic diagram illustrating the use of some embodiments of a method for suppressing flash over-erase according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of some embodiments of an apparatus for suppressing flash over-erase according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of some embodiments of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, fig. 1 is a method for inhibiting over-erase of a Flash memory, for inhibiting over-erase of a memory cell in a Nor Flash, according to some embodiments of the present application, the method includes: when the data reading or checking operation is carried out on the selected memory cells with the over-erasing problem in the chip, negative pressure is applied to the Bulk end of the selected memory cells and/or negative pressure is applied to the word line ends of unselected memory cells on the same bit line and/or positive pressure is applied to the source end of the selected memory cells.
The over-erased memory cells cannot hold data because the threshold voltage is too low, resulting in a gate trigger voltage Vgt greater than 0, and thus leakage occurs during a read or verify data operation, resulting in a data read error.
Specifically, applying a negative pressure to the Bulk terminal of the selected memory cell, the effect of the change in the threshold voltage Vt due to the back-gate effect (the effect of the change in the threshold voltage Vt due to the substrate voltage, i.e., bulk voltage, being not 0 is referred to as the back-gate effect), will increase the threshold voltage Vt to the memory cell by a voltage corresponding to half the absolute value of the negative pressure, for example, the negative pressure applied to the Bulk terminal is-1V, and the corresponding memory cell will increase the threshold voltage Vt by about 0.5V due to the back-gate effect; on the basis, the threshold voltage rises, the corresponding gate trigger voltage Vgt drops by a corresponding magnitude, the over-erased memory cell applies negative voltage at the Bulk end to enable the threshold voltage Vt to rise and the gate trigger voltage Vgt to drop, and when the gate trigger voltage Vgt drops below 0V, the problem of memory cell leakage cannot occur when the data reading or checking operation is carried out at the moment, so that the data reading or checking operation can be ensured to be accurate; therefore, by adopting the method for inhibiting over-erasure of the flash memory, which is implemented by applying negative pressure to the Bulk end of the selected memory cell, the problem that the over-erased memory cell in the flash memory generates error data due to the leakage of the memory cell in data reading or checking data can be effectively inhibited, namely, the method for inhibiting over-erasure of the flash memory can still inhibit the leakage of the over-erased memory cell under the condition of not repairing the over-erased cell so as to ensure accurate data reading.
Specifically, negative pressure is applied to a Word Line (Word Line) end of an unselected memory cell on the same bit Line, so that corresponding negative pressure is applied to a source electrode of a memory cell which is connected with the memory cell and has an over-erasure problem on the same bit Line, so that a gate-source voltage Vgs (hereinafter referred to as gate-source voltage) of the selected memory cell which has the over-erasure problem becomes smaller, if-1V voltage is applied to a Word Line end of the unselected memory cell on the same bit Line, the gate-source voltage Vgs of the selected memory cell which is connected with the memory cell and has the over-erasure problem on the same bit Line is correspondingly reduced by 1V, and accordingly, the corresponding gate trigger voltage Vgs is reduced by 1V; negative pressure is applied to the word line end of the unselected memory cell on the same bit line of the over-erased memory cell, so that the gate trigger voltage Vgt of the over-erased memory cell is reduced, when the gate trigger voltage Vgt is reduced to be lower than 0V, the problem of electric leakage of the memory cell cannot occur when data reading or checking operation is performed at the moment, and further, the data reading or checking operation can be ensured to be correct data; therefore, by adopting the method for inhibiting flash over-erasure in the embodiment of the application, negative pressure is applied to the word line end of the unselected memory cells on the same bit line, the problem that the over-erased memory cells in the flash memory generate error data due to the leakage of the memory cells in data reading or checking data can be effectively inhibited, namely the method for inhibiting flash over-erasure in the embodiment of the application can still inhibit the leakage of the over-erased memory cells under the condition of not repairing the over-erased memory cells so as to ensure accurate data reading.
More specifically, vgt=vgs-Vt, and thus the gate trigger voltage Vgt coincides with the variation amount of the gate voltage Vgs without variation of the threshold voltage Vt.
Specifically, positive voltage is applied to the source end of the selected memory cell, because the voltage on the gate electrode of the selected memory cell is 0V, the gate voltage Vgs of the memory cell with over-erasure is reduced by the voltage value applied by the corresponding source end after the positive voltage is additionally applied to the source end of the memory cell, namely, when the positive 1V voltage is applied to the source end, the gate voltage Vgs of the memory cell correspondingly drops by 1V, so that the corresponding gate trigger voltage Vgt drops by 1V, the gate trigger voltage Vgt of the memory cell with over-erasure can be reduced by the positive voltage applied to the source end of the memory cell with over-erasure, and when the gate trigger voltage Vgt drops below 0V, the problem of electric leakage of the memory cell is not generated when the data reading or checking operation is performed, and the data reading or checking operation can be ensured to be correct data; therefore, by applying positive pressure to the source end of the selected memory cell in the method for inhibiting flash over-erasure, the problem that the over-erased memory cell in the flash memory generates error data due to the leakage of the memory cell in data reading or checking data can be effectively inhibited, namely the method for inhibiting flash over-erasure can still inhibit the leakage of the over-erased memory cell under the condition that the over-erased cell is not repaired, so that the data reading accuracy is ensured.
In the method for inhibiting over-erasure of flash memory, three basic processing modes of applying negative pressure to Bulk ends of selected memory cells, applying negative pressure to word ends of unselected memory cells on the same bit line and applying positive pressure to source ends of selected memory cells are provided, so that over-erasure memory cells are inhibited from leaking electricity during data reading and checking, and further the erased memory cells can be normally used under the condition of no repair, and the three basic processing modes can be independently or randomly matched for use and have the characteristic of diversity.
More specifically, since the absolute value of the voltage required for each of the three processing modes is large when used alone, in some embodiments, it is preferable to use the three modes in combination so that the absolute value of the voltage applied to each portion is smaller than that of the voltage applied when used alone, thereby effectively reducing the power consumption, wherein the case of using the three modes in combination is shown in fig. 1.
In some preferred embodiments, the negative pressure applied to the Bulk terminal of the selected memory cell is-0.75 to-0.25V; specifically, the negative voltage value can correspondingly increase the threshold voltage Vt of the selected memory cell by 0.125V-0.375V, so that the gate trigger voltage Vgt correspondingly decreases by 0.125V-0.375V.
In this embodiment, a voltage of-0.5V is preferably applied to the Bulk terminal of the selected memory cell.
In some preferred embodiments, the negative voltage applied to the word line ends of unselected memory cells on the same bit line is-0.75 to-0.25V; specifically, the negative voltage value can reduce the gate voltage Vgs of the selected memory cell by 0.25 to-0.75V, so that the gate trigger voltage Vgt is correspondingly reduced by 0.25 to-0.75V.
In this embodiment, a voltage of-0.5V is preferably applied to the word line end of the unselected memory cells on the same bit line.
In some preferred embodiments, the positive pressure applied to the source of the selected memory cell is 0.25-0.75 v; specifically, the positive voltage value can reduce the gate voltage Vgs of the selected memory cell by 0.25 to-0.75V, so that the gate trigger voltage Vgt is correspondingly reduced by 0.25 to-0.75V.
In this embodiment, a +0.5V voltage is preferably applied to the source terminal of the selected memory cell.
In some preferred embodiments, when negative pressure is applied to Bulk terminals of selected memory cells, negative pressure is applied to word terminals of unselected memory cells on the same bit line, and positive pressure is applied to source terminals of selected memory cells, the three voltage values can be freely selected for matching, while in this embodiment, the voltage value of negative pressure applied to Bulk terminals of selected memory cells is equal to the voltage value of negative pressure applied to word terminals of unselected memory cells on the same bit line, and the absolute value of negative pressure applied to word terminals of unselected memory cells on the same bit line is equal to the absolute value of positive pressure applied to source terminals of selected memory cells.
Specifically, the absolute values of the three voltages are equal, and the overlarge absolute value of one voltage can be avoided, so that the power consumption of the method for inhibiting the over-erasure of the flash memory in the application embodiment is effectively reduced.
In some preferred embodiments, the gate trigger voltage of a memory cell having an over-erase problem is less than or equal to 0V after applying a negative voltage to the Bulk terminal of a selected memory cell and/or a negative voltage to the word terminal of an unselected memory cell on the same bit line and/or a positive voltage to the source terminal of a selected memory cell.
Specifically, under one or any combination of three processing modes, the problem that the leakage is continuously caused by the fact that the applied voltage is 0V and the gate trigger voltage Vgt is larger than 0 at the word line end of the memory cell for storing the over-erasure problem during data reading can be effectively avoided as long as the gate trigger voltage Vgt is pulled down to 0V or below, and the problems that the data reading error is caused and the reading of other area data is influenced due to the fact that the over-erasure memory cell leakage is effectively avoided.
In a second aspect, referring to fig. 2, fig. 2 is a schematic diagram of an apparatus for inhibiting over-erase of a Flash memory according to some embodiments of the present application, which is configured to inhibit over-erase of a memory cell in a Nor Flash, and includes:
the acquisition module is used for reading or checking the data of the storage unit in the chip;
the voltage operation module is used for applying voltage to the end line of the memory cell in the chip;
the voltage operation module can apply negative pressure to Bulk ends of the selected memory cells and/or negative pressure to word line ends of unselected memory cells on the same bit line and/or positive pressure to source ends of the selected memory cells when the acquisition module performs data reading or checking operation on the memory cells with over-erasure problems in the chip.
Specifically, the voltage operation module may perform one or any combination of three operation methods of applying a negative voltage to the Bulk terminal of the selected memory cell, applying a negative voltage to the word terminal of the unselected memory cell on the same bit line, and applying a positive voltage to the source terminal of the selected memory cell, and may pull down the gate trigger voltage Vgt of the memory cell having the over-erase problem by 0V or less.
According to the device for inhibiting over-erasure of the flash memory, when the acquisition module performs data reading or data verification on the storage unit in the chip, one or any combination of three operations is performed through the voltage operation module, so that the gate trigger voltage Vgt of the storage unit with the over-erasure problem is pulled down, the over-erasure storage unit is inhibited from leaking when the data is read and verified, and the erased storage unit can be normally used under the condition of no repair.
In some preferred embodiments, the voltage operation module includes a first voltage module, a second voltage module, and a third voltage module, where when the acquisition module performs a data reading or verifying operation on a selected memory cell with an over-erase problem in the chip, the first voltage module, the second voltage module, and the third voltage module simultaneously apply a negative pressure to a Bulk end of the selected memory cell, a negative pressure to a word line end of an unselected memory cell on the same bit line, and a positive pressure to a source end of the selected memory cell, respectively.
Specifically, according to design or use requirements, the first voltage module, the second voltage module and the third voltage module can be independently or simultaneously selected for operation in multiple ways to inhibit the leakage behavior of the over-erased memory unit during data reading and checking.
In a third aspect, referring to fig. 3, fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: processor 301 and memory 302, the processor 301 and memory 302 being interconnected and in communication with each other by a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, which when run by a computing device, the processor 301 executes to perform the method in any of the alternative implementations of the embodiments described above.
In a fourth aspect, embodiments of the present application provide a storage medium, which when executed by a processor, performs a method in any of the alternative implementations of the above embodiments. The storage medium may be implemented by any type of volatile or nonvolatile Memory device or combination thereof, such as static random access Memory (Static Random Access Memory, SRAM), electrically erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), erasable Programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), programmable Read-Only Memory (PROM), read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic disk, or optical disk.
In summary, the method, the device, the electronic equipment and the storage medium for inhibiting over-erasure of the flash memory provided by the embodiment of the application, wherein the method provides three basic processing modes of 'negative pressure applied to Bulk ends of selected storage units, negative pressure applied to word line ends of unselected storage units on the same bit line, and positive pressure applied to source ends of selected storage units', so that over-erasure storage units are inhibited from leaking electricity during data reading and checking, and further the erasure storage units can be normally used under the condition of no repair, and the three basic processing modes can be independently or randomly matched for use and have the characteristic of diversity.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (9)
1. A method for inhibiting over-erase of a Flash memory, the method comprising: when the data reading or checking operation is carried out on the selected storage units with the over-erasing problem in the chip, negative pressure is applied to the Bulk end of the selected storage units, negative pressure is applied to the word line ends of the unselected storage units on the same bit line, and positive pressure is applied to the source ends of the selected storage units;
the voltage value of the negative pressure applied to the Bulk terminal of the selected memory cell is equal to the voltage value of the negative pressure applied to the word line terminal of the unselected memory cell on the same bit line, and the absolute value of the negative pressure applied to the word line terminal of the unselected memory cell on the same bit line is equal to the absolute value of the positive pressure applied to the source terminal of the selected memory cell.
2. The method of claim 1, wherein the negative voltage applied to the Bulk terminal of the selected memory cell is-0.75 to-0.25V.
3. The method of claim 1, wherein the negative voltage applied to the word line terminal of the unselected memory cells on the same bit line is-0.75 to-0.25V.
4. The method of claim 1, wherein the positive voltage applied to the source of the selected memory cell is 0.25-0.75 v.
5. The method of claim 1, wherein the gate trigger voltage of the memory cell having the over-erase problem is less than or equal to 0V after applying a negative voltage to the Bulk terminal of the selected memory cell and a negative voltage to the word terminal of the unselected memory cell and a positive voltage to the source terminal of the selected memory cell on the same bit line.
6. An apparatus for inhibiting over-erase of a Flash memory, comprising:
the acquisition module is used for reading or checking the data of the storage unit in the chip;
the voltage operation module is used for applying voltage to the end line of the memory cell in the chip;
the voltage operation module can apply negative pressure to the Bulk end of the selected storage unit, negative pressure to the word line end of the unselected storage unit on the same bit line and positive pressure to the source end of the selected storage unit when the acquisition module performs data reading or checking operation on the selected storage unit with over-erasure problem in the chip;
the voltage value of the negative pressure applied to the Bulk terminal of the selected memory cell is equal to the voltage value of the negative pressure applied to the word line terminal of the unselected memory cell on the same bit line, and the absolute value of the negative pressure applied to the word line terminal of the unselected memory cell on the same bit line is equal to the absolute value of the positive pressure applied to the source terminal of the selected memory cell.
7. The device for inhibiting over-erasure of flash memory according to claim 6, wherein the voltage operation module includes a first voltage module, a second voltage module, and a third voltage module, and when the acquisition module performs a data reading or verifying operation on a memory cell selected to have an over-erasure problem in the chip, the first voltage module, the second voltage module, and the third voltage module simultaneously apply a negative pressure to a Bulk terminal of the selected memory cell, a negative pressure to a word terminal of an unselected memory cell on the same bit line, and a positive pressure to a source terminal of the selected memory cell, respectively.
8. An electronic device comprising a processor and a memory storing computer readable instructions which, when executed by the processor, perform the steps of the method of any of claims 1-5.
9. A storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method according to any of claims 1-5.
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