CN113380606B - A kind of semiconductor graphene and its preparation method and field effect tube - Google Patents

Abstract

The invention belongs to the technical field of manufacture or processing of semiconductor devices, and discloses a semiconductor graphene, a preparation method thereof, and a field effect tube. The semiconductor graphene is directly grown on the Si surface of a silicon carbide substrate as a buffer layer, and the semiconductor graphene is Monolayer and uniform growth, the crystal domain width is 50-200μm, and the length is on the order of millimeters; the preparation method is to mechanically chemically polish two 6H-type and/or 4H-type silicon carbide wafers, ultrasonically clean and dry them; one of them is coated with Apply photoresist; two silicon carbide wafers are placed in a graphite crucible and placed in a "face-to-face"form; first heated in a vacuum environment and then heated in two steps under an argon atmosphere; the obtained semiconductor graphene is used as a groove The materials can be used to prepare field effect transistors. The invention can directly grow single-layer semiconducting graphene on the insulating substrate, the crystal domain area is large, and the switching ratio of the field effect transistor prepared by using the semiconducting graphene reaches 10 ⁴ , which meets the requirement of practical application.

Description

A kind of semiconductor graphene and its preparation method and field effect tube

technical field

The invention belongs to the technical field of manufacture or processing of semiconductor devices, and in particular relates to a semiconductor graphene and a preparation method and application thereof.

Background technique

With the rapid development of modern microelectronics technology, traditional silicon-based semiconductor electronic devices have significantly lagged behind the post-Mohr's Law era. Finding a new basic material for electronic devices is an inevitable demand for the development of civilization. As a two-dimensional material arranged by carbon atoms, graphene can exist stably in nature, and it is considered to be composed of Si-based materials because of its amazing potential application value in the fields of mechanics, electronics, optics, biology, catalysis, etc. The bridge from the era to the carbon-based era.

Although graphene has great potential in the field of semiconductors, graphene is a zero-bandgap material and has a very low on-off ratio, which limits its application in the field of logic devices. Therefore, opening the graphene bandgap has become the first priority of graphene research. subject. Compared with many other graphene growth methods, the use of single crystal SiC to obtain epitaxially grown graphene by pyrolysis can effectively avoid the introduction of defects in the preparation process of electronic devices, such as wrinkles, cracks, impurity pollution and other unfavorable factors. Most importantly, the substrates used for epitaxial graphene growth are SiC wafers that are compatible with conventional semiconductor processes, which seems to be the only basic material that can be used to fabricate 2D electronic devices in terms of current development trends.

It can be seen that in order to continue Moore's Law to improve the integration and performance of devices, it is imperative to find new large-area semiconductor materials. In recent years, two-dimensional materials have become one of the best candidates, among which graphene is the most representative. However, graphene has no band gap defect, so graphene cannot be applied to logic devices, especially field effect transistors.

Since SiC has two polar planes, both planes can be used as substrates for graphene growth. However, since the sublimation rate of Si is difficult to control on the C surface, the grown graphene is generally multi-layered. On the contrary, the Si surface can generally grow large-area single-layer epitaxial graphene, which has become the most widely studied platform. The first layer grown on the Si surface is called a carbon-rich layer. Although it has graphene atomic arrangement, it does not have intrinsic graphene properties and is called a buffer layer. It has been experimentally and theoretically proved that the buffer layer is a real semiconductor with 0.5-1 eV, because the buffer layer is partially bonded to the Si atom of the substrate (30%), thus making the sp ² hybridization into sp ³ hybridization, Causes a symmetry breaking, thereby opening the band gap.

In the process of epitaxial growth of Si surface, it is inevitably affected by the "step bunching effect", resulting in a strange "landscape" in which terraces and steps alternately exist on the Si surface, and these steps are in the electron transport. It plays the role of scattering; in addition, the epitaxial graphene at the step is the first to nucleate, and the growth rate is significantly faster than the growth of graphene at the platform, so the growth of the buffer layer is likely to cause the graphene at the step to short-circuit the platform and the buffer between the platform layer situation.

The growth condition of Si-plane epitaxial graphene is mainly distributed between single-layer and double-layer (or triple-layer) graphene, which is mainly determined by the growth mechanism of Si-plane epitaxial graphene, so in a strict sense, large-area Si-plane single-layer graphene Layered graphene is characterized by a bilayer or trilayer graphene distribution. In this way, the crystal domain size of graphene is limited to the order of ten micrometers by the platform width, so there is no solution for growing large-domain semiconducting graphene on the Si surface in the prior art. The small crystal domain area of Si-plane monolayer graphene is often not conducive to device integration, thus limiting its application in industrial production.

SUMMARY OF THE INVENTION

The invention aims to solve the technical problem that the crystal domain area growth of the silicon carbide Si surface monolayer graphene is limited, and provides a semiconductor graphene and a preparation method and application thereof.

In order to solve the above-mentioned technical problems, the present invention is realized through the following technical solutions:

According to one aspect of the present invention, a semiconductor graphene is provided, comprising a silicon carbide substrate, and a semiconductor graphene is directly grown on the Si surface of the silicon carbide substrate as a buffer layer, and the semiconductor graphene is a single layer and uniform For growth, the crystal domain width of the semiconductor graphene buffer layer is 50-200 μm, and the length is in the order of millimeters.

Further, the semiconductor graphene forms a bond directly with the SiC substrate.

According to another aspect of the present invention, a kind of preparation method of above-mentioned semiconductor graphene is provided, and this method is carried out according to the following steps:

(1) Mechanochemical polishing is carried out with silicon carbide wafer A and silicon carbide wafer B; wherein, silicon carbide wafer A is a 6H-type or 4H-type silicon carbide wafer, and silicon carbide wafer B is a 6H-type silicon carbide wafer;

(2) ultrasonically cleaning the silicon carbide wafer A and the silicon carbide wafer B in an organic reagent and drying;

(3) silicon carbide wafer A is coated with photoresist, and silicon carbide wafer B is not coated with photoresist;

(4) Put the silicon carbide wafer A and the silicon carbide wafer B coated with the photoresist into the graphite crucible, and place the silicon carbide wafer A on the bottom and the silicon carbide wafer B on the top. The C side of A is opposite to the Si side of the silicon carbide wafer B;

(5) heating the graphite crucible of the silicon carbide wafer A and the silicon carbide wafer B in a vacuum environment for 20-30min under a temperature condition of 900-950°C;

(6) the graphite crucible where the silicon carbide wafer A and the silicon carbide wafer B are stacked and placed is heated to 1200°C-1350°C under an argon atmosphere, and heated for 20-30min;

(7) Continue to heat up the graphite crucible on which the silicon carbide wafer A and the silicon carbide wafer B are stacked to 1540°C-1650°C under an argon atmosphere, and heat for 60-90 minutes.

Further, the coating thickness of the photoresist in step (3) is 10-40 nm.

Further, the heating temperature in step (5) was 900° C., and the heating time was 20 min.

Further, the heating temperature in step (6) was 1300° C., and the heating time was 20 min.

Further, the heating temperature in step (7) was 1580° C., and the heating time was 50 min.

Further, the argon flow rate in step (6) and step (7) are both 400sccm.

According to another aspect of the present invention, a field effect transistor is provided, and the above-mentioned semiconductor graphene is used as a channel material.

The beneficial effects of the present invention are:

The semiconductor graphene and the preparation method thereof of the present invention do not need to be transferred to an insulating substrate without the aid of external means, but directly grow semiconductor graphene with a super-large crystal domain on the Si surface of the SiC insulating substrate. It greatly simplifies the production steps in industrial production, thereby saving costs, and is expected to be used in industrial production. It provides an ideal solution for directly opening the graphene band gap on an insulating substrate. It is widely used in the field of semiconductor and gas sensing. potential application value.

The invention uses organic substances to assist and control the sublimation of Si atoms, which is more conducive to the generation of large steps, and can obtain a semiconductor graphene buffer layer with a large crystal domain area, a width of more than 100 microns, and a length of the order of millimeters and a uniform height. The size of the crystal domains can be clearly seen.

Using the semiconductor graphene field effect transistor of the present invention as the channel material, the on-off ratio can reach 10 ⁴ , thereby having a faster working rate and small leakage current, reducing power consumption, and meeting the needs of practical applications.

Description of drawings

1 is a schematic diagram of the atomic structure of semiconductor graphene of the present invention.

Fig. 2 is the Raman fitting diagram of the semiconductor graphene-buffer layer prepared in Example 1;

Fig. 3 is the SEM image of the prepared semiconductor graphene-buffer layer of embodiment 1;

FIG. 4 is a graph showing the transfer characteristic of the field effect transistor prepared in Example 5. FIG.

Detailed ways

The present invention will be further described in detail below through specific examples, which can make those skilled in the art understand the present invention more comprehensively, but do not limit the present invention in any way.

Example 1

The semiconductor graphene buffer layer is directly grown on the Si surface of the silicon carbide substrate, and the specific steps are as follows:

(1) Select two 6H-type silicon carbide wafers, respectively called silicon carbide wafer A and silicon carbide wafer B; perform mechanical chemical polishing (CMP) on silicon carbide wafer A and silicon carbide wafer B, remove paraffin and thoroughly clean ;

(2) ultrasonically sonicate silicon carbide wafer A and silicon carbide wafer B in acetone, absolute ethanol, and deionized water for 15-30 min each, and blow dry with N _;

(3) 10nm thick AZ photoresist is spin-coated on silicon carbide wafer A, and silicon carbide wafer B is not coated with photoresist;

(4) Put the silicon carbide wafer A and the silicon carbide wafer B coated with the photoresist into the graphite crucible, and place them in the form of "face-to-face"; specifically, the silicon carbide wafer A is below and the silicon carbide wafer B Placed on top of each other, and the C surface of the silicon carbide wafer A is opposite to the Si surface of the silicon carbide wafer B;

(5) Put the graphite crucible on which the silicon carbide wafer A and the silicon carbide wafer B are stacked and placed into the induction heating furnace. When the vacuum degree reaches about 5×10 ^-6 mbar, the growth begins; the first stage is in a vacuum environment 900℃ for 30min;

(6) 400sccm flow of argon in the second stage, maintained at 1300°C for 20min;

(7) 400sccm flow of argon in the third stage, maintained at 1578°C for 90min;

(8) furnace cooling, the growth is completed, and the large crystal domain semiconductor graphene is obtained, and the crystal domain width reaches 200 μm and the length is on the order of millimeters.

Example 2

The semiconductor graphene buffer layer is directly grown on the Si surface of the silicon carbide substrate by the method of Example 1, the difference is only that the temperature in step (7) is 1650° C. for 90 minutes.

Example 3

The semiconductor graphene buffer layer is directly grown on the Si surface of the silicon carbide substrate by the method of Example 1, and the difference is only that the 4H-type silicon carbide wafer is selected as the silicon carbide wafer A, and the 6H-type silicon carbide wafer is selected as the silicon carbide wafer B.

Example 4

The semiconductor graphene buffer layer is directly grown on the Si surface of the silicon carbide substrate by the method of Example 1, the difference is only that the temperature in step (7) is 1580° C. for 90 minutes.

Example 5

The method of Example 1 is used to directly grow the semiconductor graphene buffer layer on the Si surface of the silicon carbide substrate.

Example 6

The semiconductor graphene buffer layer is directly grown on the Si surface of the silicon carbide substrate by the method of Example 1, and the difference is only that AZ photoresist with a thickness of 40 nm is spin-coated in step (3).

Example 7

The semiconductor graphene buffer layer is directly grown on the Si surface of the silicon carbide substrate by the method of Example 1, and the difference is only that the temperature in step (7) is 1540°C.

Example 8

The large crystal domain semiconductor graphene obtained in Examples 1 and 3 is used as a channel material to prepare a field effect transistor, and the specific steps are as follows:

First define the source/drain electrodes of the device by photolithography and e-beam evaporation;

The shape of the channel is defined by photolithography, the channel width is 30um and the length is 50um;

Evaporating Al ₂ O ₃ with a thickness of 2 nm over the channel by electron beam evaporation;

Immediately put it into atomic layer deposition to evaporate Al ₂ O ₃ with a thickness of 15 nm;

Finally, the gate of the device is defined by photolithography and electron beam evaporation;

Results The switching ratios of the field effect transistors tested by the semiconductor tester all reached the order of 10 ⁴ .

Discussion on the above example results and data

The present invention discusses in detail increasing the crystal domain size of semiconducting graphene and the application of this large domain semiconducting graphene as a logic device. Considering the alternating distribution of steps and platforms on the Si surface of general SiC due to the bunching effect, the size of the single crystal is limited, so the organic matter-assisted method is used to greatly increase the area of the platform, and the organic matter plays a key role in this process. During the growth process, the effects of temperature and airflow are taken into account. Finally, considering that the graphene grown by this method has a band gap, the properties of this material are characterized by processing field effect tubes.

Figure 1 shows the lattice structure of semiconducting graphene. In order to confirm that the material grown in the present invention has this structure, Raman was used to characterize Examples 1, 2, 3 and 4. The results are shown in Figure 2, with four peaks , the peak positions are at 1355cm ^-1 , 1500cm ^-1 , 1550cm ^-1 , and 1562cm ^-1 , respectively, indicating that the grown material is semiconducting graphene.

In order to grow semiconductor graphene with large crystal domains, the above embodiments use SiC substrates with different crystal types and the temperature is in the range of 1540 ° C - 1650 ° C. It is found that the B plate is 6H type and can grow semiconductor graphite with large crystal domains. Graphene, while the B sheet is 4H type, cannot grow large-domain semiconductor graphene. As shown in Figure 3, the area size of the crystal domain can be clearly seen from the SEM image, and the width exceeds 200 μm.

In the present invention, the materials grown under the conditions of Examples 1 and 3 are used as channel materials to prepare field effect transistors, and the measured switching ratio reaches 10 ⁴ . As shown in Fig. 4, the switching ratio reaches 10 ⁴ and the threshold voltage is -0.2V.

Although the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above-mentioned specific embodiments. Under the inspiration of the present invention, without departing from the scope of the present invention and the protection scope of the claims, personnel can also make many specific transformations, which all fall within the protection scope of the present invention.

Claims (9)

1. The semiconductor graphene comprises a silicon carbide substrate, and is characterized in that the semiconductor graphene is directly grown on the Si surface of the silicon carbide substrate to serve as a buffer layer, the semiconductor graphene is single-layer and uniformly grown, the domain width of the semiconductor graphene buffer layer is 50-200 mu m, and the length of the semiconductor graphene buffer layer is in millimeter order; and is prepared by the following method:

(1) carrying out mechanical chemical polishing on the silicon carbide wafer A and the silicon carbide wafer B; wherein the silicon carbide wafer A is a 6H type or 4H type silicon carbide wafer, and the silicon carbide wafer B is a 6H type silicon carbide wafer;

(2) ultrasonically cleaning a silicon carbide wafer A and a silicon carbide wafer B in an organic reagent and drying;

(3) coating the silicon carbide wafer A with photoresist, and not coating the silicon carbide wafer B with photoresist;

(4) placing the silicon carbide wafer A and the silicon carbide wafer B coated with the photoresist into a graphite crucible, and superposing the silicon carbide wafer A and the silicon carbide wafer B in a mode that the silicon carbide wafer A is arranged at the lower part and the silicon carbide wafer B is arranged at the upper part, wherein the C surface of the silicon carbide wafer A is opposite to the Si surface of the silicon carbide wafer B;

(5) heating the graphite crucible in which the silicon carbide wafer A and the silicon carbide wafer B are superposed and placed for 20-30min in a vacuum environment at the temperature of 900-950 ℃;

(6) heating the graphite crucible in which the silicon carbide wafer A and the silicon carbide wafer B are superposed to 1200-1350 ℃ in an argon atmosphere for 20-30 min;

(7) and continuously heating the graphite crucibles on which the silicon carbide wafer A and the silicon carbide wafer B are superposed to 1540-1650 ℃ in the argon atmosphere, and heating for 60-90 min.

2. The semiconductor graphene according to claim 1, wherein the semiconductor graphene is directly bonded to a SiC substrate.

3. A method for preparing semiconducting graphene according to any one of claims 1-2, wherein the method is performed according to the following steps:

(1) carrying out mechanical chemical polishing on the silicon carbide wafer A and the silicon carbide wafer B; wherein the silicon carbide wafer A is a 6H type or 4H type silicon carbide wafer, and the silicon carbide wafer B is a 6H type silicon carbide wafer;

(2) ultrasonically cleaning a silicon carbide wafer A and a silicon carbide wafer B in an organic reagent and drying;

(3) coating the silicon carbide wafer A with photoresist, and not coating the silicon carbide wafer B with photoresist;

(4) placing the silicon carbide wafer A and the silicon carbide wafer B coated with the photoresist into a graphite crucible, and superposing the silicon carbide wafer A and the silicon carbide wafer B in a mode that the silicon carbide wafer A is arranged at the lower part and the silicon carbide wafer B is arranged at the upper part, wherein the C surface of the silicon carbide wafer A is opposite to the Si surface of the silicon carbide wafer B;

(5) heating the graphite crucible in which the silicon carbide wafer A and the silicon carbide wafer B are superposed for 20-30min in a vacuum environment at the temperature of 900-950 ℃;

(6) heating the graphite crucible in which the silicon carbide wafer A and the silicon carbide wafer B are superposed to 1200-1350 ℃ in an argon atmosphere for 20-30 min;

(7) and continuously heating the graphite crucibles on which the silicon carbide wafer A and the silicon carbide wafer B are superposed to 1540-1650 ℃ in the argon atmosphere, and heating for 60-90 min.

4. The method for preparing semiconductor graphene according to claim 3, wherein the coating thickness of the photoresist in the step (3) is 10-40 nm.

5. The method for preparing semiconductor graphene according to claim 3, wherein the heating temperature in the step (5) is 900 ℃ and the heating time is 20 min.

6. The method for preparing semiconductor graphene according to claim 3, wherein the heating temperature in the step (6) is 1300 ℃ and the heating time is 20 min.

7. The preparation method of semiconductor graphene according to claim 3, wherein the heating temperature in the step (7) is 1580 ℃ and the heating time is 50 min.

8. The method for preparing semiconductor graphene according to claim 3, wherein the argon gas flow in the step (6) and the argon gas flow in the step (7) are both 400 sccm.

9. A field effect transistor, characterized in that the semiconducting graphene according to any one of claims 1-2 is used as a channel material.

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