CN113378505A - Routing layout adjusting method and device, electronic equipment and storage medium - Google Patents
Routing layout adjusting method and device, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN113378505A CN113378505A CN202010161449.1A CN202010161449A CN113378505A CN 113378505 A CN113378505 A CN 113378505A CN 202010161449 A CN202010161449 A CN 202010161449A CN 113378505 A CN113378505 A CN 113378505A
- Authority
- CN
- China
- Prior art keywords
- pin
- determining
- signal
- target
- termination position
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention discloses a routing layout adjusting method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a line sequence network of a printed circuit board, determining the tail end of a signal to be modified in the line sequence network, and acquiring the coordinates of the termination position of a wire to be modified; the signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire; determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the to-be-modified wiring; and determining a target pin meeting a preset condition from the at least one pin to be selected, and determining the target pin as a signal conduction pin. By adopting the technical scheme, the pin signal can be more efficiently and accurately adjusted when the printed circuit board is difficult to be led out.
Description
Technical Field
The present invention relates to the electronic industry, and in particular, to a method and an apparatus for adjusting routing layout, an electronic device, and a storage medium.
Background
PCBs (Printed circuit boards) are one of the important components of the electronics industry, and are used in almost every electronic device. Small to electronic watches, calculators, large to computers, communication electronics, military weaponry systems, etc.
In a complex PCB design, the situation that the wire sequence of a chip part is not orderly to cause the wire outlet difficulty is often found in the laying-out or wiring stage. This is solved in the following way: punching a hole to forcibly change the layer for outgoing; adjusting the layout of the chip or the interface end, and sorting out wires; checking the chip data and adjusting the signal definition. However, the above solutions have too many human factors, are prone to error, and have slow adjustment speed and low efficiency.
Therefore, a method for adjusting the signal definition quickly is needed to adjust the pin signal more efficiently and accurately when the outgoing line is difficult.
Disclosure of Invention
The invention provides a wiring layout adjusting method, a wiring layout adjusting device, electronic equipment and a storage medium, and aims to realize more efficient and accurate adjustment of pin signals.
In a first aspect, an embodiment of the present invention provides a method for adjusting a routing layout, including:
acquiring a line sequence network of a printed circuit board, determining the tail end of a signal to be modified in the line sequence network, and acquiring the coordinates of the termination position of a wire to be modified; the signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire;
determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the to-be-modified wiring;
and determining a target pin meeting a preset condition from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
In a second aspect, an embodiment of the present invention further provides a routing layout adjusting device, including:
the wire termination position coordinate determination module is used for acquiring a line sequence network of the printed circuit board, determining the tail end of a signal to be modified in the line sequence network and obtaining the wire termination position coordinate to be modified; the signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire;
the to-be-selected pin determining module is used for determining at least one to-be-selected pin on the printed circuit board according to the coordinates of the termination position of the to-be-modified wire;
and the signal conduction pin determining module is used for determining a target pin meeting a preset condition from the at least one pin to be selected and determining the target pin as the signal conduction pin.
In a third aspect, an embodiment of the present invention further provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the trace layout adjustment method according to any one of the embodiments of the present invention.
In a fourth aspect, an embodiment of the present invention further provides a storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the trace layout adjusting method according to any one of the embodiments of the present invention.
According to the method and the device, the wire sequence network to be modified of the printed circuit board is obtained, the functional tail end routing of the wire sequence network to be modified is determined, and the routing termination coordinate is obtained; determining at least one pin to be selected on the printed circuit board according to the wiring termination coordinate of the line sequence network to be modified; and determining a target pin meeting a preset condition from the at least one pin to be selected, and determining the target pin as a signal conduction pin. The technical scheme of the invention can more efficiently and accurately adjust the pin signal when the outgoing line is difficult.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for adjusting a routing layout according to a first embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating a routing layout adjusting method according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a tool interface provided in a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a routing layout adjustment apparatus according to a third embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1 is a schematic flow chart of a trace layout adjusting method according to an embodiment of the present invention, where the method is applicable to a situation where a wire is difficult to be led out in a PCB design process, and the method can be executed by a trace layout adjusting device, and the device can be implemented in a software and/or hardware manner, and can be integrated in an electronic device, and specifically includes the following steps:
step 110, acquiring a line sequence network of the printed circuit board, determining the tail end of a signal to be modified in the line sequence network, and obtaining the coordinates of the termination position of a wire to be modified; the signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire.
In this embodiment, the printed circuit board is also called a printed circuit board, which is a platform for electrical connection of electronic components. The design of the printed circuit board is mainly a layout design, and a line sequence network meeting corresponding functions needs to be designed in the layout design, wherein the line sequence network is generally formed by a plurality of groups of wires. Furthermore, signals are generally transmitted through the wires, functions of the signals are arranged corresponding to the wires, connection modes of the wires are different, and corresponding functions of the signals are different. In the design stage, the signals often need to be modified, and the modified connecting pins are actually routing. The end of the signal to be modified refers to the position where the function of the signal is finished, and the position of the end of the signal corresponds to the termination position of the corresponding trace. However, the coordinates of the termination position of the wire are mostly the positions where the wire can not be drawn out, or the forced wire drawing can cause the disorder of the wire. In this embodiment, after the end of the signal to be modified is obtained, the position where the line sequence function ends is determined in the printed circuit board, the coordinates of the termination position of the trace that cannot be wired are determined, the pin to be originally connected to the line is obtained, and the pin is marked as G.
And 120, determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the to-be-modified wire.
In this embodiment, the pin to be selected is a pin to which a line of the coordinates of the routing termination position can be reconnected. And determining a pin group by combining preset information of the pin group according to the specific position of the coordinates of the routing termination position and the pin G, wherein the pin in the pin group can access the same signal as the pin G. And traversing the pins in the pin group, and taking the idle pins in the pin group as pins to be selected.
In this technical solution, optionally, determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the to-be-modified trace, including:
judging whether an idle pin exists in a target area on the printed circuit board or not according to the coordinates of the termination position of the to-be-modified wire;
and if so, determining idle pins existing in the target area as pins to be selected.
In this embodiment, the target area is an area where a distance from the coordinates of the routing termination position meets a preset condition, and the target area includes pins. Specifically, the target area may be determined by taking the coordinates of the termination position of the trace as a circle center and a preset distance as a radius, and determining the pins within the range. The idle pin is a pin which is not connected with the wiring, and further, the idle pin can have the conduction function of one signal and also can have the conduction function of a plurality of signals.
In this technical solution, optionally, determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the to-be-modified trace, including:
acquiring idle pins existing in a non-target area on the printed circuit board and coordinates of the idle pins,
determining the distance between the idle pin coordinate and the wiring termination position coordinate according to the to-be-modified wiring termination position coordinate and the idle pin coordinate;
and determining a pin to be selected from the idle pins according to the distance.
In this embodiment, the coordinates of the end position of the trace are set as (x, y), and the coordinates of the idle pin in the non-target area are set as (z)i,wi) Wherein, i is used for distinguishing different idle pins, and the distance d between the I and the I is calculated according to the coordinates of the termination position of the routing and the coordinates of the idle pinsiTo be sure to know
Will diSorting according to the sequence from small to large, and diThe pin satisfying the preset condition is selected as the pin to be selected, wherein the preset condition can be d in the non-target areaiThe first three in the sequence.
Step 130, determining a target pin meeting a preset condition from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
In this embodiment, the target pin is a pin that is determined from the pins to be selected and is finally used for connecting the trace of the trace termination position coordinate. In this embodiment, the preset condition may be a preset distance condition, and the preset distance condition may be that the distance between the coordinates of the termination position of the trace and the coordinates of the idle pin is minimum, that is, the value of d between the coordinates of the idle pin and the coordinates of the termination position of the trace is minimum, and then the corresponding idle pin is determined to be the target pin. Of course, the preset condition may also be signal strength or signal function, which is not listed here.
According to the technical scheme of the embodiment, the routing termination position coordinates of the line sequence network to be modified are determined by acquiring the line sequence network to be modified of the printed circuit board; determining at least one pin to be selected on the printed circuit board according to the coordinates of the wiring termination position of the line sequence network to be modified; and determining a target pin meeting a preset condition from the at least one pin to be selected, and determining the target pin as a signal conduction pin. The pin signal can be adjusted more efficiently and accurately when the printed circuit board is difficult to be led out.
Example two
Fig. 2 is a schematic flow chart of a routing layout adjustment method according to a second embodiment of the present invention, and this embodiment is further optimized on the basis of the foregoing embodiment, and specifically optimized as follows: how to further determine the target pin specifically includes the following steps:
step 210, obtaining a line sequence network of the printed circuit board, determining a tail end of a signal to be modified in the line sequence network, and obtaining coordinates of a termination position of a wire to be modified.
The signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire.
And step 220, determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the to-be-modified wire.
Step 230, determining a target pin meeting a preset condition from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
In this embodiment, the preset condition is preferably a preset distance condition.
Step 240, if there are at least two signals, the determined target pin is a pin to be selected, and it is determined whether there is a difference in preset priority between the at least two signals.
In this embodiment, the signal may be a data signal or a pulse signal, where the data signal may be a plurality of different data signals. The signals are conducted by tracks at the coordinates of the track termination locations, and different signals are conducted by different tracks. The priority of the different signals may be predetermined, with high priority signals being conducted first. Specifically, the manner of determining the priority may be preset in a tool interface, which may be referred to as a schematic diagram of a tool interface shown in fig. 3, where the interface includes: signal priority settings, signal information and output information of the line-sequential network, etc.
If yes, go to step 250; if not, go to step 260.
And step 250, determining the target pin as a target pin of a high-priority signal in the at least two signals according to the preset priority difference.
When different signals have preset priority differences, the target pin of the high-priority signal is processed preferentially. For example, if the signal a is a data signal, the signal B is a pulse signal, and the priority of the data signal is set to be higher than that of the pulse signal, then if the target pin determined by the signal a and the signal B is the same candidate pin C, the candidate pin C is the target pin of the signal a because the signal a is higher than the signal B.
Specifically, if the a signal is a data signal, the B signal is also a data signal, and the priority between the a signal and the B signal is the same. And if the target pin determined by the signal A and the signal B is the same pin D to be selected, comparing the signals which are more consistent with the preset distance condition between the signal f and the signal g, and taking the pin D to be selected as the target pin of the signal. And f is the distance between the coordinates of the wiring termination position of the signal A and the pin D to be selected, and g is the distance between the coordinates of the wiring termination position of the signal B and the pin D to be selected. Specifically, when the preset distance condition is that the distance is the minimum, if f is smaller than g, the pin D to be selected is used as the target pin of the signal a.
And 270, outputting the coordinates of the routing termination position, the target pin and signals of the target pin.
In this embodiment, after the target pin is determined, the target pin, the coordinates of the termination position of the trace, and the signal of the target pin may be output in a form of a table, and further, information of the pin originally connected to the trace at the coordinates of the termination position of the trace may be output, so as to modify the schematic diagram.
In the technical scheme of this embodiment, if a target pin determined by at least two signals is a pin to be selected, it is determined whether the at least two signals have a difference in preset priority. And if so, determining the target pin as the target pin of a high-priority signal in the at least two signals according to the preset priority difference. By preferentially processing the signals with high priority, the layout of the line sequence network can be more rationalized on the basis of solving the difficulty of outgoing lines of the PCB.
EXAMPLE III
Fig. 4 is a schematic structural diagram of a routing layout adjusting device according to a third embodiment of the present invention. The routing layout adjusting device provided by the embodiment of the invention can execute the routing layout adjusting method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the executing method. As shown in fig. 4, the apparatus includes:
the trace termination position coordinate determination module 401 is configured to obtain a line sequence network of the printed circuit board, determine a terminal of a signal to be modified in the line sequence network, and obtain a coordinate of a termination position of a trace to be modified; the signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire;
a candidate pin determining module 402, configured to determine at least one candidate pin on the printed circuit board according to the coordinates of the termination position of the to-be-modified trace;
a signal conducting pin determining module 403, configured to determine, from the at least one pin to be selected, a target pin meeting a preset condition, and determine the target pin as a signal conducting pin.
The device further comprises:
a preset priority difference determining module 404, configured to determine whether there is a preset priority difference between at least two signals if there is a target pin determined by the at least two signals that is a pin to be selected;
and a target pin allocating module 405, configured to allocate, if yes, the target pin as a target pin of a high-priority signal in the at least two signals according to the preset priority difference.
The candidate pin determining module 402 is specifically configured to:
judging whether an idle pin exists in a target area on the printed circuit board or not according to the coordinates of the termination position of the to-be-modified wire;
and if so, determining idle pins existing in the target area as pins to be selected.
The candidate pin determining module 402 is specifically configured to obtain an idle pin existing in a non-target area on the printed circuit board and coordinates of the idle pin,
determining the distance between the idle pin coordinate and the wiring termination position coordinate according to the to-be-modified wiring termination position coordinate and the idle pin coordinate;
and determining a pin to be selected from the idle pins according to the distance.
The device comprises:
an output module 406, configured to output the coordinates of the trace ending position, the target pin, and the signal of the target pin.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
Example four
Fig. 5 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention, and fig. 5 is a schematic structural diagram of an exemplary device suitable for implementing the fourth embodiment of the present invention. The electronic device 12 shown in fig. 5 is only an example and should not bring any limitation to the function and the scope of use of the embodiment of the present invention.
As shown in FIG. 5, electronic device 12 is embodied in the form of a general purpose computing device. The components of electronic device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including the system memory 28 and the processing unit 16.
The system memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)30 and/or cache memory 32. The electronic device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 5, and commonly referred to as a "hard drive"). Although not shown in FIG. 5, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 by one or more data media interfaces. System memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in system memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 42 generally carry out the functions and/or methodologies of embodiments described herein.
The processing unit 16 executes various functional applications and data processing by running the program stored in the system memory 28, for example, to implement a trace layout adjustment method provided by the embodiment of the present invention, including:
acquiring a line sequence network of a printed circuit board, determining the tail end of a signal to be modified in the line sequence network, and acquiring the coordinates of the termination position of a wire to be modified; the signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire;
determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the to-be-modified wiring;
and determining a target pin meeting a preset condition from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
EXAMPLE five
An embodiment of the present invention further provides a storage medium, where a computer program (or called computer executable instruction) is stored, and when the program is executed by a processor, the method for adjusting routing layout according to any of the embodiments above may be implemented, where the method includes:
acquiring a line sequence network of a printed circuit board, determining the tail end of a signal to be modified in the line sequence network, and acquiring the coordinates of the termination position of a wire to be modified; the signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire;
determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the to-be-modified wiring;
and determining a target pin meeting a preset condition from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
Storage media for embodiments of the present invention may take the form of any combination of one or more computer-readable media. The readable medium may be a computer readable signal medium or a computer readable storage medium. Take the form of a computer storage medium. A storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for embodiments of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A routing layout adjustment method is characterized by comprising the following steps:
acquiring a line sequence network of a printed circuit board, determining the tail end of a signal to be modified in the line sequence network, and acquiring the coordinates of the termination position of a wire to be modified; the signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire;
determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the to-be-modified wiring;
and determining a target pin meeting a preset condition from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
2. The method according to claim 1, wherein determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the trace to be modified comprises:
judging whether an idle pin exists in a target area on the printed circuit board or not according to the coordinates of the termination position of the to-be-modified wire;
and if so, determining idle pins existing in the target area as pins to be selected.
3. The method according to claim 1, wherein determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the trace to be modified comprises:
acquiring idle pins existing in a non-target area on the printed circuit board and coordinates of the idle pins,
determining the distance between the idle pin coordinate and the wiring termination position coordinate according to the to-be-modified wiring termination position coordinate and the idle pin coordinate;
and determining a pin to be selected from the idle pins according to the distance.
4. The method according to any one of claims 1 to 3, wherein after determining a target pin meeting a preset condition from the at least one pin to be selected, the method further comprises:
if the target pins determined by the at least two signals are the same pin to be selected, judging whether the at least two signals have a preset priority level;
if so, determining the target pin as the target pin of a high-priority signal in the at least two signals according to the preset priority.
5. The method of claim 1, further comprising, after determining the target pin as a signaling pin:
and outputting the coordinates of the routing termination position, the target pin and signals of the target pin.
6. A routing layout adjusting device, comprising:
the wire termination position coordinate determination module is used for acquiring a line sequence network of the printed circuit board, determining the tail end of a signal to be modified in the line sequence network and obtaining the wire termination position coordinate to be modified; the signal is transmitted through a wire, and the end position of the signal corresponds to the termination position of the wire;
the to-be-selected pin determining module is used for determining at least one to-be-selected pin on the printed circuit board according to the coordinates of the termination position of the to-be-modified wire;
and the signal conduction pin determining module is used for determining a target pin meeting a preset condition from the at least one pin to be selected and determining the target pin as the signal conduction pin.
7. The apparatus of claim 6, wherein the to-be-selected pin determination module is specifically configured to:
judging whether an idle pin exists in a target area on the printed circuit board or not according to the coordinates of the termination position of the to-be-modified wire;
and if so, determining idle pins existing in the target area as pins to be selected.
8. The apparatus of claim 6 or 7, further comprising:
the device comprises a preset priority determining module, a priority determining module and a priority determining module, wherein the preset priority determining module is used for judging whether at least two signals have preset priorities or not if target pins determined by the at least two signals are the same pins to be selected;
and the target pin allocation module is used for allocating the target pin as a target pin of a high-priority signal in the at least two signals according to the preset priority if the target pin is the high-priority signal.
9. An electronic device comprising a memory, a processor and a program stored in the memory and executable on the processor, wherein the processor implements the trace layout adjustment method according to any one of claims 1-5 when executing the program.
10. A storage medium having a program stored thereon, wherein the program, when executed by a processor, implements the trace layout adjustment method according to any one of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010161449.1A CN113378505B (en) | 2020-03-10 | 2020-03-10 | A wiring layout adjustment method, device, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010161449.1A CN113378505B (en) | 2020-03-10 | 2020-03-10 | A wiring layout adjustment method, device, electronic equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113378505A true CN113378505A (en) | 2021-09-10 |
| CN113378505B CN113378505B (en) | 2023-05-30 |
Family
ID=77568706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010161449.1A Active CN113378505B (en) | 2020-03-10 | 2020-03-10 | A wiring layout adjustment method, device, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113378505B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0836596A (en) * | 1994-07-26 | 1996-02-06 | Oki Electric Ind Co Ltd | Wiring board wiring method and device therefor |
| JP2003279624A (en) * | 2002-03-26 | 2003-10-02 | Fujitsu Ltd | Electronic component testing equipment |
| US20050278679A1 (en) * | 2003-02-17 | 2005-12-15 | Nec Informatec Systems, Ltd. | Device for estimating number of board layers constituting board, system including the device, and method for estimating the same and program for executing the method |
| CN103153001A (en) * | 2013-02-05 | 2013-06-12 | 浙江宇视科技有限公司 | Printed circuit board (PCB) and processing method |
| CN106648007A (en) * | 2016-12-09 | 2017-05-10 | 浙江宇视科技有限公司 | Method and device for implementing general slots and communication device |
| CN107592728A (en) * | 2017-09-26 | 2018-01-16 | 郑州云海信息技术有限公司 | A kind of method and structure of PCB placement-and-routings |
| US20180157782A1 (en) * | 2016-12-06 | 2018-06-07 | Synopsys, Inc. | Automated Place-And-Route Method For HBM-Based IC Devices |
| CN110378062A (en) * | 2019-07-26 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of the pin wiring inspection method and relevant apparatus of differential lines |
| US20190376796A1 (en) * | 2018-06-06 | 2019-12-12 | Baidu Online Network Technology (Beijing) Co., Ltd. | Method and device for acquiring road track, and storage medium |
-
2020
- 2020-03-10 CN CN202010161449.1A patent/CN113378505B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0836596A (en) * | 1994-07-26 | 1996-02-06 | Oki Electric Ind Co Ltd | Wiring board wiring method and device therefor |
| JP2003279624A (en) * | 2002-03-26 | 2003-10-02 | Fujitsu Ltd | Electronic component testing equipment |
| US20050278679A1 (en) * | 2003-02-17 | 2005-12-15 | Nec Informatec Systems, Ltd. | Device for estimating number of board layers constituting board, system including the device, and method for estimating the same and program for executing the method |
| CN103153001A (en) * | 2013-02-05 | 2013-06-12 | 浙江宇视科技有限公司 | Printed circuit board (PCB) and processing method |
| US20180157782A1 (en) * | 2016-12-06 | 2018-06-07 | Synopsys, Inc. | Automated Place-And-Route Method For HBM-Based IC Devices |
| CN106648007A (en) * | 2016-12-09 | 2017-05-10 | 浙江宇视科技有限公司 | Method and device for implementing general slots and communication device |
| CN107592728A (en) * | 2017-09-26 | 2018-01-16 | 郑州云海信息技术有限公司 | A kind of method and structure of PCB placement-and-routings |
| US20190376796A1 (en) * | 2018-06-06 | 2019-12-12 | Baidu Online Network Technology (Beijing) Co., Ltd. | Method and device for acquiring road track, and storage medium |
| CN110378062A (en) * | 2019-07-26 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of the pin wiring inspection method and relevant apparatus of differential lines |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113378505B (en) | 2023-05-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20120331437A1 (en) | Electronic device and method for checking layout of printed circuit board | |
| US20110004718A1 (en) | System, method, and computer program product for ordering a plurality of write commands associated with a storage device | |
| CN113466733A (en) | Power performance testing method and device, electronic equipment and storage medium | |
| CN112835497A (en) | Method and device for quickly entering electronic whiteboard and storage medium | |
| CN112235949A (en) | Method, device and equipment for digging differential via hole in printed circuit board design | |
| CN115081389B (en) | A printed circuit board wiring inspection method, device, equipment and storage medium | |
| US11599702B2 (en) | Excitation source planning method for electrical simulation and system thereof | |
| US20130007356A1 (en) | Assigning A Classification To A Dual In-line Memory Module (DIMM) | |
| CN115761778A (en) | Document reconstruction method, device, equipment and storage medium | |
| US8781783B2 (en) | System and method for checking ground vias of a controller chip of a printed circuit board | |
| US20230394218A1 (en) | Method and apparatus for calculating equal length of winding differential lines, and device and storage medium | |
| CN111191408A (en) | PCB element layout verification method and device, server and storage medium | |
| CN113378505A (en) | Routing layout adjusting method and device, electronic equipment and storage medium | |
| CN113936232A (en) | Screen fragmentation identification method, device, equipment and storage medium | |
| CN117279213A (en) | Wiring method, flexible circuit board, display device, electronic device, and storage medium | |
| US20140089882A1 (en) | Computing device and method for modularizing power supplies placed on pcb | |
| CN112711051A (en) | Flight control system positioning method, device, equipment and storage medium | |
| CN118093031A (en) | Wiring checking method, wiring checking device, wiring checking equipment and machine-readable storage medium | |
| CN108399128A (en) | A kind of generation method of user data, device, server and storage medium | |
| CN116306410B (en) | Information printing method and device based on tightly coupled memory and hardware verification method | |
| US20130304413A1 (en) | Computing device and method for testing electromagnetic compatiblity of printed circuit board | |
| CN118012819A (en) | Server system, server configuration method, device and medium | |
| CN116974957A (en) | System protection circuit, chip system, reset method, device and storage medium | |
| CN118964164A (en) | A code repair method, device, equipment and medium | |
| KR102086775B1 (en) | Memory module improving data signal integrity |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |