CN113371673B - A hybrid integrated sensing microsystem and its single-chip integrated fabrication method - Google Patents

Abstract

The invention discloses a mixed integrated sensing microsystem and a single chip integrated preparation method thereof, wherein the components of the mixed integrated sensing microsystem comprise a multichannel microsensor, a microsensor signal conditioning circuit, a micro control unit, a radio frequency circuit module, peripheral equipment, a supporting circuit and other servo circuits, all the components are integrated and prepared by adopting a bulk silicon process or an SOI process, and the microsensor, an analog CMOS circuit and a digital CMOS circuit are integrated together in a single chip mode, or part of the components are integrated together in a single chip mode and then integrated with the rest of the components in a system level mode. The method for preparing the single chip of the integrated sensing micro system is based on a partially depleted SOI CMOS process, most of the processing steps of the plane of the micro sensor are completed by utilizing the partially depleted SOI CMOS process, and the processing steps of the rest of the micro sensors are completed after the preparation process of the SOI CMOS process is finished. The integrated sensing micro-system has the technical advantages of multi-channel signal parallel detection, signal remote transmission, high signal-to-noise ratio, low cost, small volume, low power consumption, portability and the like.

Description

A hybrid integrated sensing microsystem and its single-chip integrated fabrication method

technical field

The invention belongs to the field of micro-electromechanical systems (MEMS) and integrated circuits, and particularly relates to a hybrid integrated sensing micro-system and a single-chip integrated preparation method thereof.

Background technique

Since the late 1980s, the rapid development of MEMS technology has made sensors gradually miniaturized and low-cost, and a large number of MEMS sensors are widely used in defense, industry, aerospace, automotive and other fields. In recent years, the rapid development of micro-nano processing technology and integrated circuit technology has made it possible to integrate a variety of micro-sensors, signal conditioning and processing circuits and microprocessors with different functions to form a complex monolithic integrated micro-system. This highly integrated system chip enables the sensor performance to develop in the direction of multi-function, high precision, high sensitivity, high stability, low power consumption and high reliability. It has broad application prospects in military and national defense fields such as identification, broadband communication, and biochemical detection, as well as in civil fields such as consumer electronics, medical care, automobile driving, environmental monitoring, biochemical detection, and industrial control. At the same time, sensors with wireless functions have both long-range and multi-information perception, which can achieve a breakthrough in the collaborative perception mode of networked clusters. , Fast, miniature wireless sensors and their systems to achieve high-sensitivity real-time monitoring and perception of information. The monolithic integration of MEMS sensors and ICs not only realizes the detection of complete device functions, but also lays the foundation for the development of sensors in the direction of intelligence, miniaturization and networking.

With the increasing demand of the integrated micro-system industry, the defense and civil fields have put forward extensive demands for high-performance sensing micro-systems, and the integrated manufacturing technology is also facing great challenges. Silicon on insulator (SOI) is composed of single crystal silicon device layer, SiO2 buried oxide layer and substrate. This material has excellent electrical and mechanical properties, as well as high temperature resistance, radiation resistance and other characteristics. It is the first choice for the preparation of high-performance MEMS sensors, especially piezoresistive microsensors using the high-pressure resistance effect of the single crystal silicon device layer. At present, the monolithic integration of SOI-based MEMS devices and ICs is mainly designed according to the thickness of the device layer. For SOI substrates with thick device layers, CMOS circuits and MEMS devices are directly prepared on the device layer, so this method is actually a kind of Integration technology based on bulk silicon CMOS process. Bulk CMOS has problems such as parasitic effects with the substrate, capacitance loss, latch-up effect, high-temperature leakage current, and short-channel effect, which limit the further improvement of the performance of integrated microsystems. For the SOI material of the thin device layer, the device layer and the buried oxide layer in the circuit area are usually removed, and the CMOS circuit is prepared on a silicon substrate, so the integration process is still an integration technology based on bulk silicon CMOS. This method abandons the excellent performance of SOICMOS in suppressing latch-up effect, short-channel effect, parasitic effect, channel leakage current, crosstalk, etc., and at the same time, removes the surface defects and interface states of the silicon substrate after the device layer and the buried oxide layer are removed. , the climbing of the electrical interconnection between the circuit and the sensor, and the preparation of the circuit and the sensor not at the same level will seriously affect the performance of the integrated microsystem and the reliability of the integrated manufacturing process.

In the 1960s, due to the requirements of the development of military space technology, people began to study SOI technology. It was not until the mid-1990s that people found a low-cost SOI CMOS process, and SOI processing technology developed accordingly. Although most integrated circuits are produced today using traditional bulk CMOS technology, SOI technology presents unique advantages in the field of integrated micro-sensing systems due to its fully isolated structure. SOI technology can effectively isolate the substrate from the device, avoid leakage current caused by the isolation of the diffusion resistance and pn junction of ordinary silicon wafers at high temperatures, and can also avoid parasitic effects and latch-up effects in bulk silicon. . In the military field, in the face of a high radiation environment, the charge of the oxide layer induced by the bulk silicon CMOS process increases, resulting in an interface state, which will not work properly, while the SOI CMOS process will effectively reduce the impact on the device due to the existence of a back gate. performance impact, and therefore higher stability in various extreme cases.

SUMMARY OF THE INVENTION

The integrated micro-sensor system integrates high-sensitivity micro-sensors with signal conditioning, processing, and wireless communication circuits, thereby reducing additional parasitic parameters introduced by interconnects and PCB boards, effectively reducing DC offset voltage and signal paths The extra noise brought by the sensor can realize the high signal-to-noise ratio detection of the micro-sensor signal, as well as the application of multi-function, miniaturization, intelligence, low power consumption, and remote monitoring, which can be used for the integrated sensing micro-system in the field of information detection. Practicalization provides effective means.

In order to achieve the above object, the technical scheme of the present invention comprises the following steps:

A hybrid integrated sensing microsystem, characterized in that the components of the hybrid integrated sensing microsystem include a multi-channel microsensor and a circuit system, and the circuit system includes a microsensor signal conditioning circuit, and peripheral devices and support circuits; or The circuit system includes a micro-sensor signal conditioning circuit, a micro-control unit, and peripheral equipment and support circuits; or the circuit system includes a micro-sensor signal conditioning circuit, a micro-control unit, a radio frequency circuit module, and peripheral equipment and support circuits. The multi-channel micro-sensor performs parallel detection of multi-source information; the micro-sensor signal conditioning circuit performs selection, low-noise amplification, analog-to-digital conversion and noise filtering for the multi-channel micro-sensor signals; the micro-control unit performs the sensing micro-system The data processing, management, storage, and control radio frequency module transmits digital signals and realizes interactive functions with external systems; the radio frequency module is used to realize remote wireless transmission of micro-sensor signals; the peripheral equipment and support circuits are used to implement signal conditioning circuits It communicates with the micro-control unit and between the micro-control unit and the radio frequency module in a serial manner to exchange information, and all the above components are monolithically integrated or integrated at the system level. The hybrid integrated sensing micro-system of the present invention can be prepared based on bulk silicon CMOS process, and can also be prepared based on SOI CMOS process. The integrated sensing micro-system of the invention has the technical advantages of multi-channel signal parallel detection, long-distance signal transmission, high signal-to-noise ratio, low cost, small size, low power consumption, easy portability and the like.

The invention also provides a single-chip integrated preparation method of a hybrid integrated sensing microsystem, which is characterized in that the integrated sensing microsystem is prepared by a bulk silicon process or an SOI process, and a multi-channel microsensor, an analog CMOS circuit and a digital CMOS circuit are integrated into a single chip. The chips are integrated together. If the bulk silicon process is used, the microsensor and the CMOS circuit are prepared on the silicon substrate. If the SOI silicon wafer is used, the device layer of the SOI silicon wafer is used as the sensitive layer of the microsensor and the CMOS circuit. The active area, and the buried oxide layer of the SOI silicon wafer is used as the lower protective layer of the micro-sensor and circuit. Most of the plane processing steps of the micro-sensor are completed by the SOI CMOS process, and other SOI CMOS processes are not available in the CMOS circuit preparation process. After the preparation process of the SOI CMOS is completed, the processing steps of the remaining micro-sensors are completed to release the micro-sensor structure. The micro-sensor plane fabrication process using partially depleted SOI CMOS includes: active area definition, ion implantation, deposition of protective layer on the micro-sensor force-sensitive resistor, ohmic contact, metal interconnection line definition and pad definition. The silicon island isolation process defines the active area of the sensor and the SOI CMOS circuit at the same time; the partial electrical interconnection between the force-sensitive resistors of the micro-sensor, the protection ring of the force-sensitive resistance and the force-sensitive resistance are formed by using the channel in the SOI CMOS process or the ion implantation conditions of the adjusted threshold value. resistance. Using the heavily doped source-drain implantation and self-aligned silicide in the SOICMOS process to prepare the doping of single crystal silicon in the contact holes of the microsensor to achieve ohmic contact; using the SOI CMOS process to have metal interconnects to realize the force-sensitive resistance Closed connection between and interconnection with SOICMOS signal conditioning circuit. The release micro sensor structure is to remove the substrate silicon under the micro sensor, including removing the substrate silicon from the front side, or removing the substrate silicon from the back side, the buried oxide layer of the SOI silicon wafer is used as the self-stop layer for release, and the The removal method is to use dry etching of the silicon substrate to release the microsensor structure, or to use wet etching of the silicon substrate to release the microsensor structure.

The present invention has the following beneficial effects:

The integrated sensing micro-system of the invention has the technical advantages of multi-channel signal parallel detection, long-distance signal transmission, high signal-to-noise ratio, low cost, small size, low power consumption, easy portability, etc., and can be used for the integrated sensing micro-system in information detection. It provides an effective means for the practical application of the field, and is a new technology to realize the intelligent sensor. The invention also proposes a single-chip integrated manufacturing process for a sensing microsystem based on partially depleted SOI CMOS. On the one hand, SOI CMOS technology can avoid parasitic effects, latch-up effects, high-temperature leakage currents, etc. between bulk silicon CMOS and the substrate. problem, can greatly improve the performance of the sensing microsystem. On the other hand, the buried oxide layer of the SOI substrate provides an ideal substrate isolation layer, which provides many conveniences for the release of the microsensor structure while effectively reducing leakage. In addition, the advantages of SOI materials in high temperature resistance, low pressure and low power consumption can greatly improve the application ability of the sensor to harsh environments and expand the application scope of the sensor. The sensing microsystem integration scheme proposed by the project has a wide range of applicability. In addition to being applied to the development of the sensing microsystem proposed in this patent, it can also be widely applied to the development of other types of sensing microsystems.

Description of drawings

FIG. 1 is a basic structural block diagram of an integrated sensing microsystem according to an embodiment of the present invention.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

As shown in FIG. 1 , the hybrid integrated sensor micro-system of the present invention comprises a micro-sensor signal conditioning circuit, a micro-control unit (MCU), a radio frequency (RF) circuit module, a power management and a clock and other servo circuit components. The microsensor signal conditioning circuit is an analog application specific integrated circuit (ASIC), including a time division or frequency division multiplexer (MUX), an instrumentation operational amplifier, an analog-to-digital conversion circuit (ADC), a filter, and a servo circuit. The multi-channel signal selector enables the subsequent circuit to perform time-division or frequency-division selection on the micro-sensor signals to be processed, the instrumentation operational amplifier performs low-noise amplification on the analog electrical signal output by the MUX, and the ADC converts the analog signal output by the instrumentation operational amplifier into a Pulse width modulated digital signal, filter is used to filter out out-of-band quantization noise, servo module provides reference voltage, current source and clock signal, instrumentation operational amplifier and ADC control signal sampling frequency through clock signal, and amplifier module requires band gap Reference and current sources provide accurate offset voltage and temperature compensation.

The MUC is a data processing and control circuit, a digital circuit, mainly composed of digital signal processing (DSP), non-volatile memory (ROM), volatile memory (RAM), peripheral devices and support circuits. The CPU Perform arithmetic operations, manage data flow and generate control signals according to the written sequence of instructions, non-volatile memory is used to store the program of the microcontroller unit, volatile memory (i.e. RAM) is used for temporary data storage, peripherals help the microcontroller The hardware module that realizes the interaction between the unit and the external system, through the format conversion of the communication protocol, controls the radio frequency module to transmit digital signals. The MCU is designed to handle two distinct signal paths: the control path and the data path, the control path of the MCU controls the dominant microsensor, multiplexer, ADC and RF transmitter with antenna all in a finite state machine (FSM) Controlled in an orderly fashion to save power consumption in power management. The data path of the MCU compresses the micro-sensor data, reads the 1-bit code stream and clock output by the ADC from the chip, completes extraction and filtering through digital signal processing (DSP), and finally obtains 24-bit output data. The interface is sent to the radio frequency (RF) module, which is responsible for sending sensor output data to the outside world. The peripheral devices and support circuits include but are not limited to serial peripheral interface circuits, which are used to implement serial communication between the ADC signal and the micro-control unit, and between the micro-control unit and the radio frequency module to exchange information;

The radio frequency module includes a transceiver and an antenna, and is mainly composed of functional modules such as a radio frequency transceiver, a frequency generator, a crystal oscillator, and a modem. Remote wireless transmission; the radio frequency module is controlled by the micro-control unit to realize the low-power operation of transmission, reception, wake-up and registration of the micro-sensor signal, and the transmission and reception power, working channel and communication data rate of the radio frequency module can be configured, It comes with some communication protocols of the link layer and configures a small number of parameter registers.

All the components of the present invention can be integrated into a single chip using bulk silicon technology or SOI technology.

The present invention takes a piezoresistive integrated micro-cantilever sensor single-chip integration based on a partially depleted SOI CMOS process as an example, including but not limited to the following process steps:

a) Partially depleted SOI CMOS process, using single-polish P-type [110] crystal orientation SOI silicon wafer, the thickness of the device layer is 340nm, and the thickness of buried oxygen is 400nm. The device layer serves as the active region of the micro-sensor force-sensitive resistor and the CMOS device at the same time, and the buried oxygen layer serves as the lower protective layer of the device and the stop layer for releasing the micro-cantilever beam sensor process.

b) After the SOI silicon wafer is routinely cleaned, a silicon dioxide layer and a silicon nitride layer are deposited. The silicon nitride is used as a mask for etching silicon, and the silicon dioxide in the intermediate layer can be used for subsequent implantation barriers.

c) The active area is defined by photolithography, including the CMOS circuit area and the micro-cantilever sensor area, and the two parts are placed as far away as possible to avoid the subsequent micro-sensor process from affecting the performance and reliability of the CMOS circuit. Then, the silicon nitride, silicon dioxide layer and single crystal silicon device layer are etched to form a silicon island structure.

d) depositing a silicon dioxide insulating layer to form complete area isolation between the silicon island isolation structures to prevent mutual interference between the CMOS circuit and the microsensor device.

e) The chemical mechanical polishing process is used to flatten the surface of the device and form shallow trench isolation, and finally complete the definition of the active region.

f) The hard mask silicon nitride is removed, and the exposed silicon dioxide can be used as a blocking layer for subsequent channel ion implantation.

g) Photolithography, ion implantation to form N well region and P-channel region, in order to form a uniform distribution, the method of multiple implantation with different energy can be used to adjust the threshold voltage of SOI CMOS devices with low energy and low dose implantation. The ion implantation in the N-well region is simultaneously performed on the force-sensitive resistance region to form an N+ ring, so as to reduce the leakage current of the force-sensitive resistance.

h) Remove silicon dioxide, re-thermally oxidize to generate a gate oxide layer, and adjust the thickness of the gate oxide according to the designed threshold voltage. Then polysilicon is deposited by LPCVD, and phosphorus ions are implanted to form N+ polysilicon gates. Photolithography defines polysilicon gates, polysilicon leads, etch polysilicon, and then perform polysilicon annealing.

i) Photolithography, performing LDD implantation on PMOS and NMOS at the same time to suppress short channel effects.

j) After LPCVD deposition of silicon dioxide, the silicon dioxide sidewall spacer is formed by etching it away, which is used to block the lateral scattering of the source-drain implanted ions.

k) Perform source-drain implantation after photolithography, so that the source-drain junction is deep to the buried oxide layer, and at the same time, heavily doped interconnect lines are defined. The process also implants the body contact region at the same time, improving the body contact resistance. A rapid thermal annealing treatment is then performed to improve the ion distribution.

l) Define the force-sensitive resistor pattern, and adjust the resistance of the force-sensitive resistor by ion implantation. In order to ensure that the position of the force-sensitive resistor is close to the surface of the micro-sensor, and to ensure high detection sensitivity, the implantation dose and implantation energy need to be adjusted.

m) In order to realize metal interconnection, a silicon dioxide passivation layer is deposited first, and then photolithography is performed, and the silicon dioxide passivation layer is etched by reactive ion to form a contact hole.

n) Sputtering metal Ti/TiN. As a barrier layer, metal W has good filling performance and step coverage. After CVD deposition of W, CMP is used to planarize metal W and form metal interconnects.

o) After completing multiple metal processes, a thicker dielectric layer is formed on the surface of the microsensor and in the area of the reaction pool, which will affect the sensitivity of the microsensor. Therefore, the dielectric layer in this region needs to be thinned, and finally the overall thickness of the microsensor is about 1 μm.

p) Perform thick photolithography to define the micro-sensor structure, BHF etch the passivation layer and the buried oxide layer, and RIE etch the transition layer at the interface between the buried oxide and the silicon substrate. Finally, an anisotropic/isotropic dry etching process is used to remove the substrate silicon under the microsensor to release the microsensor.

To sum up, the above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (3)

1. A single chip integrated preparation method of a hybrid integrated sensing micro system comprises the steps that components of the hybrid integrated sensing micro system comprise a multi-channel micro sensor and a circuit system, wherein the circuit system comprises a micro sensor signal conditioning circuit, peripheral equipment and a supporting circuit; or the circuitry comprises a microsensor signal conditioning circuit, a micro-control unit, and peripherals and support circuits; or the circuit system comprises a micro-sensor signal conditioning circuit, a micro-control unit, a radio frequency circuit module, peripheral equipment and a supporting circuit; the multi-channel microsensor performs parallel detection on multi-source information; the micro-sensor signal conditioning circuit is used for selecting, amplifying low noise, converting analog to digital and filtering noise of a multi-channel micro-sensor signal; the micro control unit processes, manages and stores data of the sensing micro system, controls the radio frequency module to transmit digital signals and realizes interaction function with an external system; the radio frequency module is used for realizing remote wireless transmission of micro-sensor signals; the peripheral equipment and the supporting circuit are used for realizing serial communication between the signal conditioning circuit and the micro control unit and between the micro control unit and the radio frequency module to exchange information, and all the components are integrated in a single chip or in a system level, and the single chip integrated sensing micro system is characterized in that the single chip integrated sensing micro system is prepared based on a partially depleted SOI CMOS process, most of plane processing steps of the micro sensor are completed by utilizing the partially depleted SOI CMOS process, a micro sensor plane process which is not provided by other SOI CMOS processes is added in the preparation process of the CMOS circuit system, after the preparation process of the SOI CMOS is finished, the processing steps of the rest micro sensor are completed, and the structure of the micro sensor is released, and the method comprises the following process steps:

a) Based on a partially depleted SOI CMOS process, an SOI silicon wafer with a P-type and <110> crystal orientation device layer is adopted, and the thickness of the device layer is larger than 200nm;

b) After an SOI silicon chip is cleaned conventionally, a silicon dioxide layer and a silicon nitride layer are deposited, the silicon nitride is used as a mask for etching silicon, and the silicon dioxide is used for a subsequent ion implantation barrier layer;

c) Photoetching and defining an active region comprising a CMOS circuit region and a micro-sensor active region, and then etching silicon nitride, a silicon dioxide layer and a single crystal silicon device layer to form an isolated silicon island structure;

d) Depositing a silicon dioxide insulating layer to form complete area isolation between the isolated silicon island structures to prevent mutual interference between the CMOS circuit and the microsensor;

e) Flattening the surface of the silicon wafer by using a chemical mechanical polishing process, and forming shallow trench isolation to finish the definition of an active region;

f) Removing the silicon nitride hard mask, wherein the exposed silicon dioxide is used for a subsequent channel ion implantation barrier layer;

g) Photoetching, injecting phosphorus ions to form an N well region and a P-channel region, wherein the ions in the N well region are injected into the force-sensitive resistor region at the same time to form an N + ring so as to reduce the leakage current of the force-sensitive resistor;

h) Removing silicon dioxide, performing thermal oxidation again to generate a gate oxide layer, adjusting the thickness of the gate oxide layer according to the designed threshold voltage, then depositing polycrystalline silicon by LPCVD (low pressure chemical vapor deposition), injecting phosphorus ions to form an N + polycrystalline silicon gate, defining the polycrystalline silicon gate and a polycrystalline silicon lead by photoetching, etching the polycrystalline silicon, and then performing polycrystalline silicon annealing;

i) Photoetching, and carrying out LDD injection on the PMOS and the NMOS at the same time to inhibit a short channel effect;

j) Depositing silicon dioxide by LPCVD (low pressure chemical vapor deposition) and etching to form a silicon dioxide side wall for blocking the transverse scattering of source-drain implanted ions;

k) Performing source-drain implantation after photoetching to enable the source-drain junction depth to reach a buried oxide layer, performing ion implantation on a body contact area of a semi-depletion SOI CMOS device and a heavily doped monocrystalline silicon interconnection line of a force sensitive resistor to improve the body contact resistor, and then performing rapid thermal annealing to improve the ion distribution;

l) defining a force-sensitive resistor graph, and injecting boron ions to adjust the resistance value of the force-sensitive resistor;

m) depositing a silicon dioxide passivation layer, then carrying out photoetching, and etching the silicon dioxide passivation layer by reactive ions to form a contact hole;

n) sputtering Ti/TiN to serve as a barrier layer and W to serve as a metal interconnection line, and then flattening the metal layer by utilizing CMP to form the metal interconnection line;

o) thinning the CMOS process dielectric layer deposited in the micro-sensor area to improve the sensitivity of the micro-sensor;

p) carrying out thick photoresist photoetching, defining a microsensor structure, corroding BHF (BHF) and etching the thinned dielectric layer and the thinned buried oxide layer by RIE (reactive ion etching);

q) removing the substrate silicon under the microsensor, releasing the microsensor structure.

2. The method for single chip integrated fabrication of a hybrid integrated sensor microsystem as claimed in claim 1, wherein the release microsensor structure in step q) removes the substrate silicon from the front side or from the back side, the buried oxide layer of the SOI silicon wafer acting as a release self-stop layer.

3. The method for single-chip integrated fabrication of a hybrid integrated sensor microsystem as defined in claim 2, wherein the method for removing the substrate silicon under the microsensor is dry etching the substrate silicon release microsensor structure using isotropic/anisotropic bonding, or wet etching the substrate silicon release microsensor structure.

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