CN113364437A - Method for realizing ultra-low power consumption high-speed comparator circuit - Google Patents
Method for realizing ultra-low power consumption high-speed comparator circuit Download PDFInfo
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- CN113364437A CN113364437A CN202110649693.7A CN202110649693A CN113364437A CN 113364437 A CN113364437 A CN 113364437A CN 202110649693 A CN202110649693 A CN 202110649693A CN 113364437 A CN113364437 A CN 113364437A
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- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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Abstract
The invention discloses a method for realizing an ultra-low power consumption high-speed comparator circuit, which relates to the field of integrated circuits and comprises a comparator and a latch; the comparator comprises an input sampling amplification geminate transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor; the latch comprises a comparison pre-amplification pair transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor; in the sampling phase, the latch is in a reset state and has no power consumption; during the hold phase, the latch has no power to ground path and no power consumption. The invention has simple design and easy realization, combines the characteristics of high speed and low power consumption, and can ensure that the system is always in a linear amplification area by introducing a feedback system.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an ultra-low power consumption high-speed comparator circuit implementation method.
Background
At present, the integrated circuit integration level is higher and higher, and the requirements on the module speed and the power consumption of chip integration are higher and higher. In particular, the performance index requirements of the quantization process from analog signals to digital signals and the quantization from analog signals to digital signals are higher and higher. As shown in fig. 1, the conventional comparator design has a disadvantage that a VDD to VSS path exists in a sampling stage of a preamplifier (Preamp) and a Latch (Latch) during operation, so that a large current exists according to a design, and a large defect exists in a low power consumption application field.
Therefore, those skilled in the art are devoted to develop an ultra-low power consumption high speed comparator circuit implementation method, which can achieve high speed slew rate at ultra-low power consumption.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the technical problem to be solved by the present invention is to achieve high speed requirements at the expense of power consumption for analog to digital quantization.
In order to achieve the above object, the present invention provides a method for implementing an ultra-low power consumption high speed comparator circuit, which comprises a comparator and a latch; the comparator comprises an input sampling amplification geminate transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor; the latch comprises a comparison pre-amplification pair transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor; the input sampling amplification pair transistor is connected with a first differential input voltage and a second differential input voltage; the comparison pre-amplification pair transistor is connected with a first differential output voltage and a second differential output voltage; a first clock control signal is connected with the grid electrode of the first PMOS transistor and the grid electrode of the third NMOS transistor; the second clock control signal is connected with the grid electrode of the sixth NMOS transistor; the source electrode of the first PMOS transistor, the source electrode of the third PMOS transistor, the source electrode of the fourth PMOS transistor, the source electrode of the fifth PMOS transistor and the source electrode of the sixth PMOS transistor are connected with a power supply; the source electrode of the third NMOS transistor, the source electrode of the fourth NMOS transistor and the source electrode of the fifth NMOS transistor are grounded.
Further, the input sampling amplification pair transistors are a first NMOS transistor and a second NMOS transistor; the comparison pre-amplification pair transistors are a seventh PMOS transistor and an eighth PMOS transistor.
Further, the gate of the first NMOS transistor is connected to the first differential input voltage, and the gate of the second NMOS transistor is connected to the second differential input voltage; the source electrode of the first NMOS transistor, the source electrode of the second NMOS transistor and the drain electrode of the first PMOS transistor are connected with the drain electrode of the third NMOS transistor; the drain electrode of the first NMOS transistor and the drain electrode of the second PMOS transistor are connected with the drain electrode of the third PMOS transistor, and the connecting end outputs the first differential output voltage of the amplifier; the drain electrode of the second NMOS transistor and the source electrode of the second PMOS transistor are connected with the drain electrode of the fourth PMOS transistor, and the connecting end outputs the second differential output voltage of the amplifier; and the grid electrode of the second PMOS transistor and the grid electrode of the third PMOS transistor are connected with the grid electrode of the fourth PMOS transistor.
Further, the drain of the fourth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the gate of the fourth NMOS transistor and the gate of the fifth PMOS transistor are connected to the drain of the sixth NMOS transistor; the drain of the fifth NMOS transistor is connected with the drain of the eighth PMOS transistor, and the gate of the fifth NMOS transistor and the gate of the sixth PMOS transistor are connected with the source of the sixth NMOS transistor; the drain electrode of the fifth PMOS transistor is connected with the source electrode of the seventh PMOS transistor; the drain electrode of the sixth PMOS transistor is connected with the source electrode of the eighth PMOS transistor; the gate of the seventh PMOS transistor is connected to the second differential output voltage, and the gate of the eighth PMOS transistor is connected to the first differential output voltage.
Further, the first clock control signal is opposite in phase to the second clock control signal.
Further, the method comprises a sampling stage, a comparison stage and a holding stage; the sampling stage is that the comparator collects signals, the comparison stage is that the comparator compares and amplifies the signals collected in the sampling stage, and the holding stage is that the latch converts the comparison result in the comparison stage into a quantized signal.
Further, in the sampling phase, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are turned on, the third NMOS transistor is turned off, which is equivalent to that the source and the drain of the first NMOS transistor and the source and the drain of the second NMOS transistor are connected to a power supply, and the first NMOS transistor and the second NMOS transistor convert the first differential input voltage and the second differential input voltage into charges respectively for storage.
Further, in the sampling phase, the second PMOS transistor is turned on to reset the first differential output voltage and the second differential output voltage to the same voltage.
Further, in the comparison stage, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are turned off, and the third NMOS transistor is turned on, which is equivalent to grounding of the source of the first NMOS transistor and the source of the second NMOS transistor.
Further, during the sampling phase, the latch is in a reset state.
Compared with the prior art, the invention has the following obvious substantive characteristics and obvious advantages:
the design is simple, the realization is easy, the characteristics of high speed and low power consumption are combined, and the system can be ensured to be always in a linear amplification area by introducing a feedback system.
The conception, the specific structure and the technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, the features and the effects of the present invention.
Drawings
FIG. 1 is a circuit schematic of a conventional comparator;
FIG. 2 is a functional block diagram of a preferred embodiment of the present invention;
FIG. 3 is a circuit schematic of a preferred embodiment of the present invention;
FIG. 4 is a timing diagram of the comparator output signals in accordance with a preferred embodiment of the present invention;
fig. 5 is an equivalent circuit diagram of the sampling phase of a preferred embodiment of the present invention.
Detailed Description
The technical contents of the preferred embodiments of the present invention will be more clearly and easily understood by referring to the drawings attached to the specification. The present invention may be embodied in many different forms of embodiments and the scope of the invention is not limited to the embodiments set forth herein.
In the drawings, structurally identical elements are represented by like reference numerals, and structurally or functionally similar elements are represented by like reference numerals throughout the several views. The size and thickness of each component shown in the drawings are arbitrarily illustrated, and the present invention is not limited to the size and thickness of each component. The thickness of the components may be exaggerated where appropriate in the figures to improve clarity.
As shown in fig. 2, it is a functional structure diagram of a preferred embodiment of the present invention, and is composed of two parts: a comparator, a latch; the input port of the comparator comprises a first differential input voltage Vinn, a second differential input voltage Vinn and a first clock control signal CLK, and the output port comprises a first differential output voltage Voutn and a second differential output voltage Voutp; the latch comprises two differential output ports DP, DN, the input ports Dinp, Dinn of the latch being directly connected to the comparator differential output ports. The latch port further includes a second clock control signal CLK' and the clock control signals of the comparator and the latch are in opposite phases.
FIG. 3 is a circuit schematic of a comparator and latch of the present invention, the comparator comprising: the first NMOS transistor MN0, the second NMOS transistor MN1 form an input sampling amplification paired transistor, a third NMOS transistor MN2, a first PMOS transistor MP0, a third PMOS transistor MP2, a fourth PMOS transistor MP3 and a second PMOS transistor MP1 which are used as reset switches; the latch component comprises: the seventh PMOS transistor MP6 and the eighth PMOS transistor MP7 form a comparison pre-amplification pair transistor, and the fifth PMOS transistor MP4, the sixth PMOS transistor MP5, the fourth NMOS transistor MN3, the fifth NMOS transistor MN4, and the sixth NMOS transistor MN5 serve as reset switches.
FIG. 4 is a timing diagram of the output signal of the comparator for one clock cycle, including tSampling、tComparison、tHoldingThree stages. t is tSamplingStart the comparator to collect signal, tComparisonThe comparator starts to compare and amplifies tSamplingSignal acquired in time period, tHoldingHandle tComparisonThe result of the time period comparison holds the quantized signal (1 refers to the power supply voltage VDD, 0 refers to ground) that is converted into 0\ 1.
Fig. 5 is an equivalent circuit diagram of the sampling phase, at which time the sources and drains of the input sampling amplifying pair of the first NMOS transistor MN0, the second NMOS transistor MN1 are connected to the power supply through the first PMOS transistor MP0, the third PMOS transistor MP2, the fourth PMOS transistor MP 3.
The working principle of the embodiment is as follows:
tsamplingReferring to fig. 5, the first PMOS transistor MP0, the second PMOS transistor MP1, the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are turned on, and the second PMOS transistor MP1 is turned on to reset the voltages at the two ends of the first differential output voltage Voutn and the second differential output voltage Voutp to the same voltage, and the sources and the drains of the first NMOS transistor MN0 and the second NMOS transistor MN1 of the pair of input sampling and amplifying transistors are connected to the power supply through the first PMOS transistor MP0, the third PMOS transistor MP2 and the fourth PMOS transistor MP 3. t is tSamplingThe first NMOS transistor MN0 and the second NMOS transistor MN1 are equivalent to a capacitor CMN0、CMN1Converting the voltage information of the first differential input voltage Vinn and the second differential input voltage Vinp into charges to be stored in CMN0、CMN1The amount of stored charge is shown in equation 1 and equation 2.
Qp＝(Vinp-VDD)×CMN0Equation 1
Qn＝(Vinn-VDD)×CMN1Equation 2
tComparisonIn the comparison and pre-amplification stage, the first PMOS transistor MP0, the second PMOS transistor MP1, the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are turned off to be in a high-impedance state; the drains of the first and second NMOS transistors MN0 and MN1 are connected to the drains of the third and fourth PMOS transistors MP2 and MP3, and the sources of the first and second NMOS transistors MN0 and MN1 are connected to the drain of the third NMOS transistor MN 2. Since the third NMOS transistor MN2 is turned on and is low-impedance in this state, the sources of the first and second NMOS transistors MN0 and MN1 are grounded. To sum upT is describedComparisonIn the stage, the drains of the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are connected to the high impedance, and the sources are connected to the ground. Since the source impedances of the third and fourth PMOS transistors MP2 and MP3 are small, the impedance at t is setComparisonStage will soon hold tSamplingThe charge stored by the stage is quickly discharged.
Q ═ I × t equation 4
In the above equation, R is the equivalent impedance of MN2 after closing, and V is tComparisonThe voltage at the source and drain of stage MN0 and MN1, Q is equal to QP、QNAnd t is t in FIG. 5ComparisonTime.
So that it can be seen from equation 6 that at tComparisonThe smaller the comparison time and the faster the comparison speed of the comparator as long as the on-resistance of the third NMOS transistor MN2 is sufficiently small. In the whole working process, the comparator is transferred by charges, a current path is not formed from a power supply to the ground, and the power consumption of the module is the integral of the charge quantity stored in each sampling.
Comparator tSamplingThe phase latch is in a reset state; comparator tComparisonThe phase latch is pre-amplified by the seventh PMOS transistor MP6 and the eighth PMOS transistor MP7, and the comparison result is transmitted to a latch formed by the fifth PMOS transistor MP4, the sixth PMOS transistor MP5, the fourth NMOS transistor MN3 and the fifth NMOS transistor MN4, and the quantization result is output together with DP and DN.
The seventh PMOS transistor MP6 and the eighth PMOS transistor MP7 of the pre-amplifying module of the present invention are put into the latch at tSamplingThe stage turns off the latch, so that the latch can be avoided from being at tSamplingThe phases consume power. t is tSamplingThe time t obtained by the formula 6 is short so that the generated power consumption can be ignored when entering tHoldingThe hold phase latch has no power to ground path and therefore no power consumption.
The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.
Claims (10)
1. A method for realizing an ultra-low power consumption high-speed comparator circuit is characterized by comprising a comparator and a latch;
the comparator comprises an input sampling amplification geminate transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor;
the latch comprises a comparison pre-amplification pair transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor;
the input sampling amplification pair transistor is connected with a first differential input voltage and a second differential input voltage;
the comparison pre-amplification pair transistor is connected with a first differential output voltage and a second differential output voltage;
a first clock control signal is connected with the grid electrode of the first PMOS transistor and the grid electrode of the third NMOS transistor;
the second clock control signal is connected with the grid electrode of the sixth NMOS transistor;
the source electrode of the first PMOS transistor, the source electrode of the third PMOS transistor, the source electrode of the fourth PMOS transistor, the source electrode of the fifth PMOS transistor and the source electrode of the sixth PMOS transistor are connected with a power supply;
the source electrode of the third NMOS transistor, the source electrode of the fourth NMOS transistor and the source electrode of the fifth NMOS transistor are grounded.
2. The ultra-low power high speed comparator circuit implementation of claim 1,
the input sampling amplification pair transistors are a first NMOS transistor and a second NMOS transistor;
the comparison pre-amplification pair transistors are a seventh PMOS transistor and an eighth PMOS transistor.
3. The ultra-low power high speed comparator circuit implementation of claim 2,
the grid electrode of the first NMOS transistor is connected with the first differential input voltage, and the grid electrode of the second NMOS transistor is connected with the second differential input voltage;
the source electrode of the first NMOS transistor, the source electrode of the second NMOS transistor and the drain electrode of the first PMOS transistor are connected with the drain electrode of the third NMOS transistor;
the drain electrode of the first NMOS transistor and the drain electrode of the second PMOS transistor are connected with the drain electrode of the third PMOS transistor, and the connecting end outputs the first differential output voltage of the amplifier;
the drain electrode of the second NMOS transistor and the source electrode of the second PMOS transistor are connected with the drain electrode of the fourth PMOS transistor, and the connecting end outputs the second differential output voltage of the amplifier;
and the grid electrode of the second PMOS transistor and the grid electrode of the third PMOS transistor are connected with the grid electrode of the fourth PMOS transistor.
4. The ultra-low power high speed comparator circuit implementation of claim 3,
the drain electrode of the fourth NMOS transistor is connected with the drain electrode of the seventh PMOS transistor, and the grid electrode of the fourth NMOS transistor and the grid electrode of the fifth PMOS transistor are connected with the drain electrode of the sixth NMOS transistor;
the drain of the fifth NMOS transistor is connected with the drain of the eighth PMOS transistor, and the gate of the fifth NMOS transistor and the gate of the sixth PMOS transistor are connected with the source of the sixth NMOS transistor;
the drain electrode of the fifth PMOS transistor is connected with the source electrode of the seventh PMOS transistor;
the drain electrode of the sixth PMOS transistor is connected with the source electrode of the eighth PMOS transistor;
the gate of the seventh PMOS transistor is connected to the second differential output voltage, and the gate of the eighth PMOS transistor is connected to the first differential output voltage.
5. The ultra-low power high speed comparator circuit implementation method of claim 4, wherein the first clock control signal is opposite in phase to the second clock control signal.
6. The ultra-low power consumption high speed comparator circuit implementation method of claim 5, comprising a sampling phase, a comparison phase, a holding phase; the sampling stage is that the comparator collects signals, the comparison stage is that the comparator compares and amplifies the signals collected in the sampling stage, and the holding stage is that the latch converts the comparison result in the comparison stage into a quantized signal.
7. The method of claim 6, wherein in the sampling phase, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are turned on, the third NMOS transistor is turned off, which is equivalent to a power source connected to a source and a drain of the first NMOS transistor and a source and a drain of the second NMOS transistor, and the first NMOS transistor and the second NMOS transistor respectively convert the first differential input voltage and the second differential input voltage into a charge for storage.
8. The ultra-low power consumption high speed comparator circuit implementation method of claim 7, wherein during the sampling phase, the second PMOS transistor is turned on to reset the first differential output voltage and the second differential output voltage to a same voltage.
9. The method of claim 6, wherein in the comparison phase, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are turned off, and the third NMOS transistor is turned on, which is equivalent to grounding of the source of the first NMOS transistor and the source of the second NMOS transistor.
10. The ultra-low power high speed comparator circuit implementation of claim 6, wherein during the sampling phase, the latch is in a reset state.
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| CN202750074U (en) * | 2012-04-20 | 2013-02-20 | 西安华迅微电子有限公司 | High-speed comparator |
| CN105743507A (en) * | 2016-02-02 | 2016-07-06 | 东南大学 | Low-power-consumption comparator applied to pipelined ADC |
| CN105761748A (en) * | 2016-02-23 | 2016-07-13 | 宁波大学 | Static random access memory with defense differential power analysis function |
| CN106209035A (en) * | 2016-07-13 | 2016-12-07 | 电子科技大学 | A kind of two stage comparator |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
| US20200389160A1 (en) * | 2017-05-02 | 2020-12-10 | King Abdullah University Of Science And Technology | Strongarm latch comparator and method |
| US20200412353A1 (en) * | 2018-03-22 | 2020-12-31 | No.24 Research Institute Of China Electronics Technology Group Corporatio | High-speed and low-noise dynamic comparator |
| CN112332819A (en) * | 2020-11-12 | 2021-02-05 | 重庆百瑞互联电子技术有限公司 | Two-stage low-power-consumption high-speed comparator |
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- 2021-06-10 CN CN202110649693.7A patent/CN113364437B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202750074U (en) * | 2012-04-20 | 2013-02-20 | 西安华迅微电子有限公司 | High-speed comparator |
| CN105743507A (en) * | 2016-02-02 | 2016-07-06 | 东南大学 | Low-power-consumption comparator applied to pipelined ADC |
| CN105761748A (en) * | 2016-02-23 | 2016-07-13 | 宁波大学 | Static random access memory with defense differential power analysis function |
| CN106209035A (en) * | 2016-07-13 | 2016-12-07 | 电子科技大学 | A kind of two stage comparator |
| US20200389160A1 (en) * | 2017-05-02 | 2020-12-10 | King Abdullah University Of Science And Technology | Strongarm latch comparator and method |
| US20200412353A1 (en) * | 2018-03-22 | 2020-12-31 | No.24 Research Institute Of China Electronics Technology Group Corporatio | High-speed and low-noise dynamic comparator |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
| CN112332819A (en) * | 2020-11-12 | 2021-02-05 | 重庆百瑞互联电子技术有限公司 | Two-stage low-power-consumption high-speed comparator |
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