CN113363272B - Photosensitive array, manufacturing method and imaging device - Google Patents

Abstract

The invention relates to a photosensitive array, a manufacturing method, and an imaging device. Each pixel area in the photosensitive array corresponds to a substrate lead-out area and is connected to the substrate in the corresponding substrate lead-out area. The multi-column pixel areas include two adjacent ones with opposite charge reading areas and opposite photosensitive areas. Column pixel areas, a substrate lead-out area corresponding to each pixel area in the two adjacent column pixel areas is provided in the column gap, through the substrate lead-out area, the corresponding A voltage is applied to the substrate of the pixel area to facilitate equipotential operation, and in the two adjacent columns of pixel areas, the photosensitive areas of each pixel area in the same column are separated by a full isolator that runs through the substrate in the thickness direction. Reduce crosstalk. The photosensitive array can be obtained using the manufacturing method of the present invention. The imaging device includes the above-mentioned photosensitive array.

Description

Photosensitive array and manufacturing method, imaging device

Technical field

The present invention relates to the field of photosensitive technology, and in particular to a photosensitive array and a manufacturing method and an imaging device.

Background technique

The currently applied photosensitive technologies can be distinguished by principle, including CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor). Compared with CCD, CMOS has faster imaging speed and better system integration capabilities. Lower power consumption can be achieved. However, each pixel in the photosensitive array of an image sensor implemented using CMOS usually includes at least one photosensitive diode and three to six transistors, so that the photosensitive area occupies a small proportion. With the development of technology, the demand for increasing the number of pixels per unit area has become more urgent. Therefore, the area of a single pixel is designed to be smaller and smaller. The full well charge of CMOS pixels is low, causing the photosensitive array to face a decrease in sensitivity and dynamic range. The problem.

Chinese patent CN102938409A discloses a dual-transistor photodetector based on a composite dielectric gate MOSFET. In the photosensitive detector, each pixel includes a photosensitive transistor (also called a MOS capacitor) mainly used for light sensing and a photosensitive transistor used for reading the amount of photogenerated charges. Read transistor. The substrate areas corresponding to the MOS capacitor and the read transistor are separated by shallow trench isolation (STI), and both include a bottom insulating medium, an optoelectronic storage layer, a top insulating medium and a control gate formed sequentially on the substrate. The /drain region is provided in the substrate on one side of the read transistor. The optoelectronic storage layer between the MOS capacitor and the read transistor is connected. By controlling the read transistor, the amount of photogenerated charge entering the optoelectronic storage layer from the substrate on one side of the MOS capacitor during the exposure process can be read. The production of the above-mentioned photosensitive detector can be compatible with the integrated circuit manufacturing process, and compared with CCD and CMOS, it can achieve a higher signal-to-noise ratio and a higher full well charge under the same pixel size, so it has broad application prospects.

During the process of generating photogenerated charges through exposure of the above-mentioned photosensitive detector, a certain bias voltage (about -20V~0V) is applied to the substrate, and the substrate of each pixel is maintained at the same potential. At the same time, settings need to be set between adjacent pixels. Appropriate isolation structure to avoid photogenerated charge migration and prevent cross talk. In order to obtain a smaller-sized photosensitive array (the radial size of the pixel area is, for example, less than 1 μm, and accordingly, the spacing between pixels is also small), there is currently a lack of substrates that can effectively reduce crosstalk and at the same time facilitate application of each pixel. voltage to perform equipotential operation of the array structure.

Contents of the invention

In order to achieve photosensitivity based on the above-mentioned pixel structure including a MOS capacitor and a read transistor, crosstalk between pixels is as small as possible without affecting the application of voltage to the substrate of each pixel to facilitate equipotential operation, the present invention provides A photosensitive array and a manufacturing method, and an imaging device are also provided.

On the one hand, the present invention provides a photosensitive array. The photosensitive array includes a substrate and an isolation structure disposed in the substrate; the substrate has a plurality of pixel areas arranged in rows and columns and distributed in the plurality of pixel areas. The substrate lead-out area between the pixel areas. Each of the pixel areas includes a photosensitive area for setting MOS capacitors and a charge reading area for setting read transistors. Each of the pixel areas has corresponding The substrate lead-out area is connected to the substrate in the corresponding substrate lead-out area, and the substrate lead-out area is used to provide a voltage application position for the substrate in the corresponding pixel area, wherein multiple columns of the pixel areas include charge reading Two adjacent columns of pixel areas with opposite areas and separated photosensitive areas, a substrate lead-out area corresponding to each pixel area in the two adjacent columns of pixel areas is provided in the column gap of the two adjacent columns of pixel areas; The isolation structure includes a full isolation body that penetrates the substrate in the thickness direction. In the two adjacent columns of pixel regions, the photosensitive areas of each pixel region in the same column are separated by the full isolation body.

Optionally, one of the substrate lead-out areas is provided in a column gap between two adjacent columns of pixel areas, and the substrate lead-out area passes between the opposite columns of the charge reading areas, and Each of the charge reading areas in the two adjacent column pixel areas is connected to the substrate of the substrate lead-out area.

Optionally, more than two substrate lead-out areas are provided in the column gap between the two adjacent columns of pixel areas, and the two or more substrate lead-out areas are separated by the full isolation body, and each Each of the substrate lead-out areas is only connected to the substrate of part of the pixel areas in the two adjacent columns of pixel areas.

Optionally, each of the substrate lead-out areas is provided with one or more substrate contact positions, and each of the substrate contact positions is used to set a substrate contact that is electrically connected to the substrate. structure.

Optionally, the multiple columns of the pixel areas include multiple groups of the two adjacent column pixel areas arranged sequentially along the row direction of the pixel area, wherein the pixel areas of the two adjacent columns are in the same row and belong to two adjacent groups respectively. Two pixel areas in adjacent columns have photosensitive areas facing each other, and the photosensitive areas of the two pixel areas are separated by the full isolation body.

Optionally, the isolation structure includes a first isolation body and a second isolation body, and the first isolation body and the second isolation body are respectively embedded into the substrate from the upper surface and the lower surface of the substrate. And none of them penetrate the substrate, and all extend laterally within the substrate; wherein at least part of the full isolation body is composed of the first isolation body and the second isolation body connected up and down.

Optionally, the photosensitive area and the charge reading area in the same pixel area are separated by the first isolator, and each pixel area is separated from the corresponding substrate lead-out area. Separated by the first isolator.

Optionally, the substrate bottoms of the pixel areas in adjacent rows are separated by the second isolators, and the tops of part of the second isolators are connected to the first isolators to form the full isolator.

Optionally, each of the pixel areas includes a source setting area and a drain setting area located in the corresponding charge reading area, and the photosensitive array further includes corresponding to the source setting area and the drain setting area respectively. Source and drain regions are formed in the substrate.

Optionally, in the two adjacent column pixel areas, the charge reading areas of at least part of the pixel areas on the same column are separated by the full isolation body, and the source setting area and drain setting area corresponding to the at least part of the pixel area are The locations of the districts are different.

Optionally, among the pixel areas in two adjacent columns, at least part of the pixel areas on the same column share the same charge reading area, and two adjacent pixel areas in at least part of the pixel areas share the source. setting area or the drain setting area.

Optionally, among the two adjacent column pixel areas, at least part of the pixel areas on the same column share the same charge reading area, and the source setting area of one of the at least part of the pixel areas is The drain setting area serves as an adjacent pixel area.

Optionally, the photosensitive array further includes a gate structure provided on the substrate of each pixel area, and the gate structure spans the photosensitive area and the charge reading area of the corresponding pixel area, and the The gate structure includes a gate oxide layer, a floating gate, an inter-gate dielectric layer and a control gate that are stacked in sequence from bottom to top, wherein the MOS capacitor includes the gate structure and the substrate of the photosensitive area, A read transistor includes the gate structure and the corresponding source and drain regions.

In one aspect, the present invention provides a method for manufacturing a photosensitive array, which method includes:

Provide a substrate, the substrate is preset with a plurality of pixel areas arranged in rows and columns and a substrate lead-out area distributed between the plurality of pixel areas, each of the pixel areas includes a MOS capacitor for setting A photosensitive area and a charge reading area for setting a reading transistor. Each of the pixel areas has a corresponding substrate lead-out area and is connected to the substrate of the corresponding substrate lead-out area. The substrate lead-out area It is used to provide a voltage application position for the substrate of the corresponding pixel area, wherein the plurality of columns of pixel areas include two adjacent columns of pixel areas with charge reading areas facing each other and photosensitive areas separated from each other, and the two adjacent columns of pixel areas have A substrate lead-out area corresponding to each pixel area in the two adjacent columns of pixel areas is provided in the column gap; and an isolation structure is formed in the substrate, and the isolation structure includes an isolation structure extending through the pixel area in the thickness direction. A complete isolator of the substrate. In the two adjacent columns of pixel regions, the photosensitive areas of each pixel region in the same column are separated by the complete isolator.

Optionally, the substrate has a first conductivity type doping, and after forming the isolation structure, the manufacturing method further includes: performing a first ion implantation to form a first conductivity type well in the substrate. area, the range of the first ion implantation is located between two opposite columns of photosensitive areas in the two adjacent columns of pixel areas, and covers the two opposite columns of charge reading areas and the substrate extraction area; in the A gate structure is formed on the substrate corresponding to each of the pixel areas, and the gate structure is provided across the photosensitive area and the charge reading area of the corresponding pixel area; a second ion implantation is performed to in the substrate A source region and a drain region of the second conductivity type are formed in the charge reading region corresponding to each of the pixel regions, and the source region and the drain region are located on both sides of the gate structure in the corresponding pixel region; and, A third ion implantation is performed corresponding to the substrate lead-out region to increase the first conductive type doping concentration on the top of the substrate in the substrate lead-out region.

Optionally, the preset multiple columns of pixel areas on the substrate include multiple groups of pixel areas of two adjacent columns arranged sequentially along the row direction of the pixel area, wherein pixel areas of two adjacent columns are in the same row and belong to The two pixel areas of two adjacent columns of pixel areas in two adjacent groups have photosensitive areas facing each other; in the step of forming an isolation structure in the substrate, the photosensitive areas of the two pixel areas are separated by the entire Isolator separation.

Optionally, the step of forming an isolation structure in the substrate includes: forming a first isolation body in the substrate, the first isolation body being embedded into the substrate from an upper surface of the substrate, and does not penetrate the substrate, wherein the photosensitive area and the charge reading area in the same pixel area are separated by the first isolator, and each pixel area is connected to the corresponding substrate The bottom lead-out areas are separated by the first isolator, and the first isolator also extends to an area for disposing the full isolator; and a second isolator is formed in the substrate, and the The second isolator is embedded in the substrate from the lower surface of the substrate and does not penetrate the substrate, wherein the second isolator is provided in a region for disposing the full isolator to pass through the connection above The first spacer thus constitutes the full spacer, and the pixel areas of adjacent rows are separated by the second spacer at the bottom of the substrate.

In one aspect, the present invention provides an imaging device, which includes the above-mentioned photosensitive array.

In the photosensitive array and the manufacturing method of the photosensitive array provided by the present invention, the substrate lead-out area is connected to the substrate in the corresponding pixel area, so that a voltage can be applied to the substrate in the corresponding pixel area through the substrate lead-out area. , thereby facilitating the equipotential operation of the substrates of each pixel when the photosensitive array is operating, and by providing a full isolator that penetrates the substrate in the thickness direction, so that the charge reading areas are opposite and the photosensitive areas are separated from each other. In two adjacent columns of pixel areas, the photosensitive areas of each pixel area in the same column are separated by the full isolator. The substrates of adjacent pixel areas separated by full isolators are physically isolated, which helps to reduce Crosstalk between different pixels.

The imaging device provided by the present invention includes the above-mentioned photosensitive array. Since the above-mentioned photosensitive array can reduce crosstalk between pixels, and at the same time apply voltage to the substrate of the corresponding pixel area through the substrate lead-out area, it is convenient to operate the photosensitive array when the photosensitive array is working. The substrates of each pixel are operated at an equal potential, and the photosensitive array uses MOS capacitors and read transistors to detect light. The pixel size can be made smaller, so the imaging device can achieve higher quality photosensitive imaging.

Description of the drawings

FIG. 1 is a schematic plan view of a vertical charge photosensitive device used in a photosensitive array according to an embodiment of the present invention.

FIG. 2 is a cross-sectional structure and a schematic diagram of electrical connections of a vertical charge photosensitive device used in a photosensitive array according to an embodiment of the present invention.

3A to 3C are schematic plan views of the distribution of pixel areas in the photosensitive array according to the embodiment of the present invention.

4A to 4C are schematic plan views of the complete isolation body used in the photosensitive array according to the embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a complete isolator used in the photosensitive array according to the embodiment of the present invention.

6A to 6C are schematic plan views of the second isolator disposed in the substrate in the photosensitive array according to the embodiment of the present invention.

FIG. 7 is a schematic diagram of the first ion implantation region in the manufacturing method of the photosensitive array according to the embodiment of the present invention.

FIG. 8 is a schematic diagram after the control gate is formed in the manufacturing method of the photosensitive array according to the embodiment of the present invention.

FIG. 9 is a schematic diagram of the second ion implantation region and the third ion implantation region in the manufacturing method of the photosensitive array according to the embodiment of the present invention.

Explanation of reference symbols:

100-pixel area; 110-photosensitive area; 120-charge reading area; 200-substrate extraction area; 310-full isolation body; 320-deep trench isolation.

Detailed ways

The photosensitive array, manufacturing method, and imaging device of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions. They are only used to conveniently and clearly assist in explaining the embodiments of the present invention. The embodiments of the present invention should not be considered to be limited to those shown in the drawings. specific shape of the display area. For the sake of clarity, in all drawings used to assist in explaining the embodiments of the present invention, the same components are marked with the same reference numerals in principle, and repeated descriptions thereof are omitted. "Row" and "column" are used to represent two directions at a certain angle. In some embodiments, the two can be interchanged. For example, "adjacent rows" in the following embodiments are correspondingly used in some embodiments. are recorded as "adjacent columns".

Embodiment 1: Photosensitive array

The photosensitive array of the embodiment of the present invention adopts the pixel structure of the dual-transistor photodetector disclosed in Chinese patent CN102938409A. This pixel structure is hereinafter referred to as a vertical-transferring-charge pixel Sensor (VPS). FIG. 1 is a schematic plan view of a vertical charge photosensitive device used in a photosensitive array according to an embodiment of the present invention. FIG. 2 is a cross-sectional structure and a schematic diagram of electrical connections of a vertical charge photosensitive device used in a photosensitive array according to an embodiment of the present invention. The cross-sectional structure on the left side in Figure 2 can be regarded as a schematic cross-sectional structure diagram of the AB cross-section in Figure 1, and the cross-sectional structure on the right side of Figure 2 can be regarded as a cross-sectional structural schematic diagram of the CD cross-section in Figure 1. The pixel structure used in the photosensitive array according to the embodiment of the present invention and the process of realizing photosensitivity are first described below with reference to FIGS. 1 and 2 .

Referring to FIGS. 1 and 2 , the pixel structure of the photosensitive array according to the embodiment of the present invention includes a gate structure provided on the substrate. The gate structure is provided across the photosensitive area 110 on the substrate, an isolation structure (such as a shallow trench). On the trench isolation (STI) and charge readout region 120 , a source region (S) and a drain region (D) are formed in the substrate in the charge readout region 120 on both sides of the gate structure. The gate structure includes a gate oxide layer, a floating gate, an inter-gate dielectric layer and a control gate that are sequentially superimposed on a substrate from bottom to top; wherein the substrate of the photosensitive region 110 (for example, has a p-type lightly doped (denoted as p-) and the gate structure can be used as a MOS capacitor (as shown in the cross-sectional structure on the left in Figure 2), corresponding to the charge reading area 120, and a p-well, for example, is formed in the substrate Region (pwell), the p-type ion doping concentration of the p-well region is, for example, greater than the p-type ion doping concentration of the photosensitive region substrate. The source and drain regions are formed on top of the p-well region, the source and drain regions have, for example, n-type heavy doping (n+), the gate structure and the substrate of the charge readout region 120 below The provided source region and drain region can be used as a read transistor (as shown in the cross-sectional structure on the right side of Figure 2).

The process of using the above pixel structure to achieve photosensitivity is as follows: Referring to Figure 2, first, during the exposure stage, the substrate is applied with a negative bias voltage less than 0V and greater than or equal to -20V (for example, -3V), and the control gate is connected to a voltage greater than 0V and less than A forward bias voltage equal to 20V can form a continuous depletion region in the substrate. When light is incident from the lower surface (i.e., the back) of the substrate, the photons reaching the depletion region can excite photogeneration under appropriate conditions. Charges are transferred to the floating gate driven by the electric field. The floating gate plays a role in charge storage. This process mainly occurs within the photosensitive area that constitutes the MOS capacitor; then, during the charge reading stage, the source area and the substrate are grounded (0V ), the drain area is connected to a suitable forward bias voltage (for example, greater than 0 and less than 3V), and the above-mentioned read transistor is operated in the linear region by adjusting the voltage of the control gate. Due to the MOS capacitor and the optoelectronic storage layer of the read transistor (i.e. floating gate ) is connected, the number of photogenerated charges stored in the floating gate during the exposure phase can be obtained by measuring the drift of the drain current; then during the reset phase, the control gate is connected to a negative bias, and the source areas of the substrate and read transistor are connected to the same With a forward bias (for example, greater than 0 and less than 3V), the photogenerated charges stored in the floating gate reach the source region.

It should be noted that this article mainly takes the n-type read transistor as an example, in which the source and drain regions are n-type heavily doped, and the substrate is a p-type lightly doped substrate (for example, doped with boron or diodes). Boron fluoride) in order to generate a depletion electric field during the exposure process. It can be understood that in the case where the read transistor is p-type, the source and drain regions need to be formed as p-type heavily doped. Correspondingly, the substrate Use an n-type lightly doped substrate (eg doped with phosphorus or arsenic).

When using the above-mentioned pixel structure to form a photosensitive array, in order to take full advantage of its relatively simple structure and the ability to realize smaller pixels, the pixel size is designed to be smaller. Usually, the maximum radial size of each pixel area on the substrate is less than 1 μm. Even below 0.5μm. In order to improve the photosensitivity effect, it is very important to make the crosstalk between adjacent pixels as small as possible. At the same time, it is also necessary to make it easy to apply the same voltage to the substrate of each pixel to maintain the same potential during the above photosensitivity process, such as during the exposure stage. The depletion electric field generated by the substrate corresponding to each pixel is basically the same. The photosensitive array of the embodiment of the present invention can meet these requirements, which will be described in detail below.

Embodiments of the present invention relate to a photosensitive array, which includes a substrate and an isolation structure disposed in the substrate. The substrate can be any suitable substrate in the art, for example, a silicon substrate with p-type doping. The silicon substrate has a lower doping concentration (p-), such as a doped boron ion density. Between 1×10 ¹² /cm ² and 2×10 ¹² /cm ² to obtain a wider depletion region in the substrate during the exposure stage, which helps to improve the light conversion quantum efficiency. The area distribution of the substrate and the isolation structure are described separately below.

3A to 3C are schematic plan views of the distribution of pixel areas in the photosensitive array according to the embodiment of the present invention. Referring to FIGS. 3A to 3C , the substrate is provided with a plurality of pixel areas 100 arranged in rows and rows (the "rows and rows arrangement" here refers to the arrangement in a plane perpendicular to the thickness direction of the substrate. Each pixel area 100 can be projected onto the upper surface, lower surface or into the substrate (the same applies to the following embodiments), and also has substrate lead-out areas 200 distributed among the plurality of pixel areas 100 . Each pixel area 100 includes a photosensitive area 110 for setting the MOS capacitor in the vertical charge photosensitive device and a charge reading area 120 for setting the reading transistor in the vertical charge photosensitive device. Each pixel area 100 corresponds to A substrate lead-out area 200, each pixel area 100 is connected to the substrate of the corresponding substrate lead-out area 200 (that is, the substrate part is not completely physically isolated), and each substrate lead-out area 200 is used to provide the corresponding pixel with The substrate of region 100 provides a voltage application location.

Further, in the multi-column pixel area 100 on the substrate, there is at least one group (or pair) of two adjacent columns with the following technical characteristics: In the pixel areas 100 of these two adjacent columns, the charge reading area 120 The photosensitive areas 110 are opposite to each other. That is to say, the arrangement of the pixel areas 100 in these two adjacent columns is: the photosensitive areas 110 of each column of pixel areas 100 are arranged in one column, the charge reading areas 120 are also arranged in one column, and the two columns of charge reading areas 120 are also arranged in one column. The two columns of photosensitive areas 110 are opposite and separated from each other. For two pixel areas 100 in the same row, the charge reading areas 120 of the two are opposite and the photosensitive areas 110 are separated from each other. In this embodiment, there are more than one group of two adjacent columns in the multi-column pixel area 100. In the multi-column pixel area 100, every two columns along the row direction of the pixel area 100 are divided into one group (that is, each group is arranged in sequence). ), multiple groups can be obtained. The charge reading areas 120 of the two columns of pixel areas 100 in each group are opposite and the photosensitive areas 110 are away from each other, as shown in group one and group two in FIG. 3A, FIG. 3B and FIG. 3C.

As shown in FIG. 3A and FIG. 3C, for two adjacent columns of pixel areas 100 in which the charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other, the charge reading areas 120 of adjacent pixel areas 100 in the same column are independent, Corresponding substrates may be separated by isolation structures. But it is not limited to this. In other embodiments, some or all of the pixel areas 100 in the same column can share the charge reading area 120 , that is, within a certain depth from the upper surface of the substrate to a certain depth in the substrate. An isolation structure is required to separate the charge reading areas 120 of different pixel areas 100 . For example, referring to FIG. 3B , in one embodiment, for two adjacent columns of pixel areas 100 in which the charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other, the charge reading areas 120 of the adjacent pixel areas 100 in the same column are are connected to each other, that is, the charge reading area 120 is shared. In this case, when configuring the read transistors for the two pixel areas 100 that share the charge read area 120, a common source area or a common drain area may be used to simplify the process.

In the embodiment of the present invention, for two adjacent columns of pixel areas 100 in which the above-mentioned charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other, a pixel area in two adjacent columns is provided in the column gap of the two columns of pixel areas 100. Each pixel area in 100 corresponds to a substrate lead-out area 200, and the substrate lead-out area 200 is used to provide a voltage application position for the substrate of each pixel area 100 in two adjacent columns. Providing the substrate lead-out area 200 in the column gap of the two adjacent columns of pixel areas 100 is conducive to reducing the pixel size, and because the substrate lead-out area 200 is provided between the two columns of pixel areas 100, the two columns The gap between the pixel areas is relatively large, which helps to avoid crosstalk between the pixel areas 100 in the row direction.

The number of substrate lead-out areas 200 provided in the above-mentioned column gap and the corresponding relationship with each pixel area can be set as needed. Here, the corresponding range of substrates in the same column gap is a connected substrate lead-out area 200 as the lead-out area of the same substrate. Since they are arranged in the column gap of two columns of pixel areas 100, the two pixel areas 100 in the same row can correspond to the same substrate lead-out area 200, that is, the same substrate lead-out area can be covered by at least one pair of pixel areas 100. shared. In the embodiment of the present invention, each of the substrate lead-out areas 200 may be configured to correspond to at least one row of pixel areas 100 in the two adjacent columns of pixel areas 100, so as to provide a substrate for the at least one row of pixel areas 100. The bottom provides the voltage application location. Correspondingly, the substrate lead-out area 200 is preferably provided in the row direction of at least one row of pixel areas 100 corresponding thereto.

Referring to FIG. 3A and FIG. 3B , as an example, in some embodiments, one of the substrate lead-out areas 200 is provided in the column gap of two adjacent columns of pixel areas 100 , and the substrate lead-out area 200 is connected from the opposite column. The charge reading areas 120 pass between the columns, and each of the charge reading areas 120 in the two adjacent columns of pixel areas 100 is connected to the substrate of the substrate lead-out area 200 . In this embodiment, the substrate lead-out area 200 provided in the column gap of the two adjacent columns of pixel areas 100 is shared by all the pixel areas 100 of the two adjacent columns, so as to serve all the pixel areas 100 of the two adjacent columns. The substrate of the pixel area 100 provides a voltage application location. Within the scope of the substrate lead-out area 200, more than two substrate contact positions can be provided along the column direction of the pixel area 100, so that each substrate contact position can be electrically connected to the substrate. substrate contact structures (such as contact plugs). The substrate contact structure is used to connect external electrical signals, so that voltage can be applied to each substrate contact position of the substrate and the surrounding pixel area substrate to facilitate equipotential operation. Referring to FIG. 8 , a substrate lead-out area 200 is provided between two adjacent columns of pixel areas 100 in which a group of charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other. The substrate lead-out area 200 is provided with A plurality of substrate contact positions (shown as hollow squares located in the substrate lead-out area 200 in FIG. 8 ), each substrate contact position is provided between two rows of pixel areas 100 for setting the substrate contact structure. The present invention is not limited to this. In the embodiment shown in FIG. 8 , according to the design of the substrate contact structure, at least part of the substrate contact position can also be moved up or down. The density of the substrate contact arrangement in the same substrate lead-out area 200 It can also be adjusted as long as it does not affect the settings of other structures (such as gate structures) of the vertical charge photosensitive device. Only one common substrate lead-out area 200 is provided between the two adjacent columns of pixel areas 100, which helps to simplify the process and reduce the pixel size.

According to the allocation of the substrate lead-out areas 200, the substrate lead-out areas 200 corresponding to some pixel areas 100 in the two adjacent columns of pixel areas 100 and other parts of the pixel areas 100 can be different, which can make the design of the photosensitive array more convenient. flexible. Referring to FIG. 3C , as an example, in other embodiments, for a set of two adjacent columns of pixel regions 100 in which the charge reading regions 120 are opposite and the photosensitive regions 110 are away from each other, the column gap between the two adjacent column pixel regions 100 is There are more than two substrate lead-out areas 200 disposed therein. The two or more substrate lead-out areas 200 are not connected within the column gap, and each of the substrate lead-out areas 200 is only partially opposite to the The charge reading area 120 is connected to the substrate (that is, it is only connected to the substrate of the pixel areas 100 in some rows (rather than all rows) of the two adjacent columns of pixel areas 100). Therefore, in this embodiment, for a substrate lead-out area 200 that is only connected to the substrate of the partially opposite charge reading area 120, it is shared by the pixel area 100 to which the charge reading area 120 connected to it belongs, Each of the substrate lead-out areas 200 may be disposed in the row direction of at least one corresponding row of pixel areas 100 to provide a voltage application position for the substrate of the corresponding pixel area 100 . In this embodiment, within the scope of each substrate lead-out area 200, one or more substrate contact positions may be set along the column direction of the pixel area 100, so that each substrate contact position can be set A substrate contact structure (such as a contact plug) electrically connected to the substrate. The substrate contact structure is used to connect external electrical signals, so that each substrate lead-out area of the substrate and the substrate of the pixel area corresponding to each substrate lead-out area can be applied with a voltage to facilitate equipotential operation. The specific position of each substrate contact position in the corresponding substrate lead-out area 200 can be set as needed, as long as it does not affect the arrangement of other structures (such as gate structures) of the vertical charge photosensitive device.

For one or more substrate lead-out areas 200 provided within the column gap of the two adjacent columns of pixel areas 100, the substrate contact position set within each substrate lead-out area 200 can be based on the distribution of the pixel areas. The situation is correspondingly evenly distributed, for example, one substrate contact position is provided along the lower edge of each row of pixel areas (refer to FIG. 8 ). The effect is to apply the same pressure to each substrate contact position in the same substrate lead-out area 200 . When the voltage is high, the substrates of each pixel area corresponding to the same substrate lead-out area 200 are at the same potential, which facilitates the realization that the substrates of each pixel are at the same potential when the photosensitive array is operating.

The above-mentioned range of each pixel area 100, the range of the photosensitive area 110 and the charge reading area 120 in each pixel area 100, and the range of the substrate lead-out area 200 can be determined by arranging corresponding isolation structures (such as shallow trenches) in the substrate. Trench isolation (STI) definition, for example, the substrate lead-out area 200 and the charge reading areas 120 on both sides can be separated by shallow trench isolation. In order to make the crosstalk between adjacent pixel areas as small as possible, in the embodiment of the present invention, some areas in the substrate are isolated by full isolators that run through the upper and lower surfaces of the substrate (as shown by the dotted lines in Figure 3A to Figure 3C area), the specific settings of the isolation structure will be described later.

In the above photosensitive array, each substrate lead-out area 200 can be connected to a substrate connection line provided on the substrate (for example, the substrate lead-out area 200 can be electrically lead out through a substrate contact structure provided at each of the above-mentioned substrate contact positions). , and in contact with the substrate connection line provided on the substrate (the substrate connection line is made of metal, for example), a voltage can be applied to the substrate through the substrate connection line and the substrate of each pixel area 100 is at the same potential. , the substrate connection line may be more than one, for example, there may be multiple substrate connection lines arranged in parallel along the row direction of the pixel area, and each substrate connection line is electrically connected to each substrate lead-out area 200 . In order to facilitate the application of voltage to the substrate, ion implantation can be performed corresponding to the substrate lead-out region 200 to make the top of the substrate in the substrate lead-out region 200 heavily doped (for example, p-type heavily doped, p+) to improve conductivity. sex.

It can be understood that the number and shape of the pixel areas shown in FIGS. 3A to 3C are only examples. The photosensitive array according to the embodiment of the present invention can also adopt a region shape different from that shown in the drawings. For example, in some embodiments, the shape of each pixel area 100, the shape of the photosensitive area 110, the shape of the charge reading area 120, the shape of the lining The shapes of the bottom lead-out areas 200 can be varied. For example, in addition to squares, they can also be circles, rhombuses, triangles, pentagons, hexagons, ovals, irregular graphics or other shapes. In addition, each row or each The pixel areas 100 of a column may not be in a straight line. For example, in one embodiment, the charge reading areas 120 of the pixel areas 100 of the same column are arranged in a wavy shape in the column direction. In addition, in some embodiments, the photosensitive array may have two or more pixel area arrangements as shown in FIGS. 3A to 3C . In one embodiment, each column of photosensitive areas in the photosensitive array includes, in addition to multiple groups of two adjacent columns of pixel areas 100 in which the charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other, they also include a single pixel area column that does not form a group. , in a single pixel area column that does not form a group, a substrate lead-out area extending along the column direction of the photosensitive area 110 can be provided separately to provide the substrate for each pixel area in the single pixel area column that does not form a group. Provides a voltage application location.

The photosensitive array of the embodiment of the present invention also includes an isolation structure provided in the substrate in which the above-mentioned pixel area 100 and the substrate lead-out area 200 are arranged, and the isolation structure includes a full isolation that runs through the substrate in the thickness direction. body. Specific instructions are as follows.

4A to 4C are schematic plan views of the complete isolation body used in the photosensitive array according to the embodiment of the present invention. Here, the pixel area distribution shown in FIG. 3A to FIG. 3C is still used as an example for explanation. FIG. 4A can be viewed as a full isolator arrangement within the partial substrate surface shown in FIG. 3A , FIG. 4B can be viewed as a full isolator arrangement within the partial substrate surface shown in FIG. 3B , and FIG. 4C can be viewed as the full isolator arrangement within the partial substrate surface shown in FIG. 3C . A full isolator arrangement within the partial substrate surface is shown.

As shown in Figures 4A, 4B and 4C, the isolation structure provided in the above-mentioned substrate includes a full isolation body 310 that runs through the substrate in the thickness direction (ie, runs through the upper and lower surfaces of the substrate). The body 310 extends laterally within the substrate (that is, extends in a plane perpendicular to the thickness direction of the substrate), so that the substrates on both sides of the full isolation body 310 are physically isolated to avoid interference between the pixel areas 100 on both sides. crosstalk, and when the full isolation body 310 is extended, it does not affect the substrate connection requirements between each pixel area 100 and the corresponding substrate lead-out area 200 . In the embodiment of the present invention, for a group of two adjacent columns of pixel areas 100 in which the charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other, the substrate lead-out area 200 corresponding to each pixel area 100 is disposed in the two adjacent columns of pixels. Within the column gap of the area 100, it is necessary to keep the substrate connected between the substrate lead-out area 200 and the corresponding pixel areas 100 on both sides, that is, the charge reading between the substrate lead-out area 200 and the two sides No full isolation body 310 is provided between zones 120. Since the migration of photogenerated charges in the pixel mainly occurs within the range of the photosensitive area 110 , maintaining substrate connectivity between the pixel area 100 and the corresponding substrate lead-out area 200 here will not easily increase the risk of crosstalk.

Specifically, in the above two adjacent columns of pixel areas 100, the photosensitive areas 110 of each pixel area 100 in the same column are separated by the full isolator 310, that is, the full isolator 310 is provided in each pair of opposite photosensitive area columns. between the photosensitive areas 110. In some embodiments, in the two adjacent columns of pixel areas 100 in the same group, the charge reading areas 120 of at least part of the pixel areas 100 in the same column are not shared, so these charge reading areas 120 can be connected through the above-mentioned full The shared charge reading area 120 does not need to be separated by the above-mentioned full isolator 310 or shallow trench isolation.

In the embodiment of the present invention, since the migration of photogenerated charges in the pixels mainly occurs within the range of the photosensitive area 110, the full isolator 310 does not need to completely physically isolate each row of pixel areas 100, but only separates the opposite photosensitive areas 110. But it is not limited thereto. Referring to FIG. 3C , in some embodiments, full isolators separate more than two substrate lead-out areas 200 provided in two adjacent columns of pixel areas 100 , and are separated from each other along the row direction of the pixel area 100 . The pixel areas 100 corresponding to different substrate lead-out areas 200 are separated, that is, the pixel areas 100 in adjacent rows are separated by full isolation bodies 310 . Further, a full isolation body 310 can be provided to surround each substrate lead-out area 200 and the pixel area 100 corresponding to the substrate lead-out area 200, thereby forming a closed isolation ring in the substrate (as an example of a dotted line in Figure 4C). Shown by the dotted rectangular box). The pixel area inside the closed isolation ring forms complete physical isolation from the pixel area outside the closed isolation ring, which can enhance the physical isolation effect between the pixel areas 100 and avoid crosstalk.

As shown in FIGS. 4A to 4C , in two adjacent columns of pixel areas 100 in which the charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other, the photosensitive areas 110 of each pixel area 100 in the same column are separated by the full isolation The isolation body 310 helps to reduce the crosstalk between adjacent pixel areas 100 on the same column. For the adjacent pixel areas 100 on the same row, since the substrate lead-out area 200 is provided, no full isolation body 310 is provided. isolation. Since the substrate lead-out area 200 passes through the opposite charge reading area 120, the distance between the two columns of pixel areas 100 in the two adjacent columns of pixel areas 100 is widened. That is, the substrate lead-out area 200 also serves to separate the left and right sides. The function of the column pixel area 100 helps to avoid crosstalk between the two pixel areas 100 located on the left and right sides of the substrate lead-out area 200 on the same row. In addition, for adjacent pixel area groups (in each group, the charge reading areas 120 of two adjacent columns of pixel areas 100 are opposite and the photosensitive areas 110 are deviated from each other), the two adjacent photosensitive area columns among them are opposite to each other, Therefore, two adjacent groups of two adjacent column pixel regions 100 can be completely separated by the full isolation body 310 to avoid crosstalk. But not limited to this, considering that the photogenerated electrons in the exposure stage are mainly generated in the substrate in the photosensitive area and move toward the gate oxide layer along the thickness direction of the substrate, between non-adjacent photosensitive areas (as shown in Figure 4A The full isolation body 310 may not be provided between area a) and/or adjacent charge reading areas 120 (area b in FIG. 4A). For example, in one embodiment, the multiple columns of the pixel areas 100 include multiple groups of the two adjacent column pixel areas 100 arranged sequentially along the row direction of the pixel areas 100, wherein the two pixel areas in the same row 100 respectively belong to two adjacent groups of the two adjacent column pixel areas 100 and their photosensitive areas 110 are opposite to each other. The photosensitive areas 110 of the two pixel areas 100 are separated by the full isolation body 310 but are not located in the pixel area. The full isolators 310 on the same row are not continuous within the column gap of two adjacent groups of two adjacent column pixel areas 100, but between non-adjacent photosensitive areas 110 (as shown in Figure 4A The area a) is disconnected.

FIG. 5 is a schematic cross-sectional view of a complete isolator used in the photosensitive array according to the embodiment of the present invention. Figure 5 can be seen as a structural schematic diagram of the EF section in Figure 4A. In Figure 5, the pixel structure located on the substrate is not shown. As shown in FIG. 5 , the full isolator 310 passes through the substrate along the thickness direction, thereby isolating the substrate of different pixel areas 100 on both sides. For between the photosensitive area 110 and the charge reading area 120 in the same pixel area 100, and between each substrate lead-out area 200 and each pixel area 100 corresponding to the substrate lead-out area 200, their corresponding substrates Parts of the imaging array require the same voltage to be applied during operation, so these substrate parts are connected through the thickness of the part. When incident light irradiates the lower surface of the substrate, the photogenerated charges generated in the substrate portions of different pixel areas 100 move toward the upper surface of the substrate under the action of the depletion electric field. Under the limitation of the full isolation body 310, the photogenerated charges can basically only Moving within the substrate portion of the same pixel area 100 can reduce crosstalk between different pixel areas 100, which helps to improve the accuracy of the charge reading process, thereby helping to achieve higher-quality photosensitive imaging. Although the arrangement of the full isolator 310 does not completely physically isolate each pixel area 100 from the surrounding pixel areas due to the arrangement of the shared substrate lead-out area 200, the process of photogenerated charge migration from the substrate to the floating gate is mainly Within the scope of the photosensitive area, the arrangement of the above-mentioned full isolator 310 can still achieve a better isolation effect on the photogenerated charges entering different pixel areas.

The material of the above-mentioned full isolation body (ie, the isolation medium) may include at least one of silicon dioxide, silicon nitride, and silicon oxynitride. The full isolator may be formed in the substrate using processes disclosed in the art. In one embodiment, at least part of the full isolation body 310 is composed of isolation structures embedded in the substrate from the upper surface and the lower surface of the substrate respectively and connected to each other.

Specifically, the isolation structure may include a first isolation body and a second isolation body. The first isolation body and the second isolation body are respectively embedded into the substrate from the upper surface and the lower surface of the substrate. And none of them penetrate the substrate, and all extend laterally within the substrate; wherein, at least part of the full isolation body 310 is composed of the first isolation body and the second isolation body connected up and down. In this embodiment, the first isolator and the second isolator can be made separately. After the first isolator and the second isolator are formed, the above-mentioned full isolation body 310 is formed. Compared with forming a full isolation body from the substrate side, The integrated approach can simplify the manufacturing process and make the process more controllable.

The first isolation body is, for example, shallow trench isolation (STI). In addition to being used to obtain the above-mentioned full isolation body 310, the first isolator can also be used to separate each pixel area 100 from the corresponding substrate lead-out area 200 and to separate the photosensitive area 110 and charge reading in the same pixel area 100. District 120. The depth of the first isolator can be specifically set according to the thickness of the substrate and the isolation effect required by the photosensitive array. For the substrate area where only the first isolator is provided, the lower portion of the substrate is connected and not separated. Therefore, the operation of the MOS capacitor and the read transistor is not affected, and the function of the substrate lead-out area 200 is not affected.

The second isolator is, for example, a deep trench isolation (DTI). Since it is provided on the back side of the substrate and does not penetrate the substrate, that is, if only the second isolator is provided, it will not affect the communication of the upper part of the substrate, and therefore will not affect the substrate. The function of the bottom lead-out area 200 is to improve the isolation effect of adjacent pixel areas. In one embodiment, the second isolator is not only provided in the area of the full isolation body 310 to separate each pixel area 100, but also in some areas where full isolation is not provided. The body 310 can separate the pixel areas (for example, within the substrate corresponding to the substrate lead-out area 200), and a second isolator can also be provided to further prevent the pixels generated in the portion of the substrate corresponding to each pixel area during the exposure stage. The photogenerated charges are shifted to adjacent pixel areas to improve the anti-crosstalk effect. For example, in two adjacent columns of pixel areas 100 in which the charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other, the substrate bottoms of the pixel areas 100 in adjacent rows can be separated by the second isolator, and part of the pixel areas 100 can be separated by the second isolator. The first isolator is connected above the second isolator to form the full isolator 310 , so that the photosensitive areas 110 of each pixel area 100 in the same column are separated by the full isolator 310 .

6A to 6C are schematic plan views of the second isolator disposed in the substrate in the photosensitive array according to the embodiment of the present invention. The description is still made with reference to the pixel area distribution shown in FIG. 3A and FIG. 3C as an example. Figures 6A, 6B and 6C correspond to the pixel area distributions of Figures 3A, 3B and 3C respectively. Referring to FIGS. 6A to 6C , the shape of the second isolator 320 in a plane perpendicular to the substrate thickness direction may be a mesh structure, and two pixel areas 100 in the same row in the same group are located in the same mesh of the mesh structure. Within the grid. In addition, part of the second isolator 320 shown in FIGS. 6A to 6C (at least except for the area where the substrate lead-out area 200 is provided) can be correspondingly provided with the first isolator. On the one hand, the isolation effect can be improved, and on the other hand, the isolation effect can be improved by setting The first isolator and the second isolator are connected up and down to form a full isolator 310 that penetrates the upper and lower surfaces of the substrate.

The above-mentioned first isolator and the second isolator 320 can be formed by etching the upper surface side and the lower surface side of the substrate according to a preset pattern to form trenches and filling the isolation dielectric, respectively. The material of the two isolators 320 may include at least one of silicon dioxide, silicon nitride, and silicon oxynitride. The specific depths of the first isolator and the second isolator 320 can be specifically set according to the thickness of the substrate and the isolation effect required by the photosensitive array.

In order to obtain the above vertical charge photosensitive device, the photosensitive array may include a gate structure provided on the substrate of each pixel area 100 and a source region (S) provided in the substrate on both sides of each gate structure. and drain area (D). Specifically, each of the above-mentioned pixel areas 100 may include a source setting area and a drain setting area (not shown) located in the corresponding charge reading area 120, and the photosensitive array further includes corresponding to the The source setting region and the drain setting region are a source region (S) and a drain region (D) formed in the substrate.

In an optional embodiment, for two adjacent columns of pixel areas 100 in which the above-mentioned charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other, the charge reading areas 120 of each pixel area 100 located in the same column can be independent. Can be shared. Referring to FIGS. 3A and 3C , in one embodiment, in the above-mentioned two adjacent columns of pixel regions 100 , the charge reading regions 120 of at least part of the pixel regions 100 on the same column are separated by an isolation structure (such as a full isolation body 310 or only the third Separated by an isolator), the source setting area and the drain setting area corresponding to each of the pixel areas 100 are respectively located in their respective charge reading areas 120. The positions of the source setting area and the drain setting area corresponding to different pixel areas are different, so they are different. The positions of the source area and the drain area corresponding to the pixel area are different. Referring to FIG. 3B , in another embodiment, among the two adjacent column pixel areas 100 , at least part of the pixel areas 100 on the same column share the same charge reading area 120 (that is, the respective charge reading areas are connected to each other). In this case, , at least there is no need to provide a first isolator (the second isolator may or may not be provided) to separate the charge reading areas 120 of adjacent pixel areas 100; and, further, the adjacent charge reading areas 120 of the shared charge reading area 120 do not need to be provided. The pixel areas 100 can share the above-mentioned source setting area or drain setting area. Correspondingly, the source area or drain area formed in the substrate can also be shared by two adjacent pixel areas 100 that share the charge reading area 120, that is, The read transistors corresponding to two adjacent pixel areas on the same column share the source or drain area, which can simplify the process. In one embodiment, among the two adjacent columns of pixel regions 100 , all pixel regions 100 in the same column share the same charge reading region 120 .

Referring to FIGS. 1 and 2 , the photosensitive array according to the embodiment of the present invention may further include a gate structure provided on the substrate corresponding to each pixel area 100 , and the gate structure spans the photosensitive area 110 of the corresponding pixel area 100 and the charge reading area 120, the gate structure includes a gate oxide layer, a floating gate, an inter-gate dielectric layer and a control gate that are sequentially superimposed on the upper surface of the substrate from bottom to top, and the gate structure also It may include spacers (not shown) covering side surfaces of the gate oxide layer, the floating gate, the inter-gate dielectric layer and the control gate. The source region (S) and the drain region (D) formed in the substrate corresponding to the source setting region and the drain setting region can be further formed by ion implantation after the gate structure is formed on the substrate. The charge reading area 120 is formed on the top of the substrate, so that vertical charge photosensitive devices corresponding to each pixel area, that is, pixels of the photosensitive array, can be obtained. In the photosensitive array, the pixel corresponding to each pixel area 100 has the structure of the vertical charge photosensitive device mentioned above, wherein the MOS capacitor of the vertical charge photosensitive device includes a gate structure formed within the corresponding pixel area and a lining of the photosensitive area 110. Bottom, the reading transistor of the vertical charge photosensitive device includes a gate structure formed within the corresponding pixel area and corresponding source and drain areas.

In the photosensitive array of the embodiment of the present invention, the read transistors provided in the charge read area 120 are interconnected using a flash memory NOR architecture. Specifically, the control gates of each read transistor corresponding to the pixel area 100 in the same row are connected to the same control gate. Gate line (FG line), the drain areas of each read transistor corresponding to the pixel area 100 in the same column are connected to the same drain line (bit line), and the source areas of each read transistor corresponding to the pixel area 100 in the same row are connected to the same source line. In addition to the above-mentioned substrate and isolation structure, the photosensitive array may also include multiple gate structures, multiple control gate lines, drain lines, source lines and connection pads disposed on the substrate. The substrate connection lines in the bottom lead-out area are used to control each pixel in the photosensitive array to achieve the aforementioned photosensitive process.

Embodiment 2: Manufacturing method of photosensitive array

The manufacturing method of the photosensitive array introduced below can be used to manufacture the photosensitive array as described in Embodiment 1. The manufacturing method mainly includes a first step of providing a substrate and a second step of forming an isolation structure in the substrate.

In the first step, before or after forming the isolation structure, the substrate may be formed as a substrate with a lower doping concentration, for example, with p-type shallow doping, where p-type is used as the first conductive type. Referring to FIGS. 1 to 6C , the substrate is preset with a plurality of pixel areas 100 arranged in rows and columns and a substrate lead-out area 200 distributed between the multiple pixel areas 100 . Each of the pixel areas 100 each includes a photosensitive area 110 for setting the MOS capacitance in the above-mentioned vertical charge photosensitive device and a charge reading area 120 for setting the reading transistor in the above-mentioned vertical charge photosensitive device. Each of the pixel areas 100 is configured to be connected to a The substrate lead-out area 200 corresponds to and is connected with the substrate of the corresponding substrate lead-out area 200. The substrate lead-out area 200 is used to provide a voltage application position for the substrate of the corresponding pixel area 100, wherein multiple columns of The pixel area 100 includes two adjacent columns of pixel areas 100 with charge reading areas 120 facing each other and photosensitive areas 110 separated from each other. The pixel areas 100 of the two adjacent columns are arranged in the column gap between the two adjacent columns of pixel areas 100 . Each pixel area 100 in the corresponding substrate lead-out area 200. In an optional embodiment, the preset multiple columns of pixel areas 100 on the substrate include multiple groups of two adjacent column pixel areas 100 arranged sequentially along the row direction of the pixel area 100. Then, for Each group of the two adjacent column pixel areas 100 is provided with a corresponding substrate lead-out area 200 within the column gap. Here, the substrate lead-out area 200 in which the corresponding range of substrates are connected in the same column gap is regarded as the same substrate lead-out area. For a group of two adjacent ones in which the charge reading area 120 is opposite and the photosensitive area 110 is away from each other, The column pixel areas 100, the number of substrate lead-out areas 200 provided in the column gap, and the corresponding relationship between the substrate lead-out areas 200 and each pixel area 100 can be set as needed.

In a second step, isolation structures are formed in the substrate. Specifically, the isolation structure includes a full isolation body 310 that runs through the substrate in the thickness direction. For the two adjacent columns of pixel areas 100 preset on the substrate, the photosensitive areas of each pixel area 100 in the same column 110 are separated by the total isolation body 310 . In addition, in the case where there are multiple sets of two adjacent column pixel areas with the above-mentioned charge reading areas 120 facing each other and the photosensitive areas 110 deviating from each other sequentially arranged along the row direction of the pixel area 100, including the photosensitive areas in the same row, The areas 110 are opposite and belong to two adjacent groups of two adjacent column pixel areas 100 respectively. The photosensitive areas 110 of the two pixel areas 100 can be separated by the full isolation body 310 to increase the pixel count. Isolation effect between zones 100.

In the second step, the full isolation body 310 can be formed by etching the substrate to form a through hole and filling the through hole with dielectric. In addition, if the substrate needs to be thinned on the back surface (i.e., the lower surface), a deeper trench can be etched from the upper surface side of the substrate before thinning, and then filled with isolation dielectric. After completing the pixel structure process on the upper surface side of the substrate, the portion of the substrate that is not penetrated by the trench is removed from the back through a backside thinning process, thereby forming a full isolation body that penetrates the upper and lower surfaces of the substrate. But it is not limited thereto. At least part of the full isolation body 310 can be made by respectively making trenches from the upper surface and the lower surface of the substrate and filling the isolation medium. Compared with the first two methods of forming a full isolation body, it can be simplified. process, and the controllability of the process is high.

Specifically, in one embodiment, forming the isolation structure in the substrate may include the following process.

First, a first isolator is formed in the substrate. The first isolator is embedded into the substrate from the upper surface of the substrate and does not penetrate the substrate. The first isolator is, for example, Shallow trench isolation (STI), the first isolator is provided between the photosensitive area 110 and the charge reading area 120 in the same pixel area 100 on the substrate, and is also provided between each pixel area 100 and the corresponding between the substrate lead-out areas 200. In addition, the first isolator also extends to the area where the above-mentioned full isolator 310 is disposed, so as to obtain a partial-thickness full isolator 310 .

Then, a second spacer 320 is formed in the substrate (refer to FIGS. 6A to 6C ). The second spacer 320 is embedded in the substrate from the lower surface of the substrate without penetrating the substrate. At the bottom, the second isolator 320 is disposed in the area for arranging the full insulator 310 to obtain a partial thickness full insulator 310, and is connected to the first isolator above to form the full insulator 310. . For example, the second isolator 320 can be formed between the two adjacent columns of pixel regions 100 in adjacent groups (the charge reading regions 120 of the two columns of pixel regions in each group are opposite and the photosensitive regions 110 are away from each other), or Can be formed between pixel areas 100 in adjacent rows (in order to improve the isolation effect between pixel areas, the second isolator 320 can be set between pixel areas that cannot be completely physically isolated by the full isolation body 310, where adjacent The rows of pixel areas 100 are separated by second spacers 320 at the bottom of the substrate. The first spacers can be disposed only above part of the second spacers 320 to obtain full spacers 310, while allowing the pixel areas shared by adjacent rows of pixel areas 100 to be The substrate in the substrate lead-out area 200 is still connected). Moreover, since the first isolator has been formed in the area where the full isolator 310 is provided, when the second isolator 320 is formed in this area, the sum of the depths of the first isolator and the second isolator 320 can be controlled to be greater than or equal to the liner. The thickness of the bottom is such that the second isolator 320 in this area is connected to the first isolator above to obtain a full isolator 310 that penetrates the upper and lower surfaces of the substrate.

After the above isolation structure is formed, the manufacturing method may further include the following process. The following description takes the arrangement of the pixel area and the substrate lead-out area shown in FIG. 3B as an example.

First, referring to FIG. 3B and FIG. 7 , a first ion implantation is performed to form a well region of the first conductivity type in the substrate. For a set of two adjacent ones in which the charge reading region 120 is opposite and the photosensitive region 110 is away from each other, In the column pixel area 100, the first ion implanted area is located between two opposite columns of photosensitive areas 110 and covers the two opposite columns of charge reading areas 120 and the substrate extraction area 200. The first ion implantation is recorded as a first conductivity type, such as p-type ion implantation. After the first ion implantation, the p-type doping concentration of the well region is higher than the p-type doping concentration of other regions of the substrate.

Next, referring to Figures 1, 2 and 8, based on the first ion implantation, a gate structure is formed on the substrate corresponding to each of the pixel areas 100, and the gate structure spans the corresponding On the photosensitive area 110 and the charge reading area 120 of the pixel area 100 . The gate structure includes a gate oxide layer, a floating gate, an inter-gate dielectric layer and a control gate stacked sequentially from bottom to top, and also includes a hard mask covering the upper surface of the control gate and the gate oxide layer, The floating gate, the inter-gate dielectric layer, the control gate and the spacers on the side surface of the hard mask (not shown). As shown in Figure 8, the control gates in the gate structures corresponding to the same row of pixel areas 100 on the substrate can be connected to each other, thereby forming multiple control gate lines (exemplarily FG1, FG2, FG3, FG4), each of the control gate lines extends along the row direction of the pixel area 100 to span the photosensitive area 110 and the charge reading area 120 of each pixel area 100 on the same row, and serves as a gate electrode in each gate structure of the corresponding row. Control grid.

Referring to FIG. 8 , each pixel area 100 may have a source setting area and a drain setting area. The source setting area and the drain setting area are located in the charge reading area 120 of the corresponding pixel area 100 , and may subsequently correspond to the charge reading area 120 of the corresponding pixel area 100 . The source setting region and the drain setting region form corresponding source regions and drain regions in the substrate. The source setting area and the drain setting area corresponding to each pixel area 100 can be independent of each other, that is, the positions are different, or, as shown in FIG. 8 , when the charge reading areas 120 of adjacent pixel areas 100 located on the same column are connected to each other. When, two adjacent pixel areas 100 located on the same column can share the source setting area or the drain setting area, and further, the corresponding read transistors of the two adjacent pixel areas 100 on the same column can be shared. Source region or common drain region (the electrical lead-out positions of the source region and the drain region are illustrated by the diagonal intersecting squares located within the charge reading area 120 in Figure 8 ). In addition, in each substrate lead-out area 200, several substrate contact positions can be set (as shown by the hollow squares located within the charge reading area 120 in Figure 8). Subsequently, each substrate contact position can be set by A substrate contact structure (such as a contact plug) positioned to be electrically connected to the substrate electrically leads out the substrate in each substrate lead-out area 200 .

In one embodiment, two or more pixel areas 100 located on the same column share the charge reading area 120. The source setting area or the drain setting area of two adjacent pixel areas 100 can be shared, so that the charge reading area corresponding to the source area 120 can be shared. The source region formed by the setting region or the drain region formed corresponding to the drain setting region is also shared by the two adjacent pixel regions 100 . For example, in the charge reading area 120 shared by two pixel areas 100 that are adjacent up and down in the column direction, the common source setting area can be set at the lower right corner of the upper pixel area 100 and simultaneously set in the lower pixel area. 100, correspondingly, the drain setting area corresponding to the pixel area 100 located above is far away from the pixel area 100 located below and is located in the upper part of the common charge reading area 120, and the drain setting area corresponding to the pixel area 100 located below It is arranged at the lower part of the common charge reading area 120 away from the pixel area 100 located above.

In one embodiment, two or more pixel areas 100 located in the same column share the charge reading area 120, and the source setting area and drain setting area of at least one pixel area 100 can be shared with adjacent pixel areas 100. For example, multiple pixel areas 100 in the first column in FIG. 8 share the charge reading area 120, and the source setting area and drain setting area corresponding to each pixel area 100 are arranged up and down along the column direction in the charge reading area 120. That is, the source setting area corresponding to each pixel area 100 is vertically opposite to the drain setting area in the charge reading area 120 and is located on both sides of the corresponding gate structure. For the pixel area 100 in the first column and second row in FIG. 8, its source setting area is, for example, located at the upper right corner of the pixel area 100. It can be seen that the source setting area of the pixel area 100 is also located in the first column and first row. The lower right corner of the pixel area 100 can therefore also be used as the drain setting area of the pixel area 100 in the first column and first row. In FIG. 8 , the drain setting area of the pixel area 100 in the first column and the second row is, for example, located at the lower right corner of the pixel area 100 . It can be seen that the drain setting area of the pixel area 100 is also located in the pixels in the first column and the third row. The upper right corner of the area 100 can therefore be used as the source setting area of the pixel area 100 in the first column and third row at the same time. It can be seen that for a pixel area 100 that is adjacent to other pixel areas in the column direction, its corresponding source area can be used as a drain area of an adjacent pixel area 100 on the same column, and its drain area can be used as a drain area on the same column. The source area of another adjacent pixel area.

Then, referring to FIG. 9 , after the above-mentioned gate structure is formed, a second ion implantation is performed to correspond to the source setting area and the drain setting area in the charge reading area 120 of each pixel area 100 in the substrate. A source region and a drain region are formed in the pixel region 100 , and the source region and the drain region are located on both sides of the gate structure in the corresponding pixel region 100 . The second ion implantation is a second conductivity type, here n-type ion implantation. The second ion implantation region can be performed in a range that avoids the substrate lead-out region 200. Due to the hard mask of the gate structure and the shielding of the sidewalls, the second ion implantation will not affect the gate structure and the substrate below it.

Next, still referring to FIG. 9 , a third ion implantation is performed corresponding to the substrate lead-out region 200 to improve the first conductive type (p-type in this embodiment) doped state on the top of the substrate in the substrate lead-out region 200 . concentration. After the third ion implantation, the p-type doping concentration at the top of the substrate at the position of each substrate extraction region 200 is higher than the p-type doping concentration in other regions of the substrate. By performing the third ion implantation, the electrical contact performance at the substrate lead-out region 200 is improved, making it easier to apply a voltage to the substrate through the substrate contact position therein.

The order of the second ion implantation and the third ion implantation is not fixed. For example, in one embodiment, the third ion implantation may be performed first, and then the second ion implantation may be performed.

The above manufacturing method may also include the step of forming contact plugs on the substrate. For example, an insulating layer of a certain thickness may be formed on the substrate first, and then corresponding contact plugs may be formed in the insulating layer corresponding to the positions of the source and drain regions. A source contact plug or a drain contact plug, the source contact plug and the drain contact plug are electrically connected to the corresponding source region and drain region respectively. In addition, several substrate contact plugs may also be formed in the insulating layer corresponding to the range of the substrate lead-out area 200 (for example, formed at the substrate contact positions as shown in FIG. 8 ), so that the substrate contact plugs The substrate lead-out area 200 is electrically connected to the substrate. For example, in one embodiment, for a set of two adjacent column pixel areas 100 in which the charge reading areas 120 are opposite and the photosensitive areas 110 are away from each other, the substrate between the adjacent two or four pixel areas 100 can be led out. A substrate contact plug is disposed in the area 200 to apply a voltage to the substrates of the surrounding two or four pixel areas 100 through the substrate contact plug. In addition, the manufacturing method may subsequently include the step of forming an interconnection metal layer on each contact plug, the interconnection metal layer covering each source contact plug, drain contact plug and substrate contact plug to form Electrical connection, through interconnecting metal layers and contact plugs, can electrically control the source area, drain area, and substrate lead-out area, especially applying voltage to the substrate in the corresponding pixel area through the substrate lead-out area , to facilitate the equipotential operation of the substrate of each pixel when the photosensitive array is working.

Embodiment 3: Imaging device

Embodiments of the present invention also relate to an imaging device, which includes the photosensitive array described in the above embodiments. The imaging device may be a device using the photosensitive array and having an imaging function. The imaging device may be, for example, an image sensor including the photosensitive array. In addition to the photosensitive array, the imaging device may also include a data processing unit and/or an image output unit working in conjunction with the photosensitive array, so as to process the photogenerated charges obtained from each pixel in the photosensitive array. The data is processed and an image is formed. Since the setting of the above-mentioned photosensitive array facilitates equipotential operation of the substrates of each pixel when the photosensitive array is working, and the crosstalk between pixels is small, in addition, the photosensitive array uses MOS capacitors and read transistors for photosensitivity, and the pixels The size can be made smaller, so the imaging device can achieve higher quality photosensitive imaging.

It should be noted that the embodiments in this specification are described in a progressive manner. Each part focuses on the differences from the previous parts. The similarities and similarities between the various parts can be referred to each other.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of rights of the present invention. Any person skilled in the art can use the methods and technical contents disclosed above to improve the present invention without departing from the spirit and scope of the present invention. Possible changes and modifications are made to the technical solution. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention, all belong to the technical solution of the present invention. protected range.

Claims (18)

1. A photosensitive array, comprising:

a substrate having a plurality of pixel regions arranged in rows and columns and a substrate lead-out region distributed between the plurality of pixel regions, each of the pixel regions including a photosensitive region for setting a MOS capacitor and a charge reading region for setting a reading transistor, each of the pixel regions having a corresponding substrate lead-out region and being in communication with the substrate of the corresponding substrate lead-out region, the substrate lead-out regions being for providing a voltage application position to the substrate of the corresponding pixel region, wherein a plurality of columns of the pixel regions include two adjacent columns of pixel regions in which the charge reading regions are opposite and the photosensitive regions are opposite, the substrate lead-out regions corresponding to each of the two adjacent columns of pixel regions being provided in column gaps of the two adjacent columns of pixel regions; the method comprises the steps of,

The isolation structure is arranged in the substrate, and comprises a full isolator penetrating through the substrate in the thickness direction, and the photosensitive areas of all the pixel areas on the same column are separated by the full isolator in the pixel areas on two adjacent columns.

2. A photosensitive array as claimed in claim 1, wherein one of said substrate extraction regions is disposed in a column gap between said two adjacent column pixel regions, said substrate extraction region passing between opposed columns of said charge readout regions, and each of said charge readout regions in said two adjacent column pixel regions is in communication with a substrate of said substrate extraction region.

3. A photosensitive array as claimed in claim 1, wherein two or more substrate extraction regions are provided in column gaps of said two or more adjacent column pixel regions, said two or more substrate extraction regions being separated by said full separator, and each of said substrate extraction regions being in communication with only a portion of the substrate of said pixel region in said two adjacent column pixel regions.

4. A photosensitive array as claimed in claim 1, wherein each of said substrate extraction areas has one or more substrate contact locations thereon, each of said substrate contact locations being for providing a substrate contact structure in electrical communication with said substrate.

5. The photosensitive array of claim 1, wherein a plurality of columns of said pixel regions comprise a plurality of sets of said two adjacent columns of pixel regions sequentially arranged in a row direction of said pixel regions, wherein two pixel regions which are in a same row and respectively belong to two adjacent sets of said two adjacent columns of pixel regions are opposite to each other, and the photosensitive regions of said two pixel regions are separated by said full separator.

6. The photosensitive array of claim 1, wherein the isolation structure comprises a first isolator and a second isolator, the first isolator and the second isolator being embedded within the substrate from an upper surface and a lower surface of the substrate, respectively, and neither extending through the substrate, and both extending laterally within the substrate; at least part of the whole isolator is composed of the first isolator and the second isolator which are connected up and down.

7. A photosensitive array as claimed in claim 6, wherein said photosensitive regions and said charge readout regions in the same said pixel region are separated by said first separator, and each said pixel region is separated from the corresponding said substrate extraction region by said first separator.

8. A photosensitive array as claimed in claim 6, wherein the substrate bottoms of the pixel regions of adjacent rows are separated by said second spacers, and wherein portions of said second spacers are connected to said first spacers above to form said full spacers.

9. A photosensitive array as claimed in any one of claims 1 to 8, wherein each of said pixel regions comprises a source and drain arrangement region within a respective charge reading region, said photosensitive array further comprising source and drain regions formed in said substrate corresponding to said source and drain arrangement regions, respectively.

10. The photosensitive array of claim 9, wherein in the pixel regions of two adjacent columns, at least some of the pixel regions on the same column are separated by the full separator, and the source setting region and the drain setting region corresponding to at least some of the pixel regions are different in position.

11. The photosensitive array of claim 9, wherein at least some pixel regions on the same column among the two adjacent columns of pixel regions share the same charge reading region, and two adjacent pixel regions among the at least some pixel regions share the source arrangement region or the drain arrangement region.

12. The photosensitive array of claim 9, wherein at least some pixel regions on the same column among the two adjacent columns of pixel regions share the same charge reading region, and the source arrangement region of one of the at least some pixel regions serves as the drain arrangement region of an adjacent pixel region.

13. The photosensitive array of claim 9, further comprising a gate structure disposed on the substrate of each of the pixel regions, the gate structure straddling the photosensitive region and the charge readout region of the corresponding pixel region, the gate structure comprising a gate oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate disposed in sequence from bottom to top, wherein the MOS capacitor comprises the gate structure and the substrate of the photosensitive region, and the readout transistor comprises the gate structure and the corresponding source region and drain region.

14. A method of manufacturing a photosensitive array, comprising:

providing a substrate, wherein the substrate is pre-provided with a plurality of pixel areas arranged in rows and columns and a substrate leading-out area distributed among the pixel areas, each pixel area comprises a photosensitive area for setting a MOS capacitor and a charge reading area for setting a reading transistor, each pixel area is provided with a corresponding substrate leading-out area and is communicated with the substrate of the corresponding substrate leading-out area, the substrate leading-out area is used for providing a voltage application position for the substrate of the corresponding pixel area, a plurality of columns of pixel areas comprise two adjacent columns of pixel areas, the charge reading areas are opposite and the photosensitive areas are opposite, and the substrate leading-out areas corresponding to each pixel area in the two adjacent columns of pixel areas are arranged in column gaps of the two adjacent columns of pixel areas; the method comprises the steps of,

And forming an isolation structure in the substrate, wherein the isolation structure comprises a full isolator penetrating through the substrate in the thickness direction, and the photosensitive areas of each pixel area in the same column are separated by the full isolator in the pixel areas in the two adjacent columns.

15. The method of manufacturing of claim 14, wherein the substrate has a first conductivity type doping, the method of manufacturing further comprising, after forming the isolation structure:

performing first ion implantation to form a well region of a first conductivity type in the substrate, wherein the range of the first ion implantation is positioned between two opposite rows of photosensitive regions in the two opposite rows of pixel regions and covers the two opposite rows of charge reading regions and the substrate leading-out region;

forming a gate structure corresponding to each pixel region on the substrate, wherein the gate structure spans the photosensitive region and the charge reading region of the corresponding pixel region;

performing second ion implantation to form a source region and a drain region of a second conductivity type in the charge readout region corresponding to each of the pixel regions in the substrate, the source region and the drain region being located on both sides of the gate structure in the corresponding pixel region; the method comprises the steps of,

And carrying out third ion implantation corresponding to the substrate leading-out area so as to improve the concentration of the first conductive type doping on the top of the substrate leading-out area.

16. The method according to claim 14, wherein the pixel regions of a plurality of columns preset on the substrate include a plurality of groups of pixel regions of two adjacent columns sequentially arranged in a row direction of the pixel regions, wherein two pixel regions which are in a same row and respectively belong to two adjacent groups of pixel regions of two adjacent columns are opposite to each other as photosensitive regions; in the step of forming an isolation structure in the substrate, the photosensitive regions of the two pixel regions are separated by the full isolator.

17. The method of manufacturing of any of claims 14 to 16, wherein the step of forming the isolation structure in the substrate comprises:

forming a first spacer embedded in the substrate from an upper surface of the substrate without penetrating the substrate, wherein the photosensitive region and the charge reading region in the same pixel region are separated by the first spacer, each pixel region is separated from the corresponding substrate extraction region by the first spacer, and the first spacer further extends to a region for disposing the full spacer; the method comprises the steps of,

And forming a second spacer embedded in the substrate from the lower surface of the substrate and not penetrating through the substrate, wherein the second spacer is arranged in a region for arranging the full spacer so as to form the full spacer by connecting the first spacer above.

18. An image forming apparatus, characterized in that the image forming apparatus comprises the photosensitive array according to any one of claims 1 to 13.