CN113363252A

CN113363252A - Trench IGBT chip layout structure

Info

Publication number: CN113363252A
Application number: CN202110603168.1A
Authority: CN
Inventors: 曹功勋; 郎金荣; 刘建华
Original assignee: GTA Semiconductor Co Ltd
Current assignee: GTA Semiconductor Co Ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2021-09-07

Abstract

The invention provides a trench IGBT chip layout structure, comprising: a plurality of trench IGBT chips arranged along a first direction and a second direction perpendicular to each other; each trench IGBT chip includes a cell structure, each Several gate trenches parallel to each other are formed in each cell structure, and the direction of the gate trenches is along the first direction or the second direction; two adjacent trench IGBT chips arranged along the first and second directions The directions of the gate trenches are perpendicular to each other. By arranging the IGBT chip gate trenches on the wafer in a criss-cross distribution in both the first and second directions, the gate polysilicon filled in the vertical gate trenches warps the wafer downward, and the gate polysilicon filled in the lateral gate trenches The polysilicon warps the wafer upwards, and the criss-cross gate trenches offset the compressive stress and the tensile stress, thereby effectively improving the wafer warpage problem of the trench IGBT chip during the manufacturing process without changing the process and increasing the cost. .

Description

Trench IGBT chip layout structure

Technical Field

The invention belongs to the technical field of power semiconductor devices, and particularly relates to a trench IGBT chip layout structure.

Background

The power semiconductor device is also called as a power electronic device and is a core device for realizing electric energy conversion and circuit control of a power electronic device. The main application comprises frequency conversion, rectification, voltage transformation, power amplification, power control and the like, and the energy-saving effect is achieved. The power semiconductor device is widely applied to the power electronic fields of mobile communication, consumer electronics, new energy traffic, rail traffic, industrial control, power generation, power distribution and the like, and covers low, medium and high power levels. There are many types of power semiconductors, such as IGBT, VDMOS, CoolMOS, among which the most representative semiconductor power device is IGBT.

An Insulated Gate Bipolar Transistor (IGBT) as a hybrid power device has the characteristics of MOS structure input and Bipolar structure output, so that the IGBT has the advantages of high MOSFET input impedance, low power of a driving circuit, simple driving, high switching speed, and low switching loss, and the IGBT has the advantages of high current density, high current handling capability, and low on-state saturation voltage drop. By the beginning of the 80 s, the IGBT is widely researched at home and abroad, has wide application prospect at present, is widely applied to a plurality of fields such as new energy automobiles, industrial frequency conversion, photovoltaic, smart power grids, locomotives and the like, and the market of the Chinese IGBT accounts for about one third of the total market of the global IGBT.

Common IGBT structures are a planar IGBT structure (i.e., an IGBT chip with a planar gate structure) and a trench IGBT structure (i.e., an IGBT chip with a trench gate structure). The IGBT chip channel region of the planar gate structure is on the surface, and the channel density is limited by the surface area of the chip, so that the conductance modulation effect in the IGBT chip body is weaker, and the conduction voltage drop is higher. Therefore, the market is more inclined to use the trench IGBT structure. The early trench IGBT product of the Yingfeing adopts the square cell design, but the size of the cell is difficult to be reduced by adopting the square cell, namely the current density of the IGBT is difficult to be improved. The strip-shaped unit cell IGBT unit cell is easier to be made into a small size, has the advantages of strong latch-up resistance, suitability for high frequency and the like, so the strip-shaped unit cell becomes the mainstream unit cell of the trench IGBT, but the wafer warpage problem is easy to occur in the manufacturing process of the strip-shaped unit cell IGBT chip.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a trench IGBT chip layout structure for solving the problem that the trench IGBT chip with stripe-shaped cells in the prior art is easy to warp the wafer during the manufacturing process.

In order to achieve the above and other related objects, the present invention provides a trench IGBT chip layout structure, including:

the plurality of groove type IGBT chips are distributed along a first direction and a second direction, and the first direction is vertical to the second direction;

each groove type IGBT chip comprises a cellular structure, a plurality of grid grooves which are parallel to each other are formed in each cellular structure, the direction of each grid groove is along the first direction or the second direction, and a grid dielectric layer and a grid polycrystalline silicon layer are filled in each grid groove; the directions of the gate grooves of two adjacent trench type IGBT chips arranged along the first direction are mutually vertical, and the directions of the gate grooves of two adjacent trench type IGBT chips arranged along the second direction are mutually vertical.

Optionally, each trench type IGBT chip further includes a terminal structure disposed in an outer circumferential direction of the cell structure.

Optionally, an electrical connection structure is arranged between two adjacent gate trenches in each trench type IGBT chip, so that all the gate trenches in each trench type IGBT chip are electrically connected.

Optionally, a gate lead-out region is disposed in each trench IGBT chip.

Further, the gate lead-out region is disposed at the center of the cell structure or at the peripheral edge of the cell structure or at the corner of the cell structure.

Optionally, a distance is preset between two adjacent trench type IGBT chips arranged along the first direction and between two adjacent trench type IGBT chips arranged along the second direction, and the distance is consistent with the width of a dicing channel on the wafer substrate after the layout structure of the trench type IGBT chips is subjected to tape-out.

Optionally, the wafer substrate used for the trench IGBT chip layout structure tape-out is a silicon wafer substrate.

Further, the silicon wafer substrate is a float-zone silicon wafer substrate.

As described above, according to the trench IGBT chip layout structure of the present invention, a single IGBT chip layout is rearranged on a wafer according to a certain arrangement to form a large layout, one large layout includes four normal IGBT chip layouts, and the four normal IGBT chip layouts are arranged in a crisscross manner at intervals, so that after tape-out, trenches of IGBT chips on the wafer are both distributed crisscross in the first direction X and the second direction Y, gate polysilicon filled in longitudinal trenches warps the wafer downward, gate polysilicon filled in transverse trenches warps the wafer upward, and then the crisscross trenches offset compressive stress and tensile stress, thereby effectively improving the problem of wafer warpage of trench IGBT chips in the manufacturing process without changing the process and increasing the cost.

Drawings

Fig. 1 is a schematic diagram of a conventional trench IGBT chip layout structure relative to a wafer substrate.

Fig. 2 to 4 are schematic diagrams of a trench IGBT chip layout structure of the present invention relative to a wafer substrate, where fig. 2 shows that a gate lead-out region is disposed at the center of a cell structure, fig. 3 shows that a gate lead-out region is disposed at the peripheral edge of a cell structure, and fig. 4 shows that a gate lead-out region is disposed at a corner of a cell structure.

Fig. 5 to 7 show layout structures of a single trench IGBT chip, where fig. 5 shows that the gate lead-out region is disposed at the center of the cell structure, fig. 6 shows that the gate lead-out region is disposed at the peripheral edge of the cell structure, and fig. 7 shows that the gate lead-out region is disposed at the corner of the cell structure.

Fig. 8 to 10 show a large chip layout unit composed of layout structures of 4 single trench type IGBT chips, in which fig. 8 shows that the gate lead-out region is disposed at the center of the cell structure, fig. 9 shows that the gate lead-out region is disposed at the peripheral edge of the cell structure, and fig. 10 shows that the gate lead-out region is disposed at the corner of the cell structure.

Description of the element reference numerals

10 wafer substrate

11-cell structure

110 gate trench

111 terminal structure

112 grid electrode lead-out region

12 space apart

13 groove type IGBT chip

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed according to actual needs, and the layout of the components may be more complicated.

As shown in fig. 1, a common structure example of a conventional stripe trench IGBT chip layout structure is shown, where the trench arrangement direction in each cell structure on the chip layout is the same, for example, the trench arrangement direction is vertical or horizontal. Based on the chip layout structure and adopting a zone-melting silicon wafer substrate to carry out plate making and flow sheet making, selecting the arrangement direction of the groove as longitudinal and transverse, and finally measuring the bending degree (Bow) of the silicon wafer substrate as shown in table 1:

TABLE 1

The table shows that the IGBT wafer of the longitudinal groove is warped downwards, the IGBT wafer of the transverse groove is warped upwards, the curvature is large, the wafer warping not only influences the alignment precision of photoetching in the chip technological process, even the wafer warping degree is too large, the wafer can not be normally manufactured in a flow sheet mode, and is scrapped midway, so that the production efficiency is reduced, and the manufacturing cost is improved.

Based on this, this embodiment provides a slot IGBT chip territory structure, through arranging single IGBT chip territory according to certain, the recombination is a big territory, include four normal IGBT chip territories in a big territory, and arrange these four normal IGBT chip territories according to the mode of vertically and horizontally interval, thereby make the slot of IGBT chip on the wafer present crisscross distribution behind the tape, the gate polycrystalline silicon that fills in the vertical slot makes the wafer warp downwards, the gate polycrystalline silicon that fills in the horizontal slot makes the wafer warp upwards, then crisscross slot, can make compressive stress and tensile stress offset each other, thereby improve the problem that strip slot IGBT chip takes place the wafer warpage in manufacturing process.

As shown in fig. 2 to 4, specifically, the trench IGBT chip layout structure includes:

the plurality of trench type IGBT chips 13 are arranged along a first direction X and a second direction Y, and the first direction X and the second direction Y are perpendicular to each other;

each trench type IGBT chip 13 includes a cell structure 11, a plurality of gate trenches 110 parallel to each other are formed in each cell structure 11, the direction of each gate trench 110 is along the first direction X or the second direction Y, and a gate dielectric layer and a gate polysilicon layer are filled in each gate trench 110; the directions of the gate trenches 110 of two adjacent trench IGBT chips 13 arranged along the first direction X are perpendicular to each other, and the directions of the gate trenches 110 of two adjacent trench IGBT chips 13 arranged along the second direction Y are perpendicular to each other.

The layout design mode of the gate grooves criss-cross along the first direction X and the gate grooves criss-cross along the second direction Y ensures that the gate grooves on the whole wafer substrate are all criss-cross arrangement mode after the wafer flow, namely the whole wafer substrate has the effect of offsetting tensile stress and compressive stress in the first direction X and the second direction Y, thereby effectively improving the problem of wafer warpage caused by the groove IGBT chip in the manufacturing process on the basis of not changing the process and increasing the cost.

As shown in fig. 5 to 7, as an example, the outer ring of the cell structure 11 of each trench IGBT chip 13 is circumferentially provided with a terminal structure 111. The terminal structure 111 is a terminal protection structure of the trench IGBT chip 13, and the terminal protection structure adopts a terminal protection mode of an existing conventional IGBT chip, which is not described herein again.

As an example, an electrical connection structure (not shown in the drawings) is disposed between two adjacent gate trenches 110 in each trench IGBT chip 13, so that all the gate trenches 110 in each trench IGBT chip 13 are electrically connected. For example, the electrical connection structure may, but is not limited to, utilize polysilicon to make connections to all of the gate trenches.

As shown in fig. 5 to 7, as an example, a gate lead-out region 112 is provided in each of the trench IGBT chips 13, and the gate lead-out region 112 is formed with a pad structure to realize lead-out of the gate in the trench IGBT chip 13. The gate lead-out region 112 may be located according to specific situations, and for facilitating the chip testing after the chip is taped out, the gate lead-out region 112 is generally selected to be located at the center of the cell structure 11 (as shown in fig. 5), or located at the peripheral edge of the cell structure 11 (as shown in fig. 6), or located at the corner of the cell structure 11 (as shown in fig. 7).

As shown in fig. 2 to 4, as an example, a distance 12 is provided between two adjacent trench IGBT chips 13 arranged along the first direction X and between two adjacent trench IGBT chips 13 arranged along the second direction Y, the distance 12 is the same as the width of the scribe line on the wafer substrate 10 after the layout structure of the trench IGBT chips is formed, and the wafer can be cut into individual IGBT chips by cutting in the scribe line region. It should be noted that the width of the scribe line on the wafer substrate 10 after the layout structure of the trench IGBT chip is taped out is consistent with the width of the scribe line, which means that the width of the scribe line is equal to or substantially equal to the width of the scribe line, or the pitch 12 is consistent with the width of the scribe line.

As an example, the material of the wafer substrate 10 used for normal tape-out based on the trench IGBT chip layout structure described above may be selected from existing semiconductor materials suitable for manufacturing IGBT devices, such as silicon materials or silicon carbide materials. At present, the preparation method of the silicon single crystal mainly comprises a floating zone method (FZ) and a Czochralski method (CZ), and the silicon wafer prepared by the CZ method has low purity, high oxygen and carbon content and uneven resistivity. Therefore, the existing silicon wafer prepared by the float zone method is mainly adopted for the IGBT below 8 inches, but the silicon wafer prepared by the float zone method has low oxygen content, and the problem of wafer warping is easy to occur in the subsequent wafer process manufacturing.

As shown in fig. 5 to fig. 7, it should be noted that the trench IGBT chip 13 further includes other conventional structures of IGBTs, such as: the carrier storing N-type doped region, P-type body region, N-type source region, insulating layer and front metal layer, etc. will not be described in detail.

The following illustrates a design and a tape-out process of a trench IGBT chip layout structure based on this embodiment:

as shown in fig. 5 to 7, a layout structure of a single stripe-shaped trench IGBT chip is first drawn, wherein the gate lead-out region 112 may be selectively disposed at the center of the cell structure 11 (as shown in fig. 5), or at the peripheral edge of the cell structure 11 (as shown in fig. 6), or at the corner of the cell structure 11 (as shown in fig. 7).

As shown in fig. 8 to 10, 4 strip-shaped trench IGBT chip layout structures are arranged according to a certain rule and recombined into a large layout, so that the original grid trenches arranged in a single direction are changed into a criss-cross grid trench distribution mode in the transverse direction and the longitudinal direction, a certain distance is reserved between two adjacent strip-shaped trench IGBT chip layout structures, and the distance is consistent with the width of a scribing street after subsequent tape-out.

As shown in fig. 2 to 4, plate making is performed according to the large layout (a layout structure of 4 normal strip-shaped trench IGBT chips) of the previous step, and shots are arranged according to the large chips.

And finally, performing tape-out according to the normal IGBT chip process flow to form a wafer containing a plurality of IGBT chips. During wafer testing, for the IGBT layout of the grid lead-out region 112 on the center and the corners of the layout, testing of all chips on the wafer can be completed at one time; for the IGBT layout of the gate lead-out region 112 at the peripheral edge of the layout, four tests are required to complete the test of all chips on the wafer, but after the production of general products, the chips on the wafer cannot be tested completely, and the chips are sampled and tested according to a certain rule, and the chips with the same groove direction can be extracted to complete the test of the wafer once. The IGBT chip flow sheet is based on the groove IGBT chip layout structure, in the flow sheet process, criss-cross gate grooves are formed in the first direction X and the second direction Y on the whole wafer substrate, so that the effect of offsetting tensile stress and compressive stress is achieved in the first direction X and the second direction Y, and the problem of improving wafer warping can be achieved without changing the process of the IGBT chip and increasing cost.

In summary, the present invention provides a trench IGBT chip layout structure, where a single IGBT chip layout is rearranged on a wafer according to a certain arrangement to form a large layout, one large layout includes four normal IGBT chip layouts, and the four normal IGBT chip layouts are arranged in a criss-cross interval manner, so that after tape-out, trenches of IGBT chips on the wafer are both distributed criss-cross in a first direction X and a second direction Y, gate polysilicon filled in longitudinal trenches warps the wafer downward, gate polysilicon filled in transverse trenches warps the wafer upward, and then the criss-cross trenches offset compressive stress and tensile stress, thereby effectively improving the problem of wafer warpage of the trench IGBT chips in the manufacturing process without changing the process and increasing the cost. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. The utility model provides a slot IGBT chip layout structure which characterized in that, the layout structure includes:

2. The trench IGBT chip layout structure of claim 1, wherein: each groove type IGBT chip also comprises a terminal structure arranged in the circumferential direction of the outer ring of the cellular structure.

3. The trench IGBT chip layout structure of claim 1, wherein: an electric connection structure is arranged between two adjacent gate grooves in each groove type IGBT chip, so that all the gate grooves in each groove type IGBT chip are electrically connected.

4. The trench IGBT chip layout structure of claim 1, wherein: and a grid lead-out region is arranged in each groove type IGBT chip.

5. The trench IGBT chip layout structure of claim 4, wherein: the grid electrode leading-out region is arranged in the center of the cellular structure or on the peripheral edge of the cellular structure or on the corner of the cellular structure.

6. The trench IGBT chip layout structure of claim 1, wherein: and a distance is preset between every two adjacent groove type IGBT chips arranged along the first direction and every two adjacent groove type IGBT chips arranged along the second direction, and the distance is consistent with the width of a cutting channel on the wafer substrate after the layout structure of the groove type IGBT chips is subjected to tape-out.

7. The trench IGBT chip layout structure of claim 1, wherein: the wafer substrate used by the trench IGBT chip layout structure tape-out is a silicon wafer substrate.

8. The trench IGBT chip layout structure of claim 7, wherein: the silicon wafer substrate is a zone-melting silicon wafer substrate.