CN113359930A - Linear regulator, soft start method, and electronic device - Google Patents
Linear regulator, soft start method, and electronic device Download PDFInfo
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Abstract
The application discloses linear voltage regulator, linear voltage regulator's soft start method and electronic equipment, linear voltage regulator includes: the soft start module is used for boosting a signal input by an input end and comprises at least two input ends, wherein the first input end is used for acquiring reference voltage, the second input end is used for acquiring sampling voltage, and the reference voltage gradually rises from an initial value to reference voltage; the error amplification module comprises at least two input ends, wherein the first input end is used for being connected to the output end of the soft start module to obtain corresponding first boosting after the reference voltage is boosted, the second input end is also connected to the output end of the soft start module to obtain corresponding second boosting after the sampling voltage is boosted, the difference value of the first boosting and the second boosting is amplified, and an error amplification value is output; the error amplification value is used for adjusting the output voltage of the linear voltage stabilizer, and the sampling voltage is sampled from the output voltage.
Description
Technical Field
The present disclosure relates to the field of linear regulators, and more particularly, to a linear regulator, a soft start method and an electronic device.
Background
The linear voltage regulator is a commonly used device in a circuit, and can be used for adjusting the magnitude of input voltage to achieve the purpose of voltage stabilization. Linear regulators use transistors or FETs operating in their linear region to subtract excess voltage from the applied input voltage to produce a regulated output voltage. The product adopts small-sized package, has excellent performance, provides value-added characteristics such as thermal overload protection, safe current limiting and the like, and can greatly reduce power consumption in a turn-off mode.
The linear voltage regulator in the prior art includes a low dropout regulator, which can make a power tube in a saturated conduction state by using a voltage difference to ground, and output a stable load voltage to stably drive an external load.
In the prior art, when a linear regulator is started to drive an external load, the linear regulator may generate transient overvoltage surge exceeding the normal operating voltage of the external load, which may cause performance loss or even damage of the external load. The instantaneous overvoltage is a violent pulse which occurs in a very short time, has a great influence on an external load, and how to prevent the violent pulse is a problem to be solved by the technical personnel in the field.
Disclosure of Invention
In view of the above, the present application provides a linear regulator, a soft start method of the linear regulator, and an electronic device.
The application provides a linear voltage regulator, includes: the soft start module is used for boosting a signal input by an input end and comprises at least two input ends, wherein the first input end is used for acquiring reference voltage, the second input end is used for acquiring sampling voltage, and the reference voltage can gradually rise from an initial value to reference voltage; the error amplification module comprises at least two input ends, wherein a first input end is used for being connected to the output end of the soft start module so as to obtain a first boost corresponding to the boosted reference voltage, a second input end is also connected to the output end of the soft start module so as to obtain a second boost corresponding to the boosted sampling voltage, the difference value of the first boost and the second boost is amplified, and an error amplification value is output; the error amplification value is used for adjusting the output voltage of the linear voltage stabilizer, and the sampling voltage is sampled from the output voltage.
Optionally, the soft start module includes: a first current source for providing a first current; and the boosting unit is connected to the first current source and used for acquiring the reference voltage and the sampling voltage so as to output corresponding first boosting voltage and second boosting voltage according to the reference voltage and the sampling voltage.
Optionally, the boosting unit includes: the first PMOS tube is used for acquiring the reference voltage by a conduction threshold value, a grid electrode is used for acquiring the reference voltage, a source electrode is connected to the output end of the first current source so as to acquire the first current and is used for outputting the first boosting voltage, and a drain electrode is grounded; and the grid electrode of the second PMOS tube is used for receiving the sampling voltage, the source electrode of the second PMOS tube is connected to the output end of the first current source so as to obtain the first current and is used for outputting the second boosting voltage, and the drain electrode of the second PMOS tube is grounded.
Optionally, the first current source includes a third PMOS transistor and a fourth PMOS transistor, and gates of the third PMOS transistor and the fourth PMOS transistor are both connected to a first preset voltage source to obtain a first preset voltage; the source electrode of the third PMOS tube is used for obtaining the input voltage of the linear voltage stabilizer, and the drain electrode of the third PMOS tube is connected to the source electrodes of the first PMOS tube and the second PMOS tube; and the source electrode of the fourth PMOS tube is used for acquiring the input voltage of the linear voltage stabilizer, and the drain electrode of the fourth PMOS tube is connected to the source electrode of the third PMOS tube.
Optionally, the error amplifying module includes a second current source and an input pair transistor, where the second current source is configured to provide a second current to the input pair transistor, and the input pair transistor includes: a drain of the first NMOS transistor is connected to the second current source to obtain the second current, a source of the first NMOS transistor is grounded through a bias current source, and a gate of the first NMOS transistor is connected to an output end of the soft start module to obtain the second boost voltage; and the drain electrode of the second NMOS tube is connected to the second current source to obtain the second current, the source electrode of the second NMOS tube is grounded through the bias current source, and the grid electrode of the second NMOS tube is connected to the output end of the soft start module to obtain the first boosting.
Optionally, the second current source includes: a fifth PMOS tube, a source electrode is used for receiving input voltage, a drain electrode is connected to the drain electrode of the first NMOS tube, and the grid electrode and the drain electrode of the fifth PMOS tube are mutually connected; and the source electrode of the sixth PMOS tube is used for receiving the input voltage, the drain electrode of the sixth PMOS tube is connected to the drain electrode of the second NMOS tube, and the grid electrode of the sixth PMOS tube is connected to the grid electrode of the sixth PMOS tube.
Optionally, the apparatus further includes an output module, where the output module includes: a seventh PMOS tube, a grid electrode of which is connected to the output end of the error amplification module, a source electrode of which is connected to the input voltage, and a drain electrode of which is grounded through a voltage division unit and outputs the output voltage through the drain electrode; the voltage division unit comprises a first resistor and a second resistor which are connected in sequence, the upper end of the first resistor is connected to the drain electrode of the seventh PMOS tube, and the lower end of the second resistor is grounded.
Optionally, the initial value is less than or equal to 0V.
The application also provides a soft start method of the linear voltage stabilizer, which further comprises the following steps: providing a reference voltage, and performing boosting processing on the reference voltage to obtain a first boosted voltage, wherein the reference voltage can be gradually increased from an initial value to the reference voltage; sampling the output voltage of the linear voltage stabilizer to obtain a sampling voltage, and performing boosting processing on the sampling voltage to obtain a second boosting voltage; comparing the first boost voltage with the second boost voltage, and amplifying the error of the first boost voltage and the second boost voltage; and adjusting the output of the linear voltage stabilizer according to the error amplification value after error amplification.
Optionally, when the first boost pressure and the second boost pressure are obtained, the method includes the following steps: providing a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, wherein source electrodes of the first PMOS tube and the second PMOS tube are connected to a first current source to obtain a first current, and drain electrodes of the first PMOS tube and the second PMOS tube are grounded; and outputting the reference voltage to a grid electrode of a first PMOS tube, outputting the sampling voltage to a grid electrode of a second PMOS tube, acquiring a grid-source voltage of the first PMOS tube as the first boost voltage, and acquiring a grid-source voltage of the second PMOS tube as the second boost voltage.
The application provides an electronic device, which comprises the linear voltage regulator.
The application discloses linear voltage regulator, soft start method and electronic equipment, through the soft start module is right reference voltage and sampling voltage boost, guarantee input geminate transistor among the error amplification module just can be driven at initial start phase, prevent linear voltage regulator is in initial start phase imbalance. And the reference voltage is gradually increased from the initial value until the reference voltage is increased, so that the gradual increase of the output voltage is ensured.
In addition, the linear voltage regulator, the soft start method and the electronic equipment have the characteristics of simple structure, are insensitive to external factors such as current load, output capacitance and the like, and can realize smooth establishment of the output voltage of the linear voltage regulator with the pair transistors of N-type input.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a linear regulator according to an embodiment of the present application. And (5) a schematic connection relation.
Fig. 2 is a schematic circuit diagram of a soft-start module and an error amplification module in the linear regulator according to an embodiment of the present disclosure.
Fig. 3 is a circuit schematic diagram of the soft start module and the error amplification module in an embodiment of the present application.
Fig. 4 is a schematic circuit diagram of the output module according to an embodiment of the present application.
Fig. 5 is a flowchart illustrating steps of a soft-start method of a linear regulator according to an embodiment of the present application.
Detailed Description
It has been found that the error amplifier in the prior art linear regulator often uses an NMOS transistor as the input pair transistor. At the initial starting stage of the linear voltage stabilizer, because the output voltage of the linear voltage stabilizer is gradually increased, the sampling voltage of the output voltage is also gradually increased, so that the lower sampling voltage at the initial starting stage cannot drive the input geminate transistor, which can make the error amplifier of the linear voltage stabilizer be in a line drop state at the initial starting stage, and cannot adjust the output of the linear voltage stabilizer, thereby causing the imbalance of the linear voltage stabilizer and failing to realize the soft start of the linear voltage stabilizer.
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Fig. 1 is a schematic diagram of a linear regulator according to an embodiment of the invention.
In this embodiment, a linear regulator is provided, which includes a soft start module 101, an error amplification module 102, and an output module 103, which are connected in sequence.
The soft start module 101 is configured to perform boosting processing on a signal input by an input end, and includes at least two input ends, where a first input end is configured to obtain a reference voltage Vref _ soft, a second input end is configured to obtain a sampling voltage Vfb, and the reference voltage Vref _ soft is less than or equal to the reference voltage Vref and can gradually rise from an initial value V0 to the reference voltage.
The sampling voltage Vfb is sampled from the output voltage Vout output by the output module 103, and the reference voltage is a reference voltage used by the error amplification module 102 when the linear regulator is in normal use.
The error amplifying module 102 includes at least two input terminals, a first input terminal is used for being connected to the output terminal of the soft start module to obtain a first boost Vup1 corresponding to the boosted reference voltage Vref _ soft, and a second input terminal is also connected to the output terminal of the soft start module to obtain a second boost Vup2 corresponding to the boosted sampling voltage Vfb, and amplify a difference between the first boost Vup1 and the second boost Vup2 to output an error amplification value Vea-out; the error amplification value Vea-out is used to adjust the output voltage Vout of the linear regulator.
In this embodiment, the error amplifying module 102 uses an NMOS transistor as an input pair transistor, and the input pair transistor is driven by the boosted signal output by the soft start module 101. The reference voltage Vref _ soft is large enough for the boosting amplitudes of the reference voltage Vref _ soft and the sampling voltage Vfb, so that the first boosting voltage Vup1 and the second boosting voltage Vup2 are large enough to be greater than or equal to the conduction threshold of the input pair transistor 1022 in the error amplification module 102.
In an initial stage of the start-up of the linear regulator, even if the output voltage Vout and the sampling voltage Vfb are small, the input pair transistor can be driven by the boosted signal, so that the error amplification module 102 can be in a working state to adjust the output voltage Vout output by the output module 103.
Fig. 2 is a schematic diagram of a circuit structure of a soft start module 101 and an error amplification module 102 in the linear regulator according to an embodiment.
In this embodiment, the soft-start module 101 includes a first current source 1011 and a voltage boosting unit 1012, wherein the first current source 1011 is configured to provide a first current, and the voltage boosting unit 1012 is connected to the first current source 1011 and configured to obtain the first current, a sampling voltage Vfb and a reference voltage Vref _ soft, so as to output a corresponding first boosted voltage Vup1 and a second boosted voltage Vup2 according to the reference voltage Vref _ soft and the sampling voltage Vfb.
In this embodiment, the boosting unit 1012 includes a first PMOS transistor MP1 and a second PMOS transistor MP2 for boosting the reference voltage Vref _ soft and the sampling voltage Vfb, respectively, and the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned on when the gate voltage is lower than the turn-on threshold.
The conduction threshold of the first PMOS transistor MP1 is higher than the reference voltage, which is the maximum voltage that the reference voltage Vref _ soft can reach, so that the first PMOS transistor MP1 can also be kept conducting after the error amplification module 102 works normally, and the first boost voltage Vup1 is output.
The gate of the first PMOS transistor MP1 is used for obtaining the reference voltage Vref _ soft, the source is connected to the output end of the first current source 1011 to obtain the first current, and is used for outputting the first boost voltage Vup1, and the drain is grounded.
The conduction threshold of the second PMOS transistor MP2 needs to be higher than the sampling voltage Vfb corresponding to the target output voltage of the linear regulator by a certain value, so that when the sampling voltage Vfb rises to the maximum voltage and fluctuates at the maximum voltage, the second PMOS transistor MP2 can still be kept conducting, and outputs the second boost voltage Vup2 corresponding to the sampling voltage Vfb.
The gate of the second PMOS transistor MP2 is configured to receive the sampled voltage Vfb, the source is connected to the output end of the first current source 1011 to obtain the first current, and is configured to output the second boost voltage Vup2, and the drain is grounded.
In this embodiment, the first current output by the first current source 1011 is sufficiently large, and the transconductance of the first PMOS transistor MP1 and the second PMOS transistor MP2 is also sufficiently large, at this time, even if the reference voltage Vref _ soft and the sampling voltage Vfb are small, the first boost voltage Vup1 and the second boost voltage Vup2 output correspondingly are also sufficiently large, so that the input pair transistor 1022 in the error amplification module 102 can be smoothly driven, the error amplification module 102 is in an operating state, and the linear regulator is prevented from being offset in an initial start-up stage.
In addition, since the sampling voltage Vfb is sampled from the output voltage Vout and has a multiple relation with the output voltage Vout, the sampling voltage Vfb can gradually increase from 0V along with the reference voltage Vref _ soft, and the output voltage Vout can also gradually increase from 0V along with the sampling voltage Vfb, thereby realizing the stable establishment of the output voltage Vout.
The reference voltage Vref _ soft gradually increases from an initial value, which is a ramp voltage with a fixed slope, and is equal to or less than 0V.
In some embodiments, the initial value is 0V and the slope is 1. At this time, the output voltage Vout can also be gradually increased from 0V, and the slope is fixed, and the output voltage Vout of the linear regulator is smoothly established.
In other embodiments, the initial value and slope may also be set as desired.
In the embodiment shown in fig. 2, the first current source 1011 includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4, and gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the first predetermined voltage source to obtain a first predetermined voltage VBP; the source electrode of the third PMOS transistor MP3 is used for receiving an input voltage VDD, and the drain electrode is connected to the source electrode of the first PMOS transistor MP 1; the source of the fourth PMOS transistor MP4 is for receiving the input voltage VDD, and the drain is connected to the source of the second PMOS transistor MP 2.
The first preset voltage VBP may control source-drain resistances of the third PMOS transistor MP3 and the fourth PMOS transistor MP4, so as to control a magnitude of the first current. In practice, the magnitude of the first current may also be controlled by controlling the input voltage VDD. When the magnitude of the first current changes, the first boost voltage Vup1 and the second boost voltage Vup2 also change.
The error amplifying module 102 includes a second current source 1021 and an input pair transistor 1022.
The second current source 1021 is used for providing a second current to the input pair transistor 1022, and includes: a fifth PMOS transistor MP5 having a source for receiving an input voltage VDD, a drain connected to the drain of the first NMOS transistor MN1, and a gate and a drain connected to each other; a sixth PMOS transistor MP6, having a source for receiving the input voltage VDD, a drain connected to the drain of the second NMOS transistor MN2, and a gate of the sixth PMOS transistor MP6 connected to the gate of the fifth PMOS transistor MP 5.
The input pair of tubes 1022 includes: a first NMOS transistor MN1, having a drain connected to the second current source 1021 to obtain the second current, a source grounded through a bias current source, and a gate connected to the output end of the soft start module to obtain the second boost Vup 2; a second NMOS transistor MN2, having a drain connected to the second current source 1021 to obtain the second current, a source grounded through the bias current source, and a gate connected to the output of the soft start module to obtain the first boost Vup 1. The error amplification value Vea-out is output from the source of the second NMOS transistor MN2 and input to the output module 103.
In an embodiment shown in fig. 2, the bias current source includes a third NMOS transistor MN3, a gate of the third NMOS transistor MN3 is configured to receive a control gate voltage VBN, and control the third NMOS transistor MN3 to conduct. The drain electrode of the third NMOS transistor MN3 is connected to the source electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2, and the source electrode of the third NMOS transistor MN3 is grounded.
When the first NMOS transistor MN1 is turned on, the first boost voltage Vup1 is greater than or equal to the sum of the threshold voltage of the first NMOS transistor MN1 and the overdrive voltage of the third NMOS transistor MN 3. When the second NMOS transistor MN2 is turned on, the second boost voltage Vup2 is greater than or equal to the sum of the threshold voltage of the second NMOS transistor MN2 and the overdrive voltage of the third NMOS transistor MN 3. The overdrive voltage is the difference between the gate-source voltage VGS and the conduction threshold value VTH of the MOS tube.
Fig. 3 is a schematic circuit diagram of the soft start module and the error amplification module in an embodiment.
In this embodiment, the boosting unit 1012 further includes an eighth PMOS transistor MP 8. The conduction threshold of the first PMOS transistor MP1 is set to be smaller than the reference voltage Vref, after the reference voltage Vref _ soft is increased to be equal to the reference voltage Vref, the first PMOS transistor MP1 is turned off, the eighth PMOS transistor MP8 boosts the reference voltage Vref obtained by the gate, and the source outputs a third boost voltage Vup3 to the gate of the second NMOS transistor of the error amplification module 102. The error amplifying module 102 compares the third boost voltage Vup3 and the second boost voltage Vup2, and outputs the error amplification value Vea-out according to the comparison result.
The width-to-length ratio of the eighth PMOS transistor MP8 is much smaller than that of the first PMOS transistor MP1, and the eighth PMOS transistor MP8 is turned off at the initial start-up.
In this embodiment, although an eighth PMOS transistor MP8 and a reference voltage source are additionally provided, the accuracy of the reference voltage Vref can be ensured after the linear regulator normally operates without relying on the gradually increasing reference voltage Vref _ soft to ensure the reference voltage Vref used after the linear regulator normally operates.
Fig. 4 is a schematic circuit diagram of the output module 103 according to an embodiment.
In this embodiment, the output module 103 includes: a seventh PMOS transistor MP7, having a gate connected to the output terminal of the error amplifying module to obtain the error amplified value Vea-out, where the output terminal refers to the source of the second NMOS transistor MN2 in fig. 2 and 3, the source of the seventh PMOS transistor MP7 is connected to the input voltage VDD, the drain is grounded through the voltage dividing unit 301, and the output voltage Vout is output through the drain.
When the error amplification value Vea-out is regulated, the error amplification value Vea-out adjusts the source-drain resistance of the seventh PMOS transistor MP7, so as to regulate the drain voltage of the seventh PMOS transistor MP7, i.e., the output voltage Vout.
The voltage dividing unit 301 includes a first resistor R1 and a second resistor R2 connected in sequence, and the other end of the first resistor R1 is connected to the drain of the seventh PMOS transistor MP7, and the other end of the second resistor R2 is grounded. The sampled voltage Vfb is output from the junction of the first resistor R1 and the second resistor R2 to the soft-start module 101. The magnitude relationship of the first resistor R1 and the second resistor R2 influences the proportional relationship of the sampled voltage Vfb and the output voltage Vout. Specifically, the method comprises the following steps:
Vfb＝Vout*R1/(R1+R2)；
wherein Vfb is the sampled voltage Vfb, Vout is the output voltage Vout, R1 is the resistance of the first resistor R1, and R2 is the resistance of the second resistor R2. In this embodiment, the resistances of the first resistor R1 and the second resistor R2 may be set as needed so that the magnitude of the sampled voltage Vfb is moderate.
The embodiment of the application also provides a soft start method of the linear voltage regulator.
Fig. 5 is a flowchart illustrating a soft-start method of a linear regulator according to an embodiment of the present disclosure.
In this embodiment, the soft start method includes the steps of:
step S401: providing a reference voltage, and performing boosting processing on the reference voltage to obtain a first boosted voltage, wherein the reference voltage can be gradually increased from an initial value to the reference voltage, the initial value is less than or equal to the reference voltage, and the reference voltage is finally increased to the reference voltage;
step S402: sampling the output voltage of the linear voltage stabilizer to obtain a sampling voltage, and performing boosting processing on the sampling voltage to obtain a second boosting voltage;
step S403: comparing the first boost voltage with the second boost voltage, and amplifying the error of the first boost voltage and the second boost voltage;
step S404: and adjusting the output of the linear voltage stabilizer according to the error amplification value after error amplification.
When the first boost pressure and the second boost pressure are obtained, the method comprises the following steps: providing a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, wherein source electrodes of the first PMOS tube and the second PMOS tube are connected to a first current source to obtain a first current, and drain electrodes of the first PMOS tube and the second PMOS tube are grounded; and outputting the reference voltage to a grid electrode of a first PMOS tube, outputting the sampling voltage to a grid electrode of a second PMOS tube, acquiring a grid-source voltage of the first PMOS tube as the first boost voltage, and acquiring a grid-source voltage of the second PMOS tube as the second boost voltage.
Embodiments of the present application further include an electronic device including the linear regulator described in the above embodiments.
The electronic equipment is provided with the linear voltage regulator, so that soft start can be realized, and the linear voltage regulator is effectively prevented from being out of order at the initial starting stage.
The application discloses linear voltage regulator, soft start method and electronic equipment, through the soft start module is right reference voltage and sampling voltage boost, guarantee input geminate transistor among the error amplification module just can be driven at initial start phase, prevent linear voltage regulator is in initial start phase imbalance. And the reference voltage is gradually increased from the initial value until the reference voltage is increased, so that the gradual increase of the output voltage is ensured.
In addition, the linear voltage regulator, the soft start method and the electronic equipment have the characteristics of simple structure, are insensitive to external factors such as current load, output capacitance and the like, and can realize smooth establishment of the output voltage of the linear voltage regulator with the pair transistors of N-type input.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by the contents of the specification and the drawings, such as the combination of technical features between the embodiments and the direct or indirect application to other related technical fields, are also included in the scope of the present application.
Claims (11)
1. A linear regulator, comprising:
the soft start module is used for boosting a signal input by an input end and comprises at least two input ends, wherein the first input end is used for acquiring reference voltage, the second input end is used for acquiring sampling voltage, and the reference voltage can gradually rise from an initial value to reference voltage;
the error amplification module comprises at least two input ends, wherein a first input end is used for being connected to the output end of the soft start module so as to obtain a first boost corresponding to the boosted reference voltage, a second input end is also connected to the output end of the soft start module so as to obtain a second boost corresponding to the boosted sampling voltage, the difference value of the first boost and the second boost is amplified, and an error amplification value is output;
the error amplification value is used for adjusting the output voltage of the linear voltage stabilizer, and the sampling voltage is sampled from the output voltage.
2. The linear regulator of claim 1, wherein the soft start module comprises:
a first current source for providing a first current;
and the boosting unit is connected to the first current source and used for acquiring the reference voltage and the sampling voltage so as to output corresponding first boosting voltage and second boosting voltage according to the reference voltage and the sampling voltage.
3. The linear regulator according to claim 2, wherein the boosting unit includes:
the first PMOS tube is used for acquiring the reference voltage by a conduction threshold value, a grid electrode is used for acquiring the reference voltage, a source electrode is connected to the output end of the first current source so as to acquire the first current and is used for outputting the first boosting voltage, and a drain electrode is grounded;
and the grid electrode of the second PMOS tube is used for receiving the sampling voltage, the source electrode of the second PMOS tube is connected to the output end of the first current source so as to obtain the first current and is used for outputting the second boosting voltage, and the drain electrode of the second PMOS tube is grounded.
4. The linear regulator of claim 3, wherein the first current source comprises a third PMOS transistor and a fourth PMOS transistor, and gates of the third PMOS transistor and the fourth PMOS transistor are connected to a first preset voltage source to obtain a first preset voltage;
the source electrode of the third PMOS tube is used for obtaining the input voltage of the linear voltage stabilizer, and the drain electrode of the third PMOS tube is connected to the source electrodes of the first PMOS tube and the second PMOS tube;
and the source electrode of the fourth PMOS tube is used for acquiring the input voltage of the linear voltage stabilizer, and the drain electrode of the fourth PMOS tube is connected to the source electrode of the third PMOS tube.
5. The linear regulator of claim 1, wherein the error amplification module comprises a second current source and an input pair transistor, the second current source for providing a second current to the input pair transistor, the input pair transistor comprising:
a drain of the first NMOS transistor is connected to the second current source to obtain the second current, a source of the first NMOS transistor is grounded through a bias current source, and a gate of the first NMOS transistor is connected to an output end of the soft start module to obtain the second boost voltage;
and the drain electrode of the second NMOS tube is connected to the second current source to obtain the second current, the source electrode of the second NMOS tube is grounded through the bias current source, and the grid electrode of the second NMOS tube is connected to the output end of the soft start module to obtain the first boosting.
6. The linear regulator of claim 5, wherein the second current source comprises:
a fifth PMOS tube, a source electrode is used for receiving input voltage, a drain electrode is connected to the drain electrode of the first NMOS tube, and the grid electrode and the drain electrode of the fifth PMOS tube are mutually connected;
and the source electrode of the sixth PMOS tube is used for receiving the input voltage, the drain electrode of the sixth PMOS tube is connected to the drain electrode of the second NMOS tube, and the grid electrode of the sixth PMOS tube is connected to the grid electrode of the sixth PMOS tube.
7. The linear regulator of claim 1, further comprising an output module, the output module comprising:
a seventh PMOS tube, a grid electrode of which is connected to the output end of the error amplification module, a source electrode of which is connected to the input voltage, and a drain electrode of which is grounded through a voltage division unit and outputs the output voltage through the drain electrode;
the voltage division unit comprises a first resistor and a second resistor which are connected in sequence, the upper end of the first resistor is connected to the drain electrode of the seventh PMOS tube, and the lower end of the second resistor is grounded.
8. The linear regulator of claim 1, wherein the initial value is equal to or less than 0V.
9. A soft start method of a linear voltage regulator is characterized by further comprising the following steps:
providing a reference voltage, and performing boosting processing on the reference voltage to obtain a first boosted voltage, wherein the reference voltage can be gradually increased from an initial value to a reference voltage;
sampling the output voltage of the linear voltage stabilizer to obtain a sampling voltage, and performing boosting processing on the sampling voltage to obtain a second boosting voltage;
comparing the first boost voltage with the second boost voltage, and amplifying the error of the first boost voltage and the second boost voltage;
and adjusting the output of the linear voltage stabilizer according to the error amplification value after error amplification.
10. The soft-start method of claim 9, wherein obtaining the first boost voltage and the second boost voltage comprises:
providing a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, wherein source electrodes of the first PMOS tube and the second PMOS tube are connected to a first current source to obtain a first current, and drain electrodes of the first PMOS tube and the second PMOS tube are grounded;
and outputting the reference voltage to a grid electrode of a first PMOS tube, outputting the sampling voltage to a grid electrode of a second PMOS tube, acquiring a grid-source voltage of the first PMOS tube as the first boost voltage, and acquiring a grid-source voltage of the second PMOS tube as the second boost voltage.
11. An electronic device comprising the linear regulator according to any one of claims 1 to 8.
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