CN113359007B - Method and system for displaying wafer test chart - Google Patents
Method and system for displaying wafer test chart Download PDFInfo
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- CN113359007B CN113359007B CN202110602519.7A CN202110602519A CN113359007B CN 113359007 B CN113359007 B CN 113359007B CN 202110602519 A CN202110602519 A CN 202110602519A CN 113359007 B CN113359007 B CN 113359007B
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Abstract
The invention provides a method and a system for displaying a wafer test chart, which comprises the steps of obtaining attribute files of a plurality of chips on a wafer after the wafer sampling test, then correcting the attribute files through a preset algorithm to obtain correction files of the plurality of chips on the wafer, and then generating and displaying the corrected wafer test chart according to the correction files. According to the invention, by correcting the attribute files of a plurality of chips on the wafer, the distance between adjacent test chips on the wafer is reduced, the existence sense of untested chips is weakened, the display area of the test chips in the set wafer test chart display area is increased, the tested chips are highlighted in the wafer test chart, and the observation is facilitated. In addition, the test chips are displayed in a centralized manner, so that the overall distribution condition of the failed chips in the test chips is convenient to observe.
Description
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a method and a system for displaying a wafer test chart.
Background
In the wafer test process of IC (integrated circuit), the actual test result is analyzed to reflect the technological parameter condition of the previous process, so that the parameters of the wafer flow process of the previous process are monitored and adjusted to improve the yield of the product. There are many kinds of displays of test result information, among which the wafer test MAP (MAP) display is the most effective display mode currently and can visually reflect the IC yield distribution and the test result of the wafer-flow process in the previous process. The MAP display means that the actual test result is displayed in the form of an actual wafer graph, and different colors are used to display different test BIN distribution conditions.
The conventional MAP display generation method generally tests a wafer IC through a general integrated circuit test system and a Prober probe device, transmits a test BIN result of a coordinate value generated by the Prober probe device and a corresponding IC coordinate value generated by the general integrated circuit test system to a PC, generates a MAP initial text file at the PC, and converts the text file into a graphic file by using a corresponding MAP conversion tool, so as to intuitively reflect actual wafer IC test information. The MAP graph display function can be directly or indirectly realized for various general integrated circuit test systems.
The probe test of the wafer mainly aims to pick out the defective products before packaging, so that unnecessary packaging cost is saved, but some products have high yield, and some products reach 99% or even higher, and at this time, the sampling test can be performed on the products. Sampling test (Sampling) is a method in which a product engineer selects some chips on a wafer map as reference chips for a first batch of tests according to test data of a period of time and some relevant information during production. When the test is started, the system firstly gives a probe machine to sequentially move to the selected chip position for testing, a good product rate is calculated after all the reference chips are tested, the system compares the good product rate with a threshold value set in a file system, if the good product rate of the reference chips is higher than the threshold value, the whole wafer is tested, the good product rate of all the chips except the reference position on the wafer is defaulted to 100%, in addition, the reference chips except the sampling test can also be defined, and the positions of the chips which are forcibly tested are generally at the edge of the wafer. Alternatively, if the sampling result is lower than the threshold, the system will automatically require the prober to test all untested chips from the beginning, and finally obtain a complete wafer test pattern.
The test chart for the wafer Sampling (Sampling) test is displayed according to the actual coordinates of the test, when the size of a chip (Die) is small, namely the number of core particles contained on one wafer is large (tens of thousands of the core particles are frequently), the test points of the Sampling test are distributed at the set position of the MAP, the test points are displayed on the page displaying the MAP very small, and the observation is very difficult.
Disclosure of Invention
The invention aims to provide a method and a system for displaying a wafer test chart, which enable a tested chip to be highlighted in the wafer test chart for convenient observation.
To achieve the above object, the present invention provides a method for displaying a wafer test chart, comprising:
obtaining attribute files of a plurality of chips on a wafer after the wafer sampling test;
correcting the attribute file through a preset algorithm to obtain correction files of a plurality of chips on the wafer; and
generating a corrected wafer test chart according to the correction file and displaying the corrected wafer test chart;
wherein the modification processing of the property file includes: and reducing the distance between adjacent test chips on the wafer so as to increase the display area of the test chips in the set wafer test chart display area.
Optionally, the attribute file includes coordinate information and type information of the chip, a test chip and an untested chip are determined according to the type information, and the distance between adjacent test chips is reduced by correcting the coordinate information.
Optionally, the preset algorithm reduces the distance between the adjacent test chips by reducing the number of untested chips spaced between the adjacent test chips in the attribute file.
Optionally, reducing the distance between the adjacent test chips by reducing the number of untested chips spaced between the adjacent test chips in the attribute file includes: correcting the number of untested chips spaced between adjacent test chips from M to M in the X direction, and correcting the number of untested chips spaced between adjacent test chips from N to N in the Y direction, wherein M is greater than M and is not less than 2, and N is greater than N and is not less than 2.
Optionally, the test chips include a qualified chip and a failed chip, and are displayed in the corrected wafer test chart in a distinguishing manner through different marks.
Optionally, before generating the modified wafer test pattern according to the modification file, the method further includes: and generating a standard wafer test chart according to the attribute file.
Optionally, the method further includes: and switching and displaying the standard wafer test chart and the corrected wafer test chart according to a set instruction.
Optionally, the standard wafer test chart and the corrected wafer test chart have the same display area.
Correspondingly, the invention also provides a display system of the wafer test chart, which comprises:
the attribute file acquisition module is used for acquiring attribute files of a plurality of chips on the wafer subjected to sampling test;
the attribute file correction module is used for correcting the attribute file according to a preset algorithm to obtain correction files of a plurality of chips on the wafer;
the wafer test pattern generation module is used for generating a corrected wafer test pattern according to the corrected file; and the number of the first and second groups,
the wafer test chart display module is used for displaying the generated corrected wafer test chart;
wherein the modification processing of the property file includes: and reducing the distance between adjacent test chips on the wafer so as to increase the display area of the test chips in the set wafer test chart display area.
Optionally, the attribute file includes coordinate information and type information of the chip, a test chip and an untested chip are determined according to the type information, and the distance between adjacent test chips is reduced by correcting the coordinate information.
Optionally, the test chips include a qualified chip and a failed chip, and the modified wafer test chart is displayed in a differentiated manner through different marks.
Optionally, the preset algorithm reduces the distance between the adjacent test chips by reducing the number of untested chips spaced between the adjacent test chips in the attribute file.
Optionally, the wafer test pattern generating module is further configured to generate a standard wafer test pattern according to the attribute file.
Optionally, the standard wafer test chart and the corrected wafer test chart have the same display area.
Optionally, the display module of the wafer test chart further includes: and the display switching unit is used for switching and displaying the standard wafer test chart and the corrected wafer test chart according to a set instruction.
The invention provides a method and a system for displaying a wafer test chart, which comprises the steps of obtaining attribute files of a plurality of chips on a wafer after the wafer sampling test, then correcting the attribute files through a preset algorithm to obtain correction files of the plurality of chips on the wafer, and then generating and displaying the corrected wafer test chart according to the correction files. According to the invention, by correcting the attribute files of a plurality of chips on the wafer, the distance between adjacent test chips on the wafer is reduced, the existence sense of untested chips is weakened, the display area of the test chips in the set wafer test chart display area is increased, the tested chips are highlighted in the wafer test chart, and the observation is facilitated.
Furthermore, the test chips are displayed in a centralized manner, so that the overall distribution condition of the failed chips in the test chips can be observed conveniently.
Furthermore, an operator can switch and display the standard wafer test chart and the corrected wafer test chart according to requirements, the actual distribution condition of the test chips is kept while the test chips are highlighted, and the accuracy of the test results is kept.
Drawings
Fig. 1 is a flowchart illustrating a method for displaying a wafer test chart according to an embodiment of the present invention;
FIG. 2 is a display portion of a standard wafer test chart generated from an attribute file according to an embodiment of the present invention;
FIG. 3 is a display portion of a modified wafer test chart obtained from a modification file according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a system for displaying a wafer test chart according to an embodiment of the present invention.
Wherein the reference numerals are:
100-standard wafer test pattern; 110-untested chip; 120-test chip;
200-correcting the wafer test chart; 210-untested chips; 220-test chip.
Detailed Description
The method and system for displaying wafer test charts provided by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the inventive concepts may be embodied in many different forms and are not limited to the specific embodiments described herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
Fig. 1 is a flowchart of a method for displaying a wafer test chart according to this embodiment. As shown in fig. 1, the method for displaying a wafer test chart provided by the present invention includes:
s01: obtaining attribute files of a plurality of chips on a wafer after the wafer sampling test;
s02: correcting the attribute file through a preset algorithm to obtain correction files of a plurality of chips on the wafer; and the number of the first and second groups,
s03: and generating and displaying a corrected wafer test chart according to the correction file.
The method for displaying the wafer test chart provided in the present embodiment will be described in detail with reference to fig. 1.
First, step S01 is executed: and acquiring attribute files of a plurality of chips on the wafer after the wafer sampling test. Selecting a chip for sampling test from a plurality of chips (die) of a wafer according to a certain sampling rule to carry out corresponding test, wherein the test is for example wafer electrical test, placing the wafer to be tested on a probe station, and carrying out test and scanning on the wafer by the probe station to obtain attribute files of the plurality of chips on the wafer. The attribute file comprises coordinate information and type information of the chips, and the distribution conditions of a plurality of chips on the wafer can be determined according to the coordinate information to form a wafer map. The type information includes whether the chip is an edge chip, a test chip, a mark chip or the like, in this embodiment, the chip can be determined to be a test chip and an untested chip according to the type information of the chip, the test chip includes a qualified chip and a failed chip, the distribution of the test chip in the wafer map can be determined by combining the coordinate information and the type information, and then the distribution of the failed chip can be determined according to the test result.
And then, executing step S02, and correcting the attribute file through a preset algorithm to obtain corrected files of a plurality of chips on the wafer. Wherein the modification processing of the property file includes: and reducing the distance between adjacent test chips on the wafer so as to increase the display area of the test chips in the set wafer test chart display area. Specifically, the distance between adjacent test chips can be reduced by performing correction processing on the coordinate information. For example, the preset algorithm reduces the distance between the adjacent test chips by reducing the number of untested chips spaced between the adjacent test chips in the attribute file, and includes: correcting the number of untested chips spaced between adjacent test chips from M to M in the X direction, and correcting the number of untested chips spaced between adjacent test chips from N to N in the Y direction, wherein M is greater than M and is not less than 2, and N is greater than N and is not less than 2.
And then, executing step S03, generating a corrected wafer test chart according to the corrected file and displaying the corrected wafer test chart. The attribute file may be converted into a graphic file, for example, by a MAP conversion tool, and displayed on a display device. In this embodiment, a standard wafer test chart reflecting the actual distribution of the test chips may be obtained according to the attribute file obtained in step S01, and a corrected wafer test chart may be obtained according to the correction file, and an operator may select to display the standard wafer test chart or the corrected wafer test chart according to a requirement, for example, the standard wafer test chart and the corrected wafer test chart may be switched and displayed according to a set instruction, and the actual distribution of the test chips is maintained while the test chips are highlighted, so as to maintain the accuracy of the test results. The standard wafer test chart and the corrected wafer test chart have the same display area, and because the distance between adjacent test chips is reduced in the corrected wafer test chart, the test chips in the corrected wafer test chart are more prominent in the same display area compared with the standard wafer test chart.
It should be noted that, in this embodiment, after the attribute file is modified to obtain a modified file, the original attribute file is retained, and the obtaining of the standard wafer test chart according to the attribute file may be performed before or after the modification of the attribute file, of course, the generating of the standard wafer test chart may be performed before or after the generating of the modified wafer test chart, and preferably, the generating of the standard wafer test chart is performed before the generating of the modified wafer test chart.
FIG. 2 is a display portion of a standard wafer test chart generated from an attribute file, and FIG. 3 is a display portion of a corrected wafer test chart obtained from a correction file. The test chips include a qualified chip and a failed chip, and the qualified chip and the failed chip can be distinguished and displayed in the corrected wafer test chart through different marks, for example, different pattern marks or color marks are adopted, in fig. 2 and 3, only the test chips and untested chips are distinguished, and the qualified chips and the failed chips are not distinguished. Referring to fig. 2 and 3, for the standard wafer test chart 100, in the X direction, the number M of untested chips 110 spaced between adjacent test chips 120 is 4, and in the Y direction, the number N of untested chips spaced between adjacent test chips 120 is 5; for the corrected wafer test pattern 200, the number m of untested chips 210 spaced between adjacent test chips 220 is 2, and the number n of untested chips 210 spaced between adjacent test chips 220 in the Y direction is 3. Comparing fig. 2 and fig. 3, it can be seen that, in the modified wafer test chart 200, the coordinate positions of the chips are modified, so that the distance between adjacent test chips on the wafer is reduced, the existence of untested chips is weakened, the tested chips are highlighted in the wafer test chart (MAP), the overall distribution of the test chips is convenient to observe, and the distribution of the failed chips is further determined.
In this embodiment, after the coordinate positions of the chips are corrected, the number M of untested chips spaced between the adjacent test chips in the X direction and the number N of untested chips spaced between the adjacent test chips in the Y direction may be determined according to the final display effect by combining the actual number M of untested chips spaced between the adjacent test chips in the X direction and the actual number N of untested chips spaced between the adjacent test chips in the Y direction. For example, after the correction, the number m of untested chips spaced between the X-direction adjacent test chips may be 2, and the number n of untested chips spaced between the Y-direction adjacent test chips may be 4.
Further, the present embodiment further provides a display system of a wafer test chart, as shown in fig. 4, including:
the attribute file acquisition module is used for acquiring attribute files of a plurality of chips on the wafer subjected to sampling test;
the attribute file correction module is used for correcting the attribute file according to a preset algorithm to obtain correction files of a plurality of chips on the wafer;
the wafer test chart generating module is used for generating a corrected wafer test chart according to the correction file; and
the wafer test chart display module is used for displaying the generated corrected wafer test chart;
wherein the modification processing of the property file includes: and reducing the distance between adjacent test chips on the wafer so as to increase the display area of the test chips in the set wafer test chart display area.
Optionally, the attribute file includes coordinate information and type information of the chips, a test chip and an untested chip are determined according to the type information, and the distance between adjacent test chips is reduced by correcting the coordinate information.
Optionally, the test chips include a qualified chip and a failed chip, and the modified wafer test chart is displayed in a differentiated manner through different marks.
Optionally, the preset algorithm reduces the distance between the adjacent test chips by reducing the number of untested chips spaced between the adjacent test chips in the attribute file.
Optionally, the wafer test pattern generating module is further configured to generate a standard wafer test pattern according to the attribute file.
Optionally, the standard wafer test chart and the corrected wafer test chart have the same display area.
Optionally, the display module of the wafer test chart further includes: and the display switching unit is used for switching and displaying the standard wafer test chart and the corrected wafer test chart according to a set instruction.
In summary, the present invention provides a method and a system for displaying a wafer test chart, which includes obtaining attribute files of a plurality of chips on a wafer after a wafer sampling test, then performing a correction process on the attribute files through a preset algorithm to obtain correction files of the plurality of chips on the wafer, and then generating and displaying a corrected wafer test chart according to the correction files. According to the invention, by correcting the attribute files of a plurality of chips on the wafer, the distance between adjacent test chips on the wafer is reduced, the existence sense of untested chips is weakened, the display area of the test chips in the set wafer test chart display area is increased, the tested chips are highlighted in the wafer test chart, and the observation is facilitated. In addition, the test chips are displayed in a centralized manner, so that the overall distribution condition of the failed chips in the test chips is convenient to observe. Furthermore, an operator can switch and display the standard wafer test chart and the corrected wafer test chart according to requirements, the actual distribution condition of the test chips is kept while the test chips are highlighted, and the accuracy of the test results is kept.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (15)
1. A method for displaying a wafer test chart is characterized by comprising the following steps:
acquiring attribute files of a plurality of chips selected and tested on a wafer by sampling;
correcting the attribute file by a preset algorithm to obtain corrected files of a plurality of chips selected and tested on the wafer by sampling,
generating a corrected wafer test chart according to the correction file and displaying the corrected wafer test chart;
wherein the modification processing of the property file includes: and reducing the distance between adjacent test chips on the wafer so as to increase the display area of the test chips in the set wafer test chart display area.
2. The method as claimed in claim 1, wherein the property file includes coordinate information and type information of the chips, the chips under test and the chips under test are determined according to the type information, and the distance between adjacent chips under test is reduced by correcting the coordinate information.
3. The method as claimed in claim 2, wherein the predetermined algorithm reduces the distance between the adjacent test chips by reducing the number of untested chips spaced between the adjacent test chips in the property file.
4. The method as claimed in claim 3, wherein the reducing the distance between the adjacent test chips by reducing the number of untested chips spaced between the adjacent test chips in the property file comprises: correcting the number of untested chips spaced between adjacent test chips from M to M in the X direction, and correcting the number of untested chips spaced between adjacent test chips from N to N in the Y direction, wherein M is greater than M and is not less than 2, and N is greater than N and is not less than 2.
5. The method as claimed in claim 1, wherein the test chips include a pass chip and a fail chip, and are distinguished and displayed in the modified wafer test chart by marking different colors.
6. The method as claimed in claim 1, wherein before generating the modified wafer test chart according to the modification file, the method further comprises: and generating a standard wafer test chart according to the attribute file.
7. The method for displaying the wafer test chart according to claim 6, further comprising: and switching and displaying the standard wafer test chart and the corrected wafer test chart according to a set instruction.
8. The method as claimed in claim 7, wherein the standard wafer test chart and the modified wafer test chart have the same display area.
9. A system for displaying a wafer test chart, comprising:
the attribute file acquisition module is used for acquiring attribute files of a plurality of chips selected and tested on the wafer by sampling;
the attribute file correction module is used for correcting the attribute file according to a preset algorithm to obtain correction files of a plurality of chips selected and tested on the wafer by sampling;
the wafer test chart generating module is used for generating a corrected wafer test chart according to the correction file; and
the wafer test chart display module is used for displaying the generated corrected wafer test chart;
wherein the modification processing of the property file includes: and reducing the distance between adjacent test chips on the wafer so as to increase the display area of the test chips in the set wafer test chart display area.
10. The system of claim 9, wherein the property file includes coordinate information and type information of the chips, the test chips and the untested chips are determined according to the type information, and the distance between adjacent test chips is reduced by correcting the coordinate information.
11. The system for displaying wafer test patterns according to claim 10, wherein the predetermined algorithm reduces the distance between adjacent test chips by reducing the number of untested chips spaced between the adjacent test chips in the property file.
12. The system for displaying the wafer test chart according to claim 10, wherein the test chips comprise a qualified chip and a failed chip, and the modified wafer test chart is displayed in a differentiated manner by marking different colors.
13. The system for displaying the wafer test chart according to claim 9, wherein the wafer test chart generating module is further configured to generate a standard wafer test chart according to the attribute file.
14. The system of claim 13, wherein the standard wafer test chart and the modified wafer test chart have the same display area.
15. The system for displaying wafer test charts of claim 14, wherein the module for displaying wafer test charts further comprises: and the display switching unit is used for switching and displaying the standard wafer test chart and the corrected wafer test chart according to a set instruction.
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| JP2001144148A (en) * | 2001-05-12 | 2001-05-25 | Advantest Corp | Wafer map display device for semiconductor testing device |
| JP2001267389A (en) * | 2000-03-21 | 2001-09-28 | Hiroshima Nippon Denki Kk | System and method for producing semiconductor memory |
| JP4958659B2 (en) * | 2007-07-03 | 2012-06-20 | キヤノン株式会社 | Image display control device, image display control method, program, and recording medium |
| US7682842B2 (en) * | 2008-05-30 | 2010-03-23 | International Business Machines Corporation | Method of adaptively selecting chips for reducing in-line testing in a semiconductor manufacturing line |
| JP2010073783A (en) * | 2008-09-17 | 2010-04-02 | Yokogawa Electric Corp | Lsi tester |
| CN105224776B (en) * | 2014-05-26 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer test result comparison method and system |
| KR102620433B1 (en) * | 2016-09-30 | 2024-01-03 | 세메스 주식회사 | Method of forming a wafer map |
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| US6868513B1 (en) * | 2000-10-26 | 2005-03-15 | International Business Machines Corporation | Automated multi-device test process and system |
| CN1770255A (en) * | 2004-11-02 | 2006-05-10 | 三星Techwin株式会社 | Apparatus and method for controlling the position of an image when enlarging or reducing the image |
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