CN113348498A

CN113348498A - Display panel and display device

Info

Publication number: CN113348498A
Application number: CN201980079788.0A
Authority: CN
Inventors: 陈丹
Original assignee: Shenzhen Royole Technologies Co Ltd
Current assignee: Shenzhen Royole Technologies Co Ltd
Priority date: 2019-04-08
Filing date: 2019-04-08
Publication date: 2021-09-03
Also published as: WO2020206593A1

Abstract

A display panel (100) comprises a display area (1), and a first wiring area (21) and a second wiring area (22) which are arranged on two opposite sides of the display area (1). The display area (1) comprises pixel areas (13) distributed in an array mode, a first driving circuit (23) is arranged in the first wiring area (21), a second driving circuit (24) is arranged in the second wiring area (22), the first driving circuit (23) is used for generating a first control signal, the second driving circuit (24) is used for generating a second control signal, and the first driving circuit (23) and the second driving circuit (24) are matched with each other to control the light emitting unit (130) to work. A display device (200) having the display panel (100) is also provided. The real-time brightness of the pixel area (13) can be controlled, and bright and dark lines are prevented from being generated on the display panel (100).

Description

Display panel and display device

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a display panel and a display device.

Background

The Gate Driver On Array (GOA) technology is to fabricate a Gate scan driving circuit On a thin film transistor Array substrate to realize a line-by-line scan driving method. The GOA driving circuit is used for generating scanning driving signals and transmitting the scanning driving signals to corresponding scanning lines so as to control the on-off of the thin film transistors in the pixel area. How to reasonably design a GOA driving circuit on a display panel to accurately control the real-time brightness of a pixel area and prevent bright and dark lines from being generated on the display panel becomes a technical problem to be solved.

Disclosure of Invention

The application provides a display panel and a display device which can accurately control the real-time brightness of a pixel area and prevent bright and dark lines from being generated on the display panel.

In one aspect, the application provides a display panel, display panel includes the display area and locates the first wiring district and the second wiring district of the relative both sides of display area, the display area is including the pixel district that is array distribution, first wiring district is equipped with first drive circuit, the second wiring district is equipped with second drive circuit, first drive circuit is used for producing first control signal, second drive circuit is used for producing second control signal, first drive circuit reaches second drive circuit cooperatees in order to control the luminescence unit work.

In another aspect, the present application provides a display device including the display panel.

The first drive circuit is arranged on one side of the display area, so that the thin film transistors in the first drive circuit can be manufactured in the same process, the second drive circuit is arranged on the other side of the display area, so that the thin film transistors in the second drive circuit can be manufactured in the same process, the consistency of the thin film transistors in the first drive circuit and the consistency of the thin film transistors in the second drive circuit are improved, the light emitting units in each row of pixel area are accurately controlled to emit light, bright and dark lines generated in the pixel area are reduced, and the uniformity of the brightness display of the display panel is improved; in addition, the first driving circuit and the second driving circuit respectively occupy the positions of the two opposite sides of the display area, so that the symmetry of the display panel is improved, the problem that the first driving circuit and the second driving circuit are arranged on the same side of the display area to cause overlarge width of the peripheral area is solved, and the narrow frame design of the display panel is promoted.

Drawings

In order to more clearly illustrate the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of a pixel circuit in a pixel region of a display panel according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of a first driving circuit of a display panel according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of a second driving circuit of a display panel according to an embodiment of the present disclosure.

Fig. 5 is a timing diagram of control signals of a pixel circuit in a display panel according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The display panel 100 may be a flat display panel, a flexible screen, or the like. The flexible screen refers to a bendable screen or a foldable screen. The display panel 100 includes a display area 1, and a first wiring area 21 and a second wiring area 22 disposed on two opposite sides of the display area 1. The display area 1 includes pixel regions 13 distributed in an array.

Referring to fig. 1 and fig. 2 together, fig. 2 is a schematic structural diagram of a pixel circuit in a pixel region of a display panel according to an embodiment of the present disclosure. The first wiring region 21 is provided with a first drive circuit 23. The first driving circuit 23 is used for generating a first control signal. The second wiring region 22 is provided with a second drive circuit 24. The second driving circuit 24 is used for generating a second control signal. The first driving circuit 23 and the second driving circuit 24 cooperate to control the operation of the light emitting unit 130.

The first driving circuit 23 is arranged at one side of the display area 1, so that the thin film transistors in the first driving circuit 23 can be manufactured in the same process, and the consistency of the thin film transistors in the first driving circuit 23 is improved; by arranging the second driving circuit 24 at the other side of the display area, the thin film transistors in the second driving circuit 24 can be manufactured in the same process, so as to improve the consistency of the thin film transistors in the second driving circuit 24, accurately control the light emitting units 130 in each row of pixel areas 13 to emit light, reduce the bright and dark lines generated by the pixel areas 13, and improve the uniformity of the brightness display of the display panel 100; moreover, the first driving circuit 23 and the second driving circuit 24 respectively occupy the two opposite sides of the display area 1, so as to improve the symmetry of the display panel 100, avoid the problem that the first driving circuit 23 and the second driving circuit 24 are arranged on the same side of the display area 1, which causes the width of the frame of the display panel 100 to be too large, and promote the narrow frame design of the display panel 100.

Referring to fig. 2, the pixel region 13 is provided with a first transistor T1, a second transistor T2 and a light emitting unit 130. The first control signal is used for controlling the on-off of the first transistor T1. The second control signal is used for controlling the on/off of the second transistor T2. The first transistor T1 and the second transistor T2 cooperate to control the operation of the light emitting cell 130.

Specifically, referring to fig. 1 and fig. 2, the display panel 100 includes a display area 1 and a peripheral area 2 surrounding the display area 1. For example, the display region 1 is rectangular, and the peripheral region 2 is rectangular and annular. The display area 1 is provided with a plurality of rows of scanning lines 11 and a plurality of columns of data lines 12, the plurality of rows of scanning lines 11 are arranged at intervals, the plurality of columns of data lines 12 are arranged at intervals, and the data lines 12 and the scanning lines 11 are arranged in an insulating mode. In one embodiment, the scan lines 11 and the data lines 12 are respectively located at different layers, and the extending direction of the scan lines 11 is perpendicular or approximately perpendicular to the extending direction of the data lines 12. The area formed by the two adjacent scan lines 11 and the two adjacent data lines 12 is a pixel area 13. It is understood that the display area 1 includes a plurality of pixel areas 13 distributed in an array. Each of the pixel regions 13 has a first transistor T1, a second transistor T2, and a light emitting unit 130. The first transistor T1 and the second transistor T2 cooperate to control the brightness of the light emitting unit 130, so that the pixel region 13 where the light emitting unit 130 is located is illuminated, and the light emitting and display interface of the display region 1 is realized.

Specifically, referring to fig. 1 and fig. 2, the peripheral region 2 includes a first wiring region 21 and a second wiring region 22. The first wiring region 21 and the second wiring region 22 are respectively located on opposite sides of the display region 1. For example, referring to fig. 1, the first wiring region 21 and the second wiring region 22 are respectively disposed on the left and right sides of the display region 1. Of course, in other embodiments, the first wiring region 21 and the second wiring region 22 may be provided on both upper and lower sides of the display region 1.

Specifically, referring to fig. 1 and fig. 2, the peripheral region 2 is used for disposing a driving module for driving the light emitting unit 130 to emit light. The driving module includes, but is not limited to, the first driving circuit 23 and the second driving circuit 24. Specifically, the first driving circuit 23 is electrically connected to the first transistor T1 through a signal trace. The signal trace is used for transmitting a first control signal to the first transistor T1 so as to control the first transistor T1 to be turned on or off. In one embodiment, the signal trace may be a scan line 11.

It is understood that, referring to fig. 1 and fig. 2, the first transistor T1 is a thin film transistor, and the first transistor T1 has a gate g11, a first terminal p11 and a second terminal p 12. The gate g11 is electrically connected to the scan line 11, and the first end p11 is electrically connected to the data line 12. Wherein the first terminal p11 of the first transistor T1 is a source, and the second terminal p12 of the first transistor T1 is a drain; alternatively, the first terminal p11 of the first transistor T1 is a drain, and the second terminal p12 of the first transistor T1 is a source. Specifically, taking the first transistor T1 as an N-type transistor as an example, when the voltage difference between the first control signal and the drain of the first transistor T1 is greater than the threshold voltage of the first transistor T1, i.e., when the first control signal at a high level is applied to the gate g11 of the first transistor T1, the first terminal p11 and the second terminal p12 of the first transistor T1 are electrically connected. When the voltage difference between the first control signal and the drain of the first transistor T1 is less than the threshold voltage of the first transistor T1, i.e., the first control signal of low level is applied to the gate g11 of the first transistor T1, the first terminal p11 and the second terminal p12 of the first transistor T1 are disconnected. Of course, in other embodiments, the first transistor T1 may be a P-type transistor, and when the voltage difference between the first control signal and the drain of the first transistor T1 is smaller than the threshold voltage of the first transistor T1, the first terminal P11 and the second terminal P12 of the first transistor T1 are electrically connected; when the voltage difference between the first control signal and the drain of the first transistor T1 is greater than the threshold voltage of the first transistor T1, the first terminal p11 and the second terminal p12 of the first transistor T1 are electrically disconnected.

Specifically, referring to fig. 1 and fig. 2, the second driving circuit 24 is electrically connected to the second transistor T2 through a signal trace, and the signal trace is used for transmitting a second control signal to the second transistor T2 to control the on/off of the second transistor T2. In one embodiment, the signal trace may be a scan line 11.

It is understood that, referring to fig. 1 and fig. 2, the second transistor T2 is a thin film transistor, and the second transistor T2 has a gate g21, a first terminal p21 and a second terminal p 22. The gate g21 is electrically connected to the scan line 11, and the first terminal p21 is used for receiving a first voltage signal VDD. When the conductive path from the second transistor T2 to the light emitting unit 130 is turned on, the first signal is used to drive the light emitting unit 130 to emit light. Wherein, the first end p21 of the second transistor T2 is a source, and the second end p22 of the second transistor T2 is a drain; alternatively, the first terminal p21 of the second transistor T2 is a drain, and the second terminal p22 of the second transistor T2 is a source. Specifically, taking the second transistor T2 as an N-type transistor as an example, when the voltage difference between the second control signal and the drain of the second transistor T2 is greater than the threshold voltage of the second transistor T2, i.e., when the second control signal with a high level is applied to the gate of the second transistor T2, the first terminal p21 and the second terminal p22 of the second transistor T2 are electrically connected. When the voltage difference between the second control signal and the drain of the second transistor T2 is less than the threshold voltage of the second transistor T2, i.e., the second control signal of low level is applied to the gate g21 of the second transistor T2, the first terminal p21 and the second terminal p22 of the second transistor T2 are disconnected. Of course, in other embodiments, the second transistor T2 may be a P-type transistor, and when the voltage difference between the second control signal and the drain of the second transistor T2 is smaller than the threshold voltage of the second transistor T2, the first terminal P21 and the second terminal P22 of the second transistor T2 are electrically connected, and when the voltage difference between the second control signal and the drain of the second transistor T2 is larger than the threshold voltage of the second transistor T2, the first terminal P21 and the second terminal P22 of the second transistor T2 are disconnected.

Specifically, referring to fig. 1 and fig. 2, the first driving circuit 23 is a GOA driving circuit, and the first driving circuit 23 implements progressive scanning of the pixel region 13 of the display region 1 to control the light emitting units 130 in the pixel region 13 to emit light row by row.

In one mode, the first driving circuits 23 are divided into two groups, and each group of the first driving circuits 23 is respectively disposed on two opposite sides of the display area 1, for example, on the left and right sides of the display area 1. However, in the process of manufacturing the first driving circuits 23, the first driving circuits 23 on the left and right sides of the display area 1 are usually manufactured in different processes due to the larger spacing between the first driving circuits 23 on the left and right sides of the display area 1, but different processes may cause differences in electron mobility or threshold voltage of the thin film transistors in the two groups of first driving circuits 23, and further cause inconsistent charging state between pixel areas of adjacent rows in the display panel 100, for example, the first row of pixel areas 13 is driven by the first driving circuit 23 on the left side of the display area 1, the second row of pixel areas 13 is driven by the first driving circuit 23 on the right side of the display area 1, if the falling edge time of the thin film transistors in the first driving circuit 23 on the right side is longer, the second row of pixel areas 13 may be charged to the next level data voltage by mistake, and the brightness of the second row of pixel areas 13 is reduced, thereby causing bright and dark lines to be generated on the display panel 100, and further affecting the display function of the display panel 100.

In the display panel 100 provided in this embodiment, the first driving circuit 23 for controlling the on/off of the first transistor T1 is disposed on one side of the display area 1, so that the thin film transistors in the first driving circuit 23 can be manufactured in the same manufacturing process, and the second driving circuit 24 for controlling the on/off of the second transistor T2 is disposed on the other side of the display area 1, so that the thin film transistors in the second driving circuit 24 can be manufactured in the same manufacturing process, so as to improve the uniformity of the thin film transistors in the first driving circuit 23 and the uniformity of the thin film transistors in the second driving circuit 24, so that the first transistor T1 and the second transistor T2 in each row of pixel areas 13 can be turned on/off in a correct time period, and further, so that the data voltage written into each row of pixel areas 13 is accurate, and the uniformity of luminance display of the display panel 100 is improved; moreover, the first driving circuit 23 and the second driving circuit 24 respectively occupy the two opposite sides of the display area 1, so as to improve the symmetry of the display panel 100, avoid the problem that the first driving circuit 23 and the second driving circuit 24 are arranged on the same side of the display area 1, which causes the width of the peripheral area 2 to be too large, and promote the narrow frame design of the display panel 100.

In one possible implementation, referring to fig. 1, the first driving circuit 23 includes a plurality of first driving sub-circuits 231 and second driving sub-circuits 232. The first driving sub-circuit 231 is used for generating a first signal, and the first signal is used for controlling the on/off of the first transistor T1 in the pixel area 13 of the odd-numbered rows. The second driving sub-circuit 232 is configured to generate a second signal, and the second signal is used to control the on/off of the first transistor T1 in the pixel area 13 in the even-numbered row. It is understood that the first control signal includes a first signal and a second signal.

Specifically, referring to fig. 1 and fig. 2, each first transistor T1 in the pixel region 13 in each odd-numbered row is electrically connected to the first driving sub-circuit 231 through one row of the scan lines 11, and the scan lines 11 in the odd-numbered rows are used for transmitting the first signal to control the on/off of the first transistor T1 in the pixel region 13 in the odd-numbered rows. Each first transistor T1 in each even row of the pixel area 13 is electrically connected to the second driving sub-circuit 232 through a row of the scan lines 11, and the scan lines 11 in the even rows are used for transmitting the second signal to control the on/off of the first transistor T1 in the even row of the pixel area 13.

By driving the first transistor T1 and the second transistor T2 in the odd-numbered row of the display area 1 by the first driving sub-circuit 231 and the second driving sub-circuit 232 which are independent of each other, respectively, the brightness of the display area 1 driven by the staggered driving method is realized, and the display efficiency of the display area 1 of the display panel 100 is improved.

In other embodiments, the first driving sub-circuit 231 and the second driving sub-circuit 232 may be configured to drive a plurality of rows of consecutive first transistors T1, for example, the first driving sub-circuit 231 is configured to drive the first transistors T1 of the 1 st, 2 nd, 5 th, 6 th, 9 th, 10 th, … to be turned on and off, and the second driving sub-circuit 232 is configured to drive the first transistors T1 of the 3 rd, 4 th, 7 th, 8 th, 11 th, 12 th, … to be turned on and off.

Referring to fig. 1, for convenience of description, the length direction of the display panel 100 is determined as the Y-axis direction, and the width direction of the display panel 100 is determined as the X-axis direction.

Specifically, referring to fig. 1, the plurality of second driving sub-circuits 232 are arranged in a row along the Y-axis direction, and the plurality of first driving sub-circuits 231 are arranged in another row along the Y-axis direction. The plurality of second driving sub-circuits 232 are located between the plurality of first driving sub-circuits 231 and the display area 1. That is, the first driving sub-circuit 231 and the second driving sub-circuit 232 are disposed in two rows in the Y-axis direction. Further, the first driving sub-circuit 231 and the second driving sub-circuit 232 are arranged in a staggered manner in the X-axis direction, so that the routing of the first driving sub-circuit 231 can pass through the second driving sub-circuit 232, and the layout of the routing is more reasonable.

By arranging the first driving sub-circuit 231 and the second driving sub-circuit 232 in two rows in the Y-axis direction, the problem of the limited arrangement space of the first driving sub-circuit 231 and the second driving sub-circuit 232 in the Y-axis direction is effectively solved.

In other embodiments, the first and second driving

sub-circuits

231 and 232 are divided into a plurality of columns, such as three columns, four columns, and the like, which are greater than two, in the Y-axis direction.

In one possible implementation, referring to fig. 1 and fig. 3, the first driving sub-circuit 231 includes a plurality of cascaded first driving units 233. The plurality of first driving units 233 are G1, G3 … …, G2n-3, G2n-1, respectively. The first driving unit 233 is electrically connected to the first transistor T1 in at least one row of the odd-numbered pixel regions 13. The first driving unit 233 is configured to drive the first transistor T1 electrically connected to the first driving unit 233 to be turned on or off.

Specifically, referring to fig. 1 and fig. 3, the first driving sub-circuit 231 includes n first driving units 233, which are cascaded with each other, where n is a positive integer. The first driving unit 233 of each stage is configured to control on and off of the first transistor T1 (hereinafter, referred to as the first transistor T1 of the odd-numbered row) in the pixel region 13 of the odd-numbered row. For example, the first driving unit G1 of the first stage is used to drive the on/off of the first transistor T1 of the first row, the first driving unit G3 of the second stage is used to drive the on/off of the first transistor T1 of the third row, and the first driving unit G2n-1 of the nth stage is used to drive the on/off of the first transistor T1 of the (2n-1) th row. The n first driving units 233 are cascaded with each other, that is, the first driving unit G2n-3 of the (n-1) th stage outputs a scan signal according to the output terminal of the first driving unit G2n-5 of the (n-2) th stage and a scan signal output from the output terminal of the first driving unit G2n-1 of the n-th stage. In other embodiments, the first driving unit 233 of each stage may control the turn-on and turn-off of the first transistors T1 of a plurality of odd rows.

Further, referring to fig. 3, the first driving sub-circuit 231 further includes a dummy first driving unit G01 and a dummy first driving unit G03. The dummy first driving unit G01 is disposed at a previous stage of the first driving unit G1 of the first stage, so that the first driving unit G1 of the first stage can receive the trigger signal sent by the dummy first driving unit G01 and can generate the reset signal to the dummy first driving unit G01. The dummy first driving unit G03 is disposed at a stage next to the nth stage first driving unit G2n-1, so that the nth stage first driving unit G2n-1 can transmit a trigger signal to the dummy first driving unit G03 and can receive a reset signal transmitted by the dummy first driving unit G03.

In this embodiment, referring to fig. 3, the first driving unit 233 is used for generating a first scan signal. The first scan signal is used to control on/off of the first transistor T1 electrically connected to the first driving unit 233 of the current stage. It is understood that the first signal includes the first scan signal generated by the first driving unit 233 of each stage.

Specifically, referring to fig. 3, the nth stage first driving unit G2n-1 is electrically connected to the 2n-1 st transistor T1 through the 2n-1 st scan line 11, the nth stage first driving unit G2n-1 generates a first scan signal s1, and the first scan signal s1 is transmitted to each first transistor T1 of the 2n-1 st row through the 2n-1 st scan line 11, so that the first scan signal s1 controls on/off of each first transistor T1 of the 2n-1 st row.

Specifically, referring to fig. 2 and fig. 3, each of the first transistors T1 in the 2N-1 th column is illustrated as an N-type tft. The first scan signal s1 may be high or low. When the first scan signal s1 is at a high level, the first scan signal s1 controls each of the first transistors T1 in the 2n-1 th row to be turned on, that is, the first transistor T1 controls the first terminal p11 of the first transistor T1 and the second terminal p12 of the first transistor T1 to be electrically connected under the condition that the gate g11 loads the first scan signal s1, so that the data line 12 writes the data voltage Vdata into the second terminal p12 of the first transistor T1 through the first terminal p11 of the first transistor T1. When the first scan signal s1 is at a low level, the first scan signal s1 controls each of the first transistors T1 of the 2n-1 th row to be turned off, i.e., the gate g11 of the first transistor T1 controls the first terminal p11 of the first transistor T1 and the second terminal p12 of the first transistor T1 to be turned off under the control of the first scan signal s1, so that the data line 12 does not write the data voltage Vdata into the second terminal p12 of the first transistor T1 through the first terminal p11 of the first transistor T1.

It is understood that the first scan signal s1 controls the turn-on or turn-off of each first transistor T1 of the 2n-1 th row to perform one scan of the first transistor T1 of the 2n-1 th row by the first driving unit 233.

It is understood that the first driving unit 233 further includes a first clock signal terminal. The first clock signal end is used for receiving a first clock signal or a second clock signal, and pulses of the first clock signal and the second clock signal are sequentially output in turn and are not overlapped with each other. The first driving unit 233 generates a first scan signal at a high level according to the first clock signal. The first driving unit 233 generates a first scan signal at a low level according to the second clock signal.

The first driving unit 233 is further configured to generate a first trigger signal. The first trigger signal is used for triggering the first driving unit 233 at the next stage to operate after the first scanning signal generated by the first driving unit 233 at the current stage is scanned.

Specifically, referring to fig. 3, the first driving unit G2n-3 at the n-1 th stage generates the first trigger signal s2 and transmits the first trigger signal s2 to the first driving unit G2n-1 at the n-th stage to trigger the first driving unit G2n-1 at the n-th stage to start scanning the transistors in the pixel area 13 at the 2n-1 th row. The transistors in the pixel region 13 include, but are not limited to, the first transistor T1. It is understood that the first trigger signal may be high or low. When the first driving unit G2n-3 of the nth-1 stage generates the first trigger signal s2 to be a low level, the first driving unit G2n-1 of the nth stage stops scanning the transistors in the pixel region 13 of the 2n-1 th row under the control of the first trigger signal s 2. When the first driving unit G2n-3 of the nth-1 stage generates the first trigger signal s2 to be high level, the first driving unit G2n-1 of the nth stage starts scanning the transistors in the pixel region 13 of the 2n-1 th row under the control of the first trigger signal s 2.

The first driving unit 233 is further configured to generate a first reset signal. The first reset signal is used to reset the potential of the first driving unit 233 of the previous stage after the first scan signal generated by the first driving unit 233 of the previous stage is scanned.

Specifically, referring to fig. 3, after the n-1 stage first driving unit G2n-3 scans the transistors in the pixel region 13 of the 2n-3 th row, at this time, the n-1 stage first driving unit G2n-3 generates the first trigger signal s2 to the n-stage first driving unit G2n-1, the first trigger signal s2 is transmitted to the n-stage first driving unit G2n-1, the n-stage first driving unit G2n-1 generates the low-level first reset signal s3 under the control of the first trigger signal s2, and transmits the first reset signal s3 to the n-1 stage first driving unit G2n-3, so that the n-1 stage first driving unit G2n-3 returns to the low level, and the n-1 stage first driving unit G2n-3 stops scanning the transistors in the pixel region 13 of the 2n-3 th row, the bright lines are prevented from appearing in the dark areas of the display area 1, and the display quality of the display area 1 is improved.

In one possible implementation, referring to fig. 2, the pixel region 13 is further provided with a third transistor T3. The third transistor T3 is used to cooperate with the first transistor T1 and the second transistor T2 to control the operation of the light emitting unit 130. The first driving unit 233 is configured to generate a second scan signal, which is used to control the on/off of the third transistor T3 in a row of the pixel area 13 adjacent to the pixel area 13 of the current row after the first scan signal scans the first transistor T1 in the pixel area 13 of the current row. The third transistor T3 has a gate g31, a first terminal P31, and a second terminal P32. The gate G31 of the third transistor T3 is electrically connected to the first driving unit G2n-1 through the scan line 11. The first terminal p31 is used for receiving an initial voltage Vint.

Specifically, referring to fig. 2, the pixel region 13 further includes a fourth transistor T4. The fourth transistor T4 has a gate g41, a first terminal P41 and a second terminal P42. The gate g41 of the fourth transistor T4 is connected to the second terminal p12 of the first transistor T1, so that the first transistor T1 controls the gate potential of the fourth transistor T4. The first terminal P41 of the fourth transistor T4 is connected to the second terminal P22 of the second transistor T2, so that the second transistor T2 controls the potential of the first terminal P41 of the fourth transistor T4. The second terminal P42 of the fourth transistor T4 is connected to the second terminal P32 of the third transistor T3, so that the third transistor T3 controls the potential of the second terminal P42 of the fourth transistor T4. When the second transistor T2 and the fourth transistor T4 are turned on, the light emitting unit 130 receives the first voltage signal VDD, and the light emitting unit 130 emits light under the driving of the first voltage signal VDD. In the present embodiment, the first transistor T1, the third transistor T3, and the fourth transistor T4 are N-type transistors, and the second transistor T2 is a P-type transistor, for example, but it goes without saying that in other embodiments, the first transistor T1, the third transistor T3, and the fourth transistor T4 are P-type transistors, and the second transistor T2 is an N-type transistor.

Specifically, referring to fig. 2 and 3, the first driving unit G2n-1 of the nth stage is electrically connected to the third transistor T3 in the pixel area 13 of the 2n-1 th row through the scan line 11 of the 2n-1 th row. After the first scan signal generated by the first driving unit G2n-1 of the nth stage completes scanning the first transistors T1 in the pixel region 13 of the 2n-1 th row, the first driving unit G2n-1 of the nth stage generates the second scan signal s4 to scan the third transistors T3 in the pixel region 13 of the 2n th row so that the gate G31 of each third transistor T3 in the pixel region 13 of the 2n th row is at a high level, and then the first terminal P31 and the second terminal P32 of each third transistor T3 in the pixel region 13 of the 2n th row are turned on to write the initial voltage Vint from the first terminal P31 of each third transistor T3 in the pixel region 13 of the 2n th row to the second terminal P32 of the third transistor T3, and then to the potential of the first terminal P41 of the fourth transistor T4. It can be understood that the first driving unit G2n-1 of the nth stage is electrically connected to the scan line 11 of the 2 nth row and transfers the second scan signal s4 to each third transistor T3 in the pixel region 13 of the 2 nth row through the scan line 11 of the 2 nth row.

In one possible implementation, referring to fig. 1, the first driving sub-circuit 231 includes a plurality of cascaded second driving units 234. The second driving unit 234 is electrically connected to the first transistor T1 in at least one row of even-numbered pixel regions 13. The second driving unit 234 is used for driving the on/off of a first transistor T1 electrically connected with the second driving unit 234.

Specifically, referring to fig. 1 and fig. 3, the first driving sub-circuit 231 includes n second driving units 234 cascaded with each other, where n is a positive integer. The plurality of second driving units 234 are G2, G4 … …, G2n-2, G2n, respectively. The second driving unit 234 of each stage is used to control the on/off of the first transistor T1 of one even row. For example, the second driving unit G2 of the first stage is used to drive the switching of the first transistor T1 of the second row, the second driving unit G4 of the second stage is used to drive the switching of the first transistor T1 of the fourth row, and the second driving unit G2n of the nth stage is used to drive the switching of the first transistor T1 of the 2 nth row. The n second driving units 234 are cascaded with each other, that is, the second driving unit 234 of the n-1 th stage outputs a scan signal according to the output terminal of the second driving unit 234 of the n-2 th stage and the scan signal output from the output terminal of the second driving unit 234 of the n-th stage. In other embodiments, the second driving unit 234 of each stage may control the switching of the first transistors T1 of a plurality of even rows.

It can be understood that the second driving unit 234 and the first driving unit 233 have the same structure, and the electrical connection and control manner between the second driving unit 234 and the first transistor T1 in the even-numbered row pixel region 13 are the same as the electrical connection and control manner between the first driving unit 233 and the first transistor T1 in the odd-numbered row pixel region 13, and therefore, the description thereof is omitted.

For example, referring to fig. 3, after the first scan signal generated by the first driving unit G1 of the 1 st stage completes the switching of the first transistor T1 of the 1 st column, the first driving unit G1 of the 1 st stage generates the second scan signal, and the second scan signal can control the switching of the third transistor T3 of the 2 nd column. After the gate of the third transistor T3 of the 2 nd row receives the second scan signal, the second driving unit G2 of the 1 st stage generates a scan signal, and the scan signal is transmitted to the gate of the first transistor T1 of the 2 nd row through the scan line 11 of the 2 nd row to control the on/off of the first transistor T1 of the 2 nd row, so as to scan the transistors in the pixel region 13 of the 2 nd row. After the scanning of the transistors in the pixel region 13 of the 2 nd row is completed, i.e., after one scan period, the first driving unit G1 of the 1 st stage generates a first trigger signal for triggering the first driving unit G3 of the 2 nd stage to generate a first scan signal to scan the transistors of the pixel region 13 of the third row. After the transistor scan in the pixel region 13 of the third row is completed, the first driving unit G3 of the 2 nd stage transfers a scan signal to the third transistor T3 of the fourth row through the scan line 11 of the fourth row to turn on the third transistor T3 of the fourth row; the second driving unit G2 of the 1 st stage generates a trigger signal for triggering the second driving unit G4 of the 2 nd stage to generate a scan signal for scanning the first transistors T1 of the pixel regions 13 of the 4 th row, and so on, to realize the row-by-row scanning of the transistors of the pixel regions 13 of the 2n rows in the display region 1.

Further, referring to fig. 3, the first driving sub-circuit 232 further includes a dummy second driving unit G02 and a dummy second driving unit G04. The dummy second driving unit G02 is disposed at a previous stage of the first stage second driving unit G2, so that the first stage second driving unit G2 can receive the trigger signal sent by the dummy second driving unit G02 and can generate the reset signal to the dummy second driving unit G02. The dummy second driving unit G04 is disposed at a stage next to the nth stage second driving unit G2n, so that the nth stage second driving unit G2n can transmit a trigger signal to the dummy second driving unit G04 and can receive a reset signal transmitted by the dummy second driving unit G04.

In one possible implementation, referring to fig. 1, the first wiring region 21 is further provided with a signal line 24. The first driving sub-circuit 231 and the second driving sub-circuit 232 are electrically connected to the signal line 24. The signal line 24 is used to generate a first level signal and a second level signal. The first level signal may be a high level signal and the second level signal is a low level signal, or the first level signal is a low level signal and the second level signal is a high level signal. The first level signal is used to drive the first driving sub-circuit 231 to generate the first control signal. The second level signal is used to drive the second driving sub-circuit 232 to generate the second control signal. The signal line 25 includes a dc signal line 251 and an ac signal line 252 having a low frequency.

By placing the first driving sub-circuit 231 and the second driving sub-circuit 232 on the same side, the first driving circuit 23 disposed on the same side can share the signal line 25 without disposing the signal line 25 on both opposite sides of the display region 1, so that the number of the signal lines 25 can be halved, the width of the peripheral region 2 is greatly reduced, and the narrow frame design of the display panel 100 is further promoted.

In one possible implementation, referring to fig. 1, the second driving circuit 24 includes a third driving sub-circuit 241 and a fourth driving sub-circuit 242. The third driving sub-circuit 241 is used for generating a third signal. The third signal is used to control the switching of the second transistor T2 in the odd row pixel area 13. The fourth driver sub-circuit 242 is configured to generate a fourth signal, and the fourth signal is used to control on/off of the second transistor T2 in the pixel region 13 in the even-numbered row. It is understood that the second control signal includes a third signal and a fourth signal.

Similarly to the first driving circuit 23, the second driving circuit 24 is divided into a third driving sub-circuit 241 for controlling the on/off of the second transistor T2 in the odd-numbered row pixel area 13 and a fourth driving sub-circuit 242 for controlling the on/off of the second transistor T2 in the even-numbered row pixel area 13, so as to drive the transistors of the display area 1 in an interlaced driving manner, thereby improving the display efficiency of the display area 1.

Specifically, referring to fig. 1, the plurality of third driving sub-circuits 241 are arranged in a row along the Y-axis direction, and the plurality of fourth driving sub-circuits 242 are arranged in another row along the Y-axis direction. The plurality of fourth driving sub-circuits 242 are located between the plurality of third driving sub-circuits 241 and the display area 1. That is, the third driver sub-circuit 241 and the fourth driver sub-circuit 242 are disposed in two rows in the Y-axis direction. Further, the third driving sub-circuit 241 and the fourth driving sub-circuit 242 are arranged in an staggered manner in the X-axis direction, so that the routing of the third driving sub-circuit 241 can pass through the fourth driving sub-circuit 242, and the layout of the routing is more reasonable.

By arranging the third drive sub-circuit 241 and the fourth drive sub-circuit 242 in two rows in the Y-axis direction, the problem of the limited arrangement space of the third drive sub-circuit 241 and the fourth drive sub-circuit 242 in the Y-axis direction is effectively solved.

In other embodiments, the third driver sub-circuit 241 and the fourth driver sub-circuit 242 are divided into more than two columns, such as three columns, four columns, and the like, in the Y-axis direction.

In one possible implementation, referring to fig. 4, the third driving sub-circuit 241 includes a plurality of cascaded third driving units 243. The third driving unit 243 includes E1, E3 … … E2n-3, E2 n-1. The third driving unit 243 electrically connects the second transistors T2 in at least one row of the odd-numbered pixel regions 13. The third driving unit 243 is used for driving the second transistor T2 electrically connected to the third driving unit 243 to be turned on and off. The third driving units 243 correspond to the first driving units 233 one by one, and the third driving units 243 and the first driving units 233 cooperate to control the light emitting units 130 in the odd-numbered rows of the pixel regions 13 to emit light. Specifically, the third driving sub-circuit 241 includes n third driving units 243 cascaded with each other, where n is a positive integer. The third driving unit 243 of each stage is used to control the on/off of the second transistor T2 of one odd row. In other embodiments, the third driving unit 243 of each stage is used to control the on/off of the second transistor T2 of the odd rows of the plurality of rows.

Further, the third driving unit 243 is configured to generate a third scan signal, where the third scan signal controls on/off of the second transistor T2 electrically connected to the third driving unit 243 of the current stage.

In one possible embodiment, referring to fig. 3 and 4, the third driving unit 243 is linked with the first driving unit 233. Specifically, the third driving unit 243 of the nth stage is electrically connected to the first driving unit G2n-1 of the nth stage. After the first scan signal generated by the first driving unit G2n-1 of the nth stage scans the first transistor T1 of the pixel region 13 of the 2n-1 th row, the first driving unit G2n-1 of the nth stage triggers the third driving sub-circuit 241 of the nth stage to generate the third scan signal for scanning the second transistor T2 of the pixel region 13 of the 2n-1 th row. The third driving units 243 and the first driving units 233 are in one-to-one correspondence, and the third driving units 243 and the first driving units 233 cooperate to control the on/off of the first transistor T1 and the third transistor T3, so as to control the light emitting units 130 in the odd-numbered rows of the pixel regions 13 to emit light.

Further, referring to fig. 3 and 4, the first driving unit 233 is further configured to generate a second trigger signal and a second reset signal. The second trigger signal is used to trigger the third driving unit 243 of the current stage to generate the third scan signal. The second reset signal is used to reset the potential of the third driving unit 243 at the previous stage after the third scanning signal generated by the third driving unit 243 at the previous stage is scanned.

For example, referring to fig. 3 and 4, after the first scan signal s1 generated by the first driving unit G2n-1 at the nth stage scans the first transistor T1 of the pixel region 13 at the 2n-1 th row, the first driving unit G2n-1 at the nth stage generates the second trigger signal s5, and the second trigger signal s5 is used for triggering the third driving unit E2n-1 at the nth stage to generate the third scan signal s6, so that the third scan signal s6 controls the second transistor T2 at the 2n-1 th row to be turned on or off. The first driving unit G2n-1 of the nth stage also generates a second reset signal s7, and the second reset signal s7 is used to reset the potential of the third driving unit E2n-3 of the nth-1 stage, so that the third driving unit E2n-3 of the nth-1 stage stops controlling the on/off of the second transistor T2.

Further, referring to fig. 3 and 4, the scan line 11 is electrically connected to the first driving unit 233 and the third driving unit 243 corresponding to the first driving unit 233 at the current stage. The scan line 11 is further configured to transmit the second trigger signal to trigger the third driving unit 243 to operate.

For example, referring to fig. 3 and 4, the nth stage of the first driving unit G2n-1 is electrically connected to the nth stage of the third driving unit E2n-1 through the 2n-1 th row of the scan line 11, so as to transmit the second trigger signal s5 generated by the nth stage of the first driving unit G2n-1 to the nth stage of the third driving unit E2 n-1.

In this embodiment, the first driving unit 233 and the third driving unit 243 are respectively disposed at two opposite sides of the display area 1, the connection line between the first driving unit 233 and the second driving unit 234 needs to span the whole display area 1, and the first driving unit 233 and the third driving unit 243 at two opposite sides of the display area 1 are connected by the scanning line 11, so that the structural advantage that the scanning line 11 spans the whole display area 1 is utilized, the scanning line 11 is disposed between the first driving unit 233 and the third driving unit 243, and the connection line spanning the whole display area 1 does not need to be additionally disposed, thereby reducing the number of the connection lines, and avoiding the connection lines occupying more positions of the display area 1.

In one possible implementation manner, referring to fig. 3 and 4, the scan line 11 is further electrically connected to the first driving unit 233 and a third driving unit 243 corresponding to the first driving unit 233 at a previous stage. The scan line 11 is further configured to transmit the second reset signal to reset the potential of the third driving unit 243 corresponding to the first driving unit 233 at a previous stage.

For example, referring to FIG. 3 and FIG. 4, the first driving unit G2n-1 of the nth stage is electrically connected to the third driving unit E2n-3 of the nth-1 stage through the scan line 11 of the 2n-1 th row. After the scan of the third driving unit E2n-3 of the n-1 th stage for the second transistor T2 of the 2n-3 th row is completed, the second reset signal s7 generated by the first driving unit G2n-1 of the n-1 th stage is transmitted to the third driving unit E2n-3 of the n-1 th stage through the scan line 11 of the 2n-1 th row for resetting the potential of the third driving unit E2n-3 of the n-1 th stage, for example, the second reset signal s7 changes the voltage of the third driving unit E2n-3 of the n-1 th stage from a high voltage to a low level.

Further, referring to fig. 4, the second driving sub-circuit 233 further includes a virtual third driving unit E01 and a virtual third driving unit E03. Wherein, the virtual third driving unit E01 is disposed at a previous stage of the third driving unit E1 of the first stage, so that the virtual third driving unit E01 can receive the trigger signal transmitted by the virtual first driving unit G01 and the reset signal emitted by the first driving unit G1. The dummy third driving unit E03 is disposed at a stage next to the nth stage third driving unit E2n-1 to receive the trigger signal transmitted by the dummy first driving unit G03.

In one possible implementation, referring to fig. 1, fig. 3 and fig. 4, the fourth driver sub-circuit 242 includes a plurality of cascaded fourth driver units 244. The fourth driving unit 244 is electrically connected to the second transistor T2 in at least one row of even-numbered pixel regions 13. The fourth driving unit 244 is configured to turn on and off the second transistor T2 electrically connected to the fourth driving unit 244. It is understood that the fourth driving unit 244 has the same structure as the third driving unit 243.

Specifically, referring to fig. 1, fig. 3 and fig. 4, the fourth driver sub-circuit 242 includes n fourth driver units 244 cascaded with each other, where n is a positive integer. The fourth driving unit 244 of each stage is used to control the switching of the second transistor T2 of one even row. For example, the fourth driving unit E2 of the first stage is used to drive the second transistor T2 of the second row to be turned on and off, the fourth driving unit E4 of the second stage is used to drive the second transistor T2 of the fourth row to be turned on and off, and the fourth driving unit E2n of the nth stage is used to drive the second transistor T2 of the 2 nth row to be turned on and off. The n fourth driving units 244 are cascaded with each other, that is, the n-1 th-stage fourth driving unit E2n-2 is based on the scan signal output from the output terminal of the n-2 th-stage fourth driving unit E2n-4 and the scan signal output from the output terminal of the n-th-stage fourth driving unit E2 n. In other embodiments, the fourth driving unit 244 of each stage may control the switching of the second transistors T2 of a plurality of even rows.

It can be understood that the fourth driving unit 244 has the same structure as the third driving unit 243, and the electrical connection between the fourth driving unit 244 and the second driving unit 234 and the electrical connection between the third driving unit 243 and the first driving unit 233 are not described herein again. The electrical connection and control of the fourth driving unit 244 and the second transistor T2 in the pixel region 13 in the even-numbered row are the same as the electrical connection and control of the third driving unit 243 and the second transistor T2 in the pixel region 13 in the odd-numbered row, and therefore, the description thereof is omitted.

Further, referring to fig. 3, the second driving sub-circuit 234 further includes a dummy fourth driving unit E02 and a dummy fourth driving unit E04. The virtual fourth driving unit E02 is disposed at a stage above the fourth driving unit E2 of the first stage to receive the trigger signal sent by the virtual fourth driving unit E01 and the reset signal emitted by the fourth driving unit E1. The virtual fourth driving unit E04 is disposed at the next stage of the nth stage fourth driving unit E2n to receive the trigger signal sent by the virtual fourth driving unit E03.

In one possible implementation manner, referring to fig. 3 and fig. 5, the pixel region 13 is further provided with a first capacitor C1 and a second capacitor C2. The first end p11 of the first transistor T1 is electrically connected to the gate g41 of the fourth transistor T4, the gate g11 of the first transistor T1 is electrically connected to the first driving circuit 23, the second end p12 of the first transistor T1 is electrically connected to the data line 12, and the data line 12 is used for transmitting a data voltage Vdata/reference voltage Vref. The first transistor T1 is used for receiving a data voltage Vdata/reference voltage Vref according to the first control signal. Specifically, the gate g11 of the first transistor T1 turns on the first and second terminals p11 and p12 of the first transistor T1 under the first control signal, so that the data voltage Vdata/reference voltage Vref may be transmitted to the gate g41 of the fourth transistor T4.

Referring to fig. 3 and 5, the first terminal p21 of the second transistor T2 is electrically connected to the first terminal p41 of the fourth transistor T4, the gate g21 of the second transistor T2 is electrically connected to the second driving circuit 24, and the second terminal p21 of the second transistor T2 is used for receiving the first voltage signal VDD. The second transistor T2 is used for receiving a first voltage signal VDD according to the second control signal. Specifically, the gate g21 of the second transistor T2 turns on the first terminal p21 and the second terminal p22 of the second transistor T2 under the second control signal, so that the first voltage signal VDD may be transmitted to the first terminal p41 of the fourth transistor T4.

Referring to fig. 3 and 5, the first end p31 of the third transistor T3 is electrically connected to the second end p42 of the fourth transistor T4, the gate g31 of the third transistor T3 is electrically connected to the first driving circuit 23, and the second end p32 of the third transistor T3 is used for receiving an initial voltage Vint. The third transistor T3 is used for receiving an initial voltage Vint according to a third control signal generated by the first driving circuit 23. Specifically, the gate g31 of the third transistor T3 turns on the first terminal p31 and the second terminal p32 of the third transistor T3 under the third control signal, so that the initial voltage Vint may be transmitted to the second terminal p42 of the fourth transistor T4.

Referring to fig. 3 and 5, the second terminal p42 of the fourth transistor T4 is electrically connected to one terminal of the light emitting unit 130, and the other terminal of the light emitting unit 130 is electrically connected to the second voltage signal VSS. The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 cooperate to control the light emitting unit 130 to emit light. Specifically, the first transistor T1, the second transistor T2, and the third transistor T3 may control the potentials of the gate terminal g41, the first terminal p41, and the second terminal p42 of the fourth transistor T4, respectively, so as to control the fourth transistor T4 to be turned on or off. When the fourth transistor T4 and the second transistor T2 are turned on, opposite ends of the light emitting unit 130 are connected to the first voltage signal VDD and the second voltage signal VSS, respectively. The second voltage signal VSS may be a low voltage, and the first voltage signal VDD may be a high voltage, so as to enable the light emitting unit 130 to emit light.

Referring to fig. 3, the first capacitor C1 is electrically connected to the first terminal p11 of the first transistor T1 and the second terminal p42 of the fourth transistor T4. The second capacitor C2 is electrically connected to the second terminal p22 of the second transistor T2 and the first terminal p31 of the third transistor T3.

The time period for driving the light emitting unit 130 to emit light includes a reset phase t1, a storage phase t2 and a light emitting phase t3 which are sequentially continuous, and the reset phase t1, the storage phase t2 and the light emitting phase t3 are described in detail below.

In the reset phase T1, the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned off, and the third transistor T3 is turned on, so that the voltages at the first end p21 of the second transistor T2 and the second end p42 of the fourth transistor T4 charge the second capacitor C2. And the potential of the second terminal of the fourth transistor T4 is reset.

In the storage period T2, the first transistor T1 and the third transistor T3 are turned on, and the second transistor T2 is turned off to charge the gate of the fourth transistor T4, so that the data voltage Vdata is written into the gate g41 of the fourth transistor T4; the voltage difference between the gate g41 and the second terminal p42 of the fourth transistor T4 is stored in the first capacitor C1. In this stage, the second transistor T2 is turned off while the data voltage Vdata is written to achieve the effect of internally compensating the threshold voltage Vth of the fourth transistor T4, so as to prevent the threshold voltage Vth of the fourth transistor T4 from drifting and improve the brightness uniformity of the display panel 100.

In the light emitting period T3, the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on, the third transistor T3 is turned off to charge the first terminal p41 of the fourth transistor T4, and when the voltage of the gate g41 of the fourth transistor T4 is greater than a predetermined threshold, the fourth transistor T4 is turned on to apply the first voltage signal VDD to one terminal of the light emitting unit 130, so that the light emitting unit 130 emits light. This stage realizes the light emitting unit 130 to emit light.

In the present embodiment, the first transistor T1, the third transistor T3 are N-type transistors, the second transistor T2 is a P-type transistor, and the fourth transistor T4 is an N-type transistor, so as to describe a pixel driving method for driving the light emitting unit 130 to emit light.

Specifically, in the reset phase T1, the driving unit Gn-1 in the first driving circuit 23 provides a high potential to the gate g31 of the third transistor T3 to turn on the third transistor T3, and the initial voltage Vint is applied to the second end p42 of the fourth transistor T4; the driving unit Gn in the first driving circuit 23 supplies a low potential to the gate g11 of the first transistor T1 to turn off the first transistor T1; the driving unit En in the second driving circuit 24 provides a high potential to the gate g21 of the second transistor T2 to turn off the second transistor T2, and stores the voltages at the first terminal p21 of the second transistor T2 and the second terminal p42 of the fourth transistor T4 to charge the second capacitor C2. The reset phase is to reset the potential of the second terminal p42 of the fourth transistor T4.

Specifically, in the storage period T2, the driving unit Gn-1 in the first driving circuit 23 supplies a high potential to the gate g31 of the third transistor T3 to turn on the third transistor T3; the driving unit Gn in the first driving circuit 23 supplies a high potential to the gate g11 of the first transistor T1 to turn on the first transistor T1, and the driving unit En in the second driving circuit 24 supplies a high potential to the gate g21 of the second transistor T2 to turn off the second transistor T2.

Specifically, in the light emitting period T3, the driving unit Gn-1 in the first driving circuit 23 supplies a low potential to the gate g31 of the third transistor T3 to turn off the third transistor T3; the driving unit Gn in the first driving circuit 23 supplies a high potential to the gate g11 of the first transistor T1 to turn on the first transistor T1; the driving unit En in the second driving circuit 24 provides a low potential to the gate g21 of the second transistor T2 to turn on the second transistor T2 to charge the first terminal g41 of the fourth transistor T4, and when the voltage of the gate g41 of the fourth transistor T4 is greater than a predetermined threshold, the fourth transistor T4 is turned on to apply the first voltage signal VDD to one terminal of the light emitting unit 130, so that the light emitting unit 130 emits light. This stage realizes the light emitting unit 130 to emit light.

Of course, in other embodiments, other pixel circuits for driving the light emitting unit 130 to emit light and other pixel driving methods for driving the light emitting unit 130 to emit light may be provided in the pixel region 13.

The present application further provides a display device 200, wherein the display device 200 comprises the display panel 100. The display device 200 may be a mobile phone, a desktop computer, a notebook computer, a television, a wearable device, an intelligent appliance, or the like.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the methods and their core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

The utility model provides a display panel, its characterized in that, display panel includes the display area and locates the first wiring district and the second wiring district of the relative both sides of display area, the display area is including being array distribution's pixel district, first wiring district is equipped with first drive circuit, second wiring district is equipped with second drive circuit, first drive circuit is used for producing first control signal, second drive circuit is used for producing second control signal, first drive circuit reaches second drive circuit cooperatees in order to control the luminescence unit work.
The display panel according to claim 1, wherein the pixel region is provided with a first transistor, a second transistor, and a light emitting unit, wherein the first control signal is used for controlling on/off of the first transistor, the second control signal is used for controlling on/off of the second transistor, and the first transistor and the second transistor cooperate with each other to control operation of the light emitting unit.
The display panel according to claim 2, wherein the first driving circuit comprises a plurality of first driving sub-circuits and a plurality of second driving sub-circuits, the first driving sub-circuits are used for generating a first signal, the first signal is used for controlling the on/off of the first transistor in the pixel area of the odd rows, the second driving sub-circuits are used for generating a second signal, and the second signal is used for controlling the on/off of the first transistor in the pixel area of the even rows.
The display panel according to claim 3, wherein the first driving sub-circuit comprises a plurality of cascaded first driving units, the first driving units are electrically connected with the first transistors in the pixel regions in at least one row with odd number of rows, and the first driving units are used for driving the first transistors electrically connected with the first driving units to be turned on and off.
The display panel according to claim 4, wherein the first driving unit is configured to generate a first scan signal, and the first scan signal is configured to control on/off of the first transistor electrically connected to the first driving unit of the current stage.
The display panel according to claim 5, wherein the first driving unit is further configured to generate a first trigger signal, and the first trigger signal is configured to trigger the first driving unit of a next stage to operate after the first scan signal generated by the first driving unit of the current stage is scanned.
The display panel according to claim 5, wherein the first driving unit is further configured to generate a first reset signal, and the first reset signal is configured to reset a potential of the first driving unit of a previous stage after the first scan signal generated by the first driving unit of the previous stage is scanned.
The display panel of claim 5, wherein the pixel area further includes a third transistor, the third transistor is used to cooperate with the first transistor and the second transistor to control the light emitting unit to operate, the first driving unit is used to generate a second scan signal, and the second scan signal is used to control the third transistor in a pixel area of a next row adjacent to the pixel area of the current row to be turned on and off after the first scan signal scans the first transistor in the pixel area of the current row.
The display panel according to any one of claims 3 to 8, wherein the first driving sub-circuit comprises a plurality of cascaded second driving units, the second driving units are electrically connected with the first transistors in the pixel regions of at least one row of even-numbered rows, and the second driving units are used for driving the first transistors electrically connected with the second driving units to be turned on and off.
The display panel according to any one of claims 3 to 8, wherein the first wiring region is further provided with a signal line, the first driving sub-circuit and the second driving sub-circuit are electrically connected to the signal line, the signal line is configured to generate a first level signal and a second level signal, the first level signal is configured to drive the first driving sub-circuit to generate the first control signal, and the second level signal is configured to drive the second driving sub-circuit to generate the second control signal.
The display panel according to any one of claims 4 to 8, wherein the second driving circuit comprises a third driving sub-circuit and a fourth driving sub-circuit, the third driving sub-circuit is configured to generate a third signal for controlling the switching of the second transistor in the pixel region of the odd-numbered rows, and the fourth driving sub-circuit is configured to generate a fourth signal for controlling the switching of the second transistor in the pixel region of the even-numbered rows.
The display panel according to claim 11, wherein the third driving sub-circuit comprises a plurality of cascaded third driving units, the third driving units are electrically connected to the second transistors in the pixel regions in at least one row with odd number of rows, the third driving units are used for driving the second transistors electrically connected to the third driving units to be turned on and off, the third driving units are in one-to-one correspondence with the first driving units, and the third driving units cooperate with the first driving units to control the light emitting units in the pixel regions in the odd number of rows to emit light.
The display panel according to claim 12, wherein the third driving unit is configured to generate a third scan signal, and the third scan signal controls on/off of a second transistor electrically connected to the third driving unit of the current stage.
The display panel according to claim 12, wherein the first driving unit is further configured to generate a second trigger signal and a second reset signal, the second trigger signal being configured to trigger the third driving unit of the current stage to generate the third scan signal; the second reset signal is used for resetting the potential of the third driving unit of the previous stage after the third scanning signal generated by the third driving unit of the previous stage is scanned.
The display panel according to claim 14, wherein the display area is further provided with a plurality of rows of scanning lines, the first transistor in each row of the pixel area is electrically connected to one row of the scanning lines, the scanning lines are electrically connected to the first driving unit and the third driving unit corresponding to the first driving unit in the current stage, the scanning lines are used for transmitting the first signal to control the on/off of the first transistor, and the scanning lines are further used for transmitting the second trigger signal to trigger the third driving unit to operate.
The display panel according to claim 15, wherein the scan electrically connects the first driving unit and a third driving unit corresponding to the first driving unit of the previous stage, and wherein the scan is further configured to transmit the second reset signal to reset a potential of the third driving unit corresponding to the first driving unit of the previous stage.
The display panel according to any one of claims 11 to 16, wherein the fourth driver sub-circuit comprises a plurality of cascaded fourth driving units, the fourth driving units are electrically connected to the second transistors in at least one row of even-numbered pixel regions, and the fourth driving units are configured to turn on and off the second transistors electrically connected to the fourth driving units.
The display panel according to any one of claims 1 to 8, wherein the pixel region further comprises a third transistor, a fourth transistor, a first capacitor and a second capacitor, the first transistor, the second transistor, the third transistor and the fourth transistor each have a gate, a first terminal and a second terminal, wherein the first terminal is a source and the second terminal is a drain, or the first terminal is a drain and the second terminal is a source,

a first end of the first transistor is electrically connected with a grid electrode of the fourth transistor, the grid electrode of the first transistor is electrically connected with the first driving circuit, and the first transistor is used for receiving a data voltage and a reference voltage according to the first control signal;

the first end of the second transistor is electrically connected with the first end of the fourth transistor, the grid electrode of the second transistor is electrically connected with the second driving circuit, and the second transistor is used for receiving a power supply voltage according to the second control signal;

a first end of the third transistor is electrically connected to a second end of the fourth transistor, a gate of the third transistor is electrically connected to the first driving circuit, and the third transistor is used for receiving an initial voltage according to a third control signal generated by the first driving circuit;

a second end of the fourth transistor is electrically connected to the light emitting unit, and the first transistor, the second transistor, the third transistor and the fourth transistor cooperate to control the light emitting unit to emit light;

the first capacitor is electrically connected with the first end of the first transistor and the second end of the fourth transistor; the second capacitor is electrically connected with the second end of the second transistor and the first end of the third transistor.
A display device comprising the display panel according to any one of claims 1 to 18.