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CN113345986A - Inverted Mini LED chip and manufacturing method thereof - Google Patents

Inverted Mini LED chip and manufacturing method thereof Download PDF

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Publication number
CN113345986A
CN113345986A CN202110250074.0A CN202110250074A CN113345986A CN 113345986 A CN113345986 A CN 113345986A CN 202110250074 A CN202110250074 A CN 202110250074A CN 113345986 A CN113345986 A CN 113345986A
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type semiconductor
electrode
layer
extension
quantum well
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王洪峰
黄文光
张振
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Focus Lightings Technology Suqian Co ltd
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Focus Lightings Technology Suqian Co ltd
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    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
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    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0137—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials the light-emitting regions comprising nitride materials
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    • H10H20/80—Constructional details
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    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • H10H20/812—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
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    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
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    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
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    • H10H20/831—Electrodes characterised by their shape
    • H10H20/8314—Electrodes characterised by their shape extending at least partially onto an outer side surface of the bodies
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    • H10H20/01—Manufacture or treatment
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    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
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    • H10H20/0364—Manufacture or treatment of packages of interconnections

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Abstract

本发明提供一种倒装Mini LED芯片及其制造方法，倒装Mini LED芯片依次包括衬底、N型半导体层、多量子阱层、和P型半导体层，P型半导体层包括相互间隔设置的第一P型半导体区和第二P型半导体区，多量子阱层包括分别位于第一P型半导体区和第二P型半导体区下方的第一多量子阱区和第二多量子阱区；第一P型半导体区上设有与其电性连接的第一扩展电极，第二P型半导体区上设有第二扩展电极，第二扩展电极延伸至N型半导体层，与其电性连接；第一扩展电极和第二扩展电极上分别设有与其电性连接的第一焊盘电极和第二焊盘电极，第一焊盘电极和第二焊盘电极上端面平齐，能有效避免倒装Mini LED芯片在封装使用时出现固晶不良的问题，保证足够的焊接强度。

Figure 202110250074

The invention provides a flip-chip Mini LED chip and a manufacturing method thereof. The flip-chip Mini LED chip sequentially includes a substrate, an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer. the first P-type semiconductor region and the second P-type semiconductor region, the multi-quantum well layer includes a first multi-quantum well region and a second multi-quantum well region located under the first P-type semiconductor region and the second P-type semiconductor region, respectively; The first P-type semiconductor region is provided with a first extension electrode that is electrically connected to it, the second P-type semiconductor region is provided with a second extension electrode, and the second extension electrode extends to the N-type semiconductor layer and is electrically connected to it; An extension electrode and a second extension electrode are respectively provided with a first pad electrode and a second pad electrode that are electrically connected to them, and the upper end surfaces of the first pad electrode and the second pad electrode are flush, which can effectively avoid flipping Mini LED chips have problems of poor die bonding when they are packaged and used to ensure sufficient soldering strength.

Figure 202110250074

Description

Inverted Mini LED chip and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor light-emitting devices, in particular to an inverted Mini LED chip and a manufacturing method thereof.
Background
As a novel energy-saving and environment-friendly solid-state illumination Light source, a Light Emitting Diode (LED) has the advantages of high energy efficiency, small size, Light weight, fast response speed, long service life and the like, so that the Light Emitting Diode (LED) is widely applied in many fields. The flip LED chip is widely applied due to good heat dissipation, wire bonding saving and good reliability. The Mini LED can provide better color gamut, can be subjected to dynamic region adjustment, realizes the HDR effect, can realize ultrathin application, and can also realize splicing to replace some OLEDs and traditional liquid crystals.
Then the current flip mini LED chip because the step structure of P type semiconductor region and N type semiconductor region, there is the difference in height in P/N electrode pad, and it is bad to appear solid brilliant when the encapsulation is used easily, causes the problem that encapsulation lamp pearl became invalid.
Disclosure of Invention
The invention aims to provide a flip Mini LED chip and a manufacturing method thereof.
The invention provides an inverted Mini LED chip which sequentially comprises a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer, wherein the P-type semiconductor layer comprises a first P-type semiconductor region and a second P-type semiconductor region which are arranged at intervals, and the multi-quantum well layer comprises a first multi-quantum well region and a second multi-quantum well region which are respectively positioned below the first P-type semiconductor region and the second P-type semiconductor region;
a first expansion electrode electrically connected with the first P-type semiconductor region is arranged on the first P-type semiconductor region, a second expansion electrode is arranged on the second P-type semiconductor region, and the second expansion electrode extends to the N-type semiconductor layer and is electrically connected with the N-type semiconductor layer;
the first extension electrode and the second extension electrode are respectively provided with a first pad electrode and a second pad electrode which are electrically connected with the first extension electrode and the second extension electrode, and the upper end faces of the first pad electrode and the second pad electrode are flush.
As a further improvement of the present invention, thicknesses of the first and second P-type semiconductor regions, the first and second multi-quantum well regions, the first and second extension electrodes, and the first and second pad electrodes are respectively uniform.
As a further improvement of the present invention, a passivation layer is further disposed on the surface and the side surface of the flip Mini LED chip, and the first pad electrode and the second pad electrode are disposed on the passivation layer and electrically connected to the first extension electrode and the second extension electrode through a through hole in the passivation layer, respectively.
As a further improvement of the invention, the passivation layer is SiO2Layer of or Si3N4Layer of or SiO2Layer and Ti3O5The layers are alternately stacked to form a Bragg reflection layer.
As a further improvement of the invention, the substrate is exposed at the side edge and the central position of the N-type semiconductor layer, and the passivation layer covers the part of the substrate exposed at the side edge of the N-type semiconductor layer.
As a further improvement of the invention, the first extension electrode and the second extension electrode are made of Cr, Ti, Al, Ni, Pt, Au or an alloy of two or more of the above metal materials, and the thickness of the first extension electrode and the second extension electrode is 1nm-3000 nm.
As a further improvement of the invention, the first pad electrode and the second pad electrode are made of Cr, Ti, Al, Ni, Pt, Au, Sn or an alloy of two or more of the above metal materials, and the thickness of the first pad electrode and the second pad electrode is 1nm-5000 nm.
The invention also provides a manufacturing method of the inverted Mini LED chip, which comprises the following steps:
providing a substrate, and growing an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer on the substrate in sequence;
etching the P-type semiconductor layer and the multi-quantum well layer to form a first multi-quantum well region and a second multi-quantum well region which are arranged at intervals, and a first P-type semiconductor region and a second P-type semiconductor region which are respectively positioned on the first multi-quantum well region and the second multi-quantum well region;
respectively arranging a first extension electrode and a second extension electrode on the first P-type semiconductor region and the second P-type semiconductor region, wherein the first extension electrode is electrically connected to the first P-type semiconductor region, and the second extension electrode extends to the N-type semiconductor layer and is electrically connected with the N-type semiconductor layer;
and forming a first pad electrode and a second pad electrode electrically connected to the first extension electrode and the second extension electrode respectively.
As a further improvement of the present invention, before "forming a first pad electrode and a second pad electrode electrically connected to the first extension electrode and the second extension electrode respectively" the method further comprises the steps of:
and forming a passivation layer on the surface and the side surface of the inverted Mini LED chip.
As a further improvement of the present invention, "forming a first pad electrode and a second pad electrode electrically connected thereto on the first extension electrode and the second extension electrode, respectively" specifically includes:
etching to form two through holes on the passivation layer, and respectively exposing the first extension electrode and the second extension electrode;
and evaporating a first pad electrode and a second pad electrode on the passivation layer, wherein the through hole is filled with the first pad electrode and the second pad electrode, and the first pad electrode and the second pad electrode are respectively and electrically connected with the first extension electrode and the second extension electrode.
As a further improvement of the present invention, after "etching the P-type semiconductor layer and the multiple quantum well layer", the method further comprises the steps of:
and etching the side edge and the central area of the N-type semiconductor layer until the substrate is exposed.
The invention has the beneficial effects that: according to the invention, the second P-type semiconductor region and the second multi-quantum well region which are used for supporting the structure are arranged on the N-type semiconductor layer, and the extension electrode which extends to the N-type semiconductor layer is arranged above the N-type semiconductor layer to electrically connect the second pad electrode with the N-type semiconductor layer, so that a structure with the same height is formed below the first pad electrode and the second pad electrode, the upper end surfaces of the first pad electrode and the second pad electrode are flush, the problem of poor die bonding of an inverted Mini LED chip during packaging can be effectively avoided, and the sufficient welding strength is ensured.
Drawings
Fig. 1 is a top view of a flip-chip Mini LED chip in an embodiment of the invention.
Fig. 2 is a side view of a flip-chip Mini LED chip in an embodiment of the invention.
Fig. 3 is a flow chart illustrating a method for manufacturing a flip Mini LED chip according to an embodiment of the present invention.
Fig. 4 to 7 are schematic diagrams of steps of a method for manufacturing a flip Mini LED chip according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be clearly and completely described below with reference to the detailed description of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
For convenience in explanation, the description herein uses terms indicating relative spatial positions, such as "upper," "lower," "rear," "front," and the like, to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
As shown in fig. 1 and 2, the present invention provides a flip-chip Mini LED chip, which includes a substrate 1, an N-type semiconductor layer 2, a multiple quantum well layer 3, and a P-type semiconductor layer 4 in this order.
The substrate 1 is made of sapphire, silicon carbide, silicon or a composite substrate of the materials, and can also be made of other common LED chip substrate materials.
The N-type semiconductor layer 2 and the P-type semiconductor layer 4 are any one of group III nitride based semiconductor layers commonly used in the art, and the present invention is not particularly limited thereto.
In some embodiments of the present invention, a nitride buffer layer is further disposed on the substrate 1 to reduce lattice mismatch between the substrate 1 and the semiconductor layer, so as to improve the growth quality of the epitaxial layer.
The P-type semiconductor layer 4 includes a first P-type semiconductor region 41 and a second P-type semiconductor region 42 disposed spaced apart from each other, and the multi-quantum well layer 3 includes a first multi-quantum well region 31 and a second multi-quantum well region 32 located below the first P-type semiconductor region 41 and the second P-type semiconductor region 42, respectively. Namely, the first P-type semiconductor region 41 overlaps the outer contour of the first multi-quantum well region 31 to form a first island-shaped structure a on the N-type semiconductor layer 2; the second P-type semiconductor region 42 overlaps the outer contour of the second multi-quantum well region 32 to form a second island-shaped structure b on the N-type semiconductor layer 2. The first island-shaped structures a and the second island-shaped structures b are arranged at intervals so as to avoid electrical connection at two positions after the electrodes are arranged.
Specifically, the first island-shaped structure a and the second island-shaped structure b are formed by etching after the multiple quantum well layer 3 and the P-type semiconductor layer 4 are formed, in the embodiment, the cross sections of the first island-shaped structure a and the second island-shaped structure b are both in a rounded rectangle shape, the cross section area of the first island-shaped structure a is larger, the first island-shaped structure a and the N-type semiconductor layer 2 together form a main function region of the LED chip for emitting light, the cross section area of the second island-shaped structure b is smaller than that of the first island-shaped structure a, the second island-shaped structure b is used as a support structure for arranging electrodes, and the cross section area of the second island-shaped structure b is similar to the area of an electrode plane arranged on the first island-shaped structure a, so that the space volume occupied by the second island-shaped structure b in the LED chip is reduced.
Since the first island-like structure a and the second island-like structure b are formed by etching the excess portions of the multiple quantum well layer 3 and the P-type semiconductor layer 4, the first island-like structure a and the second island-like structure b have the same thickness.
In some other embodiments of the present invention, the first island-shaped structure a and the second island-shaped structure b may also be adjusted in shape according to the LED chip size and the electrode shape.
The first P-type semiconductor region 41 is provided with a first extension electrode 51 electrically connected thereto, the second P-type semiconductor region is provided with a second extension electrode 52, the second extension electrode 52 extends to the N-type semiconductor layer 2 and is electrically connected thereto, and the second extension electrode 52 is disposed at an insulating interval from the first P-type semiconductor region 41 and the first multi-quantum well region 31.
The first extension electrode 51 covers substantially all of the upper surface of the first P-type semiconductor region 41, which increases the path for the current to laterally extend, acts to extend the current, and mitigates the current crowding effect. The second extension electrode 52 covers the surface of the second island-shaped structure b, extends to the N-type semiconductor layer 2 along the side surface of the second island-shaped structure b, and is extended and distributed on the surface of the N-type semiconductor layer 2 to also play a role in extending current on the N-type semiconductor layer 2.
Further, the first and second extension electrodes 51 and 52 are made of Cr, Ti, Al, Ni, Pt, Au, or an alloy of two or more of the above metal materials, and the thickness of the first and second extension electrodes 51 and 52 is 1nm to 3000 nm.
Since the first extended electrode 51 and the second extended electrode 52 are formed simultaneously by evaporation, the thicknesses of the first extended electrode 51 and the second extended electrode 52 are uniform, that is, the upper end surface of the first extended electrode 51 is flush with the upper end surface of the portion of the second extended electrode 52 above the second island-like structure b.
Specifically, in the present embodiment, the second extension electrode 52 is extended downward along the second island-shaped structure b toward the side surface of the first island-shaped structure a and the adjacent side surface thereof, so that the second extension electrode 52 has a larger contact area with the N-type semiconductor layer 2 to compensate for the defect that the second extension electrode 52 is not directly disposed on the N-type semiconductor layer 2. In another embodiment of the present invention, the shape of the second extended electrode 52 may be adjusted according to parameters such as the size and shape of the LED chip.
In some other embodiments of the present invention, a transparent conductive layer may be further disposed between the first extension electrode 51 and the first P-type semiconductor region 41 to further function as a current spreading layer, wherein the transparent conductive layer is an indium tin oxide layer or other transparent conductive material such as aluminum-doped zinc oxide, and has a thickness ranging from 10 nm to 300 nm.
Further, in some embodiments of the present invention, a passivation layer 6 is further disposed on the surface and the side surface of the LED chip, and the passivation layer 6 is SiO2Layer of or Si3N4Layer of or SiO2Layer and Ti3O5The protection layers with excellent insulating property, such as Bragg reflection layers and the like, which are alternately stacked are arranged in layers, and the passivation layer 6 is arranged to play a role in insulating and protecting the LED chip.
Furthermore, the side edge and the center of the N-type semiconductor layer 2 are exposed out of the substrate 1, the passivation layer 6 covers the substrate 1 exposed out of the side edge of the N-type semiconductor layer 2 to play a role in side short circuit protection, and a through hole (not shown) for exposing the substrate 1 is arranged in the middle of the N-type semiconductor layer 2 to serve as a thimble extending region, so that the surface structure of the LED chip is prevented from being damaged when the LED chip is jacked up by a thimble.
The passivation layer 6 is formed with a first via hole 61 and a second via hole 62 above the first extension electrode 51 and the second extension electrode 52, respectively, and a first pad electrode 71 and a second pad electrode 72 are disposed on the passivation layer 6 and fill the spaces in the first via hole 61 and the second via hole 62, respectively, so as to be electrically connected to the first extension electrode 51 and the second extension electrode 52.
Further, the first pad electrode 71 and the second pad electrode 72 are Cr, Ti, Al, Ni, Pt, Au, Sn or an alloy composed of two or more of the above metal materials, and the thickness of the first pad electrode 71 and the second pad electrode 72 is 1nm to 5000 nm.
Since the first pad electrode 71 and the second pad electrode 72 are formed simultaneously by vapor deposition, the first pad electrode 71 and the second pad electrode 72 have the same thickness, that is, the upper end surfaces of the first pad electrode 71 and the second pad electrode 72 are flush with each other.
In summary, in the present invention, the second P-type semiconductor region 42 and the second multi-quantum well region 32 for supporting the structure are disposed on the N-type semiconductor layer 2, and the extension electrode extending to the N-type semiconductor layer 2 is disposed above the second P-type semiconductor region, so as to electrically connect the second pad electrode 72 with the N-type semiconductor layer 2, thereby forming a structure with uniform height below the first pad electrode 71 and the second pad electrode 72, so that the upper end surfaces of the first pad electrode 71 and the second pad electrode 72 are flush, the problem of poor die bonding of the flip Mini LED chip during packaging can be effectively avoided, and sufficient welding strength can be ensured.
As shown in fig. 3, the present invention further provides a method for manufacturing a flip Mini LED chip, comprising the steps of:
s1: as shown in fig. 4, a substrate 1 is provided, and an N-type semiconductor layer 2, a multiple quantum well layer 3, and a P-type semiconductor layer 4 are grown in this order on the substrate 1.
The substrate 1 is made of sapphire, silicon carbide, silicon or a composite substrate 1 made of the materials, and can also be made of other common LED substrate 1 materials.
The N-type semiconductor layer 2 and the P-type semiconductor layer 4 are any one of group III nitride based semiconductor layers commonly used in the art, and the present invention is not particularly limited thereto.
In some embodiments of the invention, a nitride buffer layer may be further grown on the substrate 1 to reduce lattice mismatch between the substrate 1 and the semiconductor layer, thereby improving the growth quality of the epitaxial layer.
S2: as shown in fig. 5, the P-type semiconductor layer 4 and the multiple quantum well layer 3 are etched to form the first multiple quantum well region 31 and the second multiple quantum well region 32 which are arranged at intervals and the first P-type semiconductor region 41 and the second P-type semiconductor region 42 which are respectively located thereon.
Specifically, in the present embodiment, the P-type semiconductor layer 4 and the excess portions of the multiple quantum well region are etched to form the first island-like structure a and the second island-like structure b having rounded rectangular cross-sectional shapes, the first P-type semiconductor region 41 and the first multiple quantum well region 31 together form the first island-like structure a, and the second P-type semiconductor region 42 and the second multiple quantum well region 32 together form the second island-like structure b. In other embodiments, the etching area may also be adjusted according to the model size of the LED chip and the shape of the electrode.
Further, in some embodiments of the present invention, after step S2, the method further includes the steps of: the side edges and the central region of the N-type semiconductor layer 2 are etched to expose the substrate 1.
S3: as shown in fig. 6, a first extension electrode 51 and a second extension electrode 52 are respectively disposed on the first P-type semiconductor region 41 and the second P-type semiconductor region 42, the first extension electrode 51 is electrically connected to the first P-type semiconductor region 41, the second extension electrode 52 extends to the N-type semiconductor layer 2 and is electrically connected thereto, and the second extension electrode 52 is disposed with an insulating interval between the first P-type semiconductor region 41 and the first multi-quantum well region 31.
S4: as shown in fig. 7, a first pad electrode 71 and a second pad electrode 72 electrically connected thereto are formed on the first extension electrode 51 and the second extension electrode 52, respectively.
Further, in some embodiments of the present invention, before step S4, the method further includes the steps of:
and forming a passivation layer 6 on the surface and the side surface of the inverted Mini LED chip.
Specifically, the forming of the pad electrode includes the steps of:
two through holes are etched in the passivation layer 6 to expose the first and second extension electrodes 51 and 52, respectively.
A first pad electrode 71 and a second pad electrode 72 are deposited on the passivation layer 6, and the first pad electrode 71 and the second pad electrode 72 fill the through hole and are electrically connected to the first extension electrode 51 and the second extension electrode 52, respectively.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention and is not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention are included in the scope of the present invention.

Claims (11)

1. A flip Mini LED chip comprises a substrate, an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer in sequence,
the P-type semiconductor layer comprises a first P-type semiconductor region and a second P-type semiconductor region which are arranged at intervals, and the multi-quantum well layer comprises a first multi-quantum well region and a second multi-quantum well region which are respectively positioned below the first P-type semiconductor region and the second P-type semiconductor region;
a first expansion electrode electrically connected with the first P-type semiconductor region is arranged on the first P-type semiconductor region, a second expansion electrode is arranged on the second P-type semiconductor region, and the second expansion electrode extends to the N-type semiconductor layer and is electrically connected with the N-type semiconductor layer;
the first extension electrode and the second extension electrode are respectively provided with a first pad electrode and a second pad electrode which are electrically connected with the first extension electrode and the second extension electrode, and the upper end faces of the first pad electrode and the second pad electrode are flush.
2. The flip Mini LED chip of claim 1, wherein the first and second P-type semiconductor regions, the first and second multi-quantum well regions, the first and second extension electrodes, and the first and second pad electrodes are uniform in thickness, respectively.
3. The flip Mini LED chip of claim 2, wherein a passivation layer is further disposed on the surface and the side of the flip Mini LED chip, and the first pad electrode and the second pad electrode are disposed on the passivation layer and electrically connected to the first extension electrode and the second extension electrode through a via hole in the passivation layer, respectively.
4. The flip Mini LED chip of claim 3, wherein the passivation layer is SiO2Layer of or Si3N4Layer of or SiO2Layer and Ti3O5The layers are alternately stacked to form a Bragg reflection layer.
5. The flip Mini LED chip of claim 4, wherein the substrate is exposed at the sides and center of the N-type semiconductor layer, and the passivation layer covers the exposed portions of the substrate at the sides of the N-type semiconductor layer.
6. The flip Mini LED chip of claim 1, wherein the first and second extension electrodes are Cr, Ti, Al, Ni, Pt, Au or an alloy of two or more of the above metallic materials, and the thickness of the first and second extension electrodes is 1nm to 3000 nm.
7. The flip Mini LED chip of claim 1, wherein the first and second pad electrodes are Cr, Ti, Al, Ni, Pt, Au, Sn or an alloy of two or more of the above metallic materials, and the first and second pad electrodes have a thickness of 1nm to 5000 nm.
8. A manufacturing method of an inverted Mini LED chip is characterized by comprising the following steps:
providing a substrate, and growing an N-type semiconductor layer, a multi-quantum well layer and a P-type semiconductor layer on the substrate in sequence;
etching the P-type semiconductor layer and the multi-quantum well layer to form a first multi-quantum well region and a second multi-quantum well region which are arranged at intervals, and a first P-type semiconductor region and a second P-type semiconductor region which are respectively positioned on the first multi-quantum well region and the second multi-quantum well region;
respectively arranging a first extension electrode and a second extension electrode on the first P-type semiconductor region and the second P-type semiconductor region, wherein the first extension electrode is electrically connected to the first P-type semiconductor region, and the second extension electrode extends to the N-type semiconductor layer and is electrically connected with the N-type semiconductor layer;
and forming a first pad electrode and a second pad electrode electrically connected to the first extension electrode and the second extension electrode respectively.
9. The method of claim 8, wherein before the step of forming the first pad electrode and the second pad electrode electrically connected to the first extended electrode and the second extended electrode respectively, the method further comprises the steps of:
and forming a passivation layer on the surface and the side surface of the inverted Mini LED chip.
10. The method of claim 9, wherein the step of forming a first pad electrode and a second pad electrode electrically connected to the first extended electrode and the second extended electrode respectively comprises:
etching to form two through holes on the passivation layer, and respectively exposing the first extension electrode and the second extension electrode;
and evaporating a first pad electrode and a second pad electrode on the passivation layer, wherein the through hole is filled with the first pad electrode and the second pad electrode, and the first pad electrode and the second pad electrode are respectively and electrically connected with the first extension electrode and the second extension electrode.
11. The method of claim 8, further comprising the step of, after "etching the P-type semiconductor layer and the multiple quantum well layer":
and etching the side edge and the central area of the N-type semiconductor layer until the substrate is exposed.
CN202110250074.0A 2021-03-08 2021-03-08 Inverted Mini LED chip and manufacturing method thereof Pending CN113345986A (en)

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