CN113345838B - Semiconductor device cleavage method - Google Patents
Semiconductor device cleavage method Download PDFInfo
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- CN113345838B CN113345838B CN202110894220.3A CN202110894220A CN113345838B CN 113345838 B CN113345838 B CN 113345838B CN 202110894220 A CN202110894220 A CN 202110894220A CN 113345838 B CN113345838 B CN 113345838B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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Abstract
The invention provides a semiconductor device cleavage method, and relates to the technical field of semiconductor processing. The semiconductor device cleavage method comprises the following steps: forming a concave structure which is concave towards one side of the lower surface on the upper surface of the semiconductor device in a plasma etching or chemical etching mode, wherein the width of the concave structure is gradually reduced from the upper surface of the semiconductor device to the lower surface; and cleaving the semiconductor device along a depth direction of the recess structure. The width of the concave structure is gradually reduced to extend towards the inside of the semiconductor device, and the stress can be more concentrated when the semiconductor device is cleaved from the position. The insulating protective layer is formed on the upper surface of the semiconductor device, so that short circuit and electric leakage caused by electric contact between P-surface electrons and an N-surface substrate due to the fact that solder is easy to move to the side surface of the semiconductor device in the packaging process of a small semiconductor device after subsequent cleavage can be prevented.
Description
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to a semiconductor device cleavage method.
Background
In semiconductor processing, a whole semiconductor device needs to be cleaved into a plurality of individual small semiconductor structures, and in the prior art, a dicing line is cut on the whole semiconductor device by using a dicing blade, and then the semiconductor device is separated along the dicing line, which is similar to a method of cutting a glass plate.
When the method is adopted to cut the whole semiconductor device, because the width of the cutting edge of the scribing knife is larger, the width of the scribing cutting line is also larger, and when the semiconductor device is cleaved, a single small semiconductor structure is broken when being separated due to the fact that stress is not concentrated, and the quality of the small semiconductor structure is reduced. Meanwhile, the solder adopted during packaging of the cleaved small semiconductor structure is indium, the solder easily climbs to the side face of the small semiconductor structure, and under the quasi-continuous pulse operation, the indium solder can generate electromigration to form a leakage channel. The resistance of a leakage channel formed by the indium solder is far smaller than the resistance between the P surface and the N surface of the small semiconductor structure, and when the small semiconductor structure is electrified, large current flows through the leakage channel, so that the P surface and the N surface of the small semiconductor structure are in electric contact to form a short circuit.
Disclosure of Invention
The invention aims to provide a semiconductor device cleavage method, which is used for relieving the technical problems that the edge of a single small semiconductor structure is broken and the quality is reduced due to the fact that stress is not concentrated when the conventional semiconductor device is cleaved, and the P surface and the N surface of the cleaved small semiconductor structure are in electric contact to form a short circuit.
The semiconductor device cleavage method provided by the embodiment of the invention comprises the following steps:
s10, forming a concave structure which is concave towards one side of the lower surface on the upper surface of the semiconductor device in a plasma etching or chemical corrosion mode, wherein the width of the concave structure is gradually reduced from the upper surface of the semiconductor device to the lower surface;
s20, forming an insulating protective layer on the upper surface of the semiconductor device;
and S30, cleaving the semiconductor device along the depth direction of the concave structure.
Further, the semiconductor device cleaving method further includes, before the step S10, the step of:
s1, forming a photoresist layer on the upper surface of the semiconductor device, wherein the photoresist layer has a first opening penetrating the upper and lower surfaces of the photoresist layer;
s2, etching the semiconductor device by taking the photoresist layer with the first opening as a mask to form a first groove;
s3, forming first side walls on two opposite side walls of the first groove respectively, wherein a gap is formed between the two first side walls in the same first groove;
and S4, etching the bottom of the first groove by taking the two first side walls in the same first groove as masks to form a second groove, wherein the bottom surface of the second groove is used for forming a concave structure.
Further, the step S3 specifically includes the steps of:
forming a covering layer on the inner wall of the first groove, etching and removing the middle part of the covering layer, and forming first side walls on the two remaining side parts of the covering layer;
or, forming the first side wall by using chemical vapor deposition.
Further, the step of forming a concave structure on the upper surface of the semiconductor device by plasma etching in step S10 includes:
s111, forming second side walls on two opposite side walls of the second groove respectively in a chemical vapor deposition mode from top to bottom, wherein the distance between the two second side walls is gradually reduced, and the bottoms of the two second side walls are in contact with each other;
and S112, carrying out plasma etching on the bottom surface of the second groove by using the photoresist layer, the first side wall and the second side wall as masks, and forming a concave structure on the bottom surface of the second groove after the second side wall structure and the semiconductor device are etched.
Further, the first side wall and the second side wall are made of silicon oxide or silicon nitride.
Further, in step S112: the plasma etching adopts an inductively coupled plasma process, wherein the source power of the inductively coupled plasma process is 1400W-1600W, the bias power is 90W-110W, the chlorine flow is 18ml/min-22ml/min, the boron trichloride flow is 6ml/min-10ml/min, and the argon flow is 4 ml/min-6 ml/min.
Further, the step of forming a recessed structure recessed toward the lower surface side on the upper surface of the semiconductor device by means of chemical etching in step S10 specifically includes the steps of:
s121, forming a light resistance layer on the upper surface of the semiconductor device, wherein the light resistance layer is provided with a first opening penetrating through the upper surface and the lower surface of the light resistance layer;
s122, etching the semiconductor device by using the photoresist layer with the first opening as a mask to form a first groove;
s123, forming side wall structures on two opposite side walls of the first groove by using a photoresist material, wherein the height value of each side wall structure is greater than or equal to the depth value of the first groove, and a gap is formed between the two side wall structures;
and S124, chemically etching the bottom surface of the first groove by using an etching solution, and forming a concave structure on the bottom surface of the first groove.
Further, the thickness of the insulating protection layer is 100-200 nm.
Further, the semiconductor device cleavage method further includes the steps of:
providing a chamber comprising a passivation station and a cleaving station;
forming an insulating protective layer on the upper surface of the semiconductor device at a passivation station;
a step of cleaving the semiconductor device in a depth direction of the recess structure at a cleaving station;
after the semiconductor device is cleaved, the cleaved semiconductor device is transported to a passivation station and subjected to a passivation process to form a passivation layer on the cleaved surface of the semiconductor device.
The semiconductor device cleavage method provided by the embodiment of the invention comprises the following steps: firstly, forming a concave structure which is concave towards one side of a lower surface on the upper surface of a semiconductor device in a plasma etching or chemical etching mode, wherein the width of the concave structure is gradually reduced from the upper surface of the semiconductor device to the lower surface; then, forming an insulating protection layer on the upper surface of the semiconductor device; finally, the semiconductor device is cleaved in the depth direction of the recess structure. The size of the concave structure obtained by plasma etching or chemical corrosion can reach micron level, and the size of the concave structure is far smaller than a line groove cut by a scribing knife. Moreover, the width of the concave structure gradually decreases towards the inside of the semiconductor device, and the semiconductor device can be cleaved from the position, so that stress can be more concentrated during cleavage, and the semiconductor device can be more easily cleaved. Before the semiconductor device is cleaved, an insulating protection layer is formed on the upper surface of the semiconductor device, the insulating protection layer can prevent short circuit and electric leakage caused by electric contact between P-surface electrons and an N-surface substrate due to the fact that solder is easy to move to the side surface of the semiconductor device in the subsequent process of packaging the small semiconductor device after the semiconductor device is cleaved, the solder can be separated by the insulating protection layer, and therefore the short circuit and the ignition phenomenon cannot be caused even if the solder climbs. By adopting the method, the processing of the concave structure can be carried out on the semiconductor device when the structure of the semiconductor device is designed, the previous process is not increased, the step of marking off required in the next process can be reduced, the yield is increased, and the product performance is improved; meanwhile, the insulating protection layer can be processed on the semiconductor device when the structure of the semiconductor device is designed, namely the whole semiconductor device is processed uniformly, compared with the process of coating a film on a single small semiconductor device with a small volume, the efficiency of processing the insulating protection layer uniformly is higher, and the operation is easier.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of step S2 in the semiconductor device cleaving method according to embodiment 1 of the present invention;
fig. 2 is a schematic diagram of step S3 in the semiconductor device cleaving method according to embodiment 1 of the present invention;
fig. 3 is a schematic diagram of step S4 in the semiconductor device cleaving method according to embodiment 1 of the present invention;
fig. 4 is a schematic diagram of step S111 in the semiconductor device cleaving method provided in embodiment 1 of the present invention;
fig. 5 is a schematic diagram of step S112 in the semiconductor device cleaving method according to embodiment 1 of the present invention;
fig. 6 is a schematic diagram of step S20 in the semiconductor device cleaving method according to embodiment 1 of the present invention;
fig. 7 is a schematic diagram of step S123 in the semiconductor device cleaving method according to embodiment 2 of the present invention.
Icon: 100-a semiconductor device; 110 — a first trench; 120-a second trench; 200-a photoresist layer; 210-a first opening; 310-a first sidewall; 320-a second side wall; 400-a concave structure, 500-an insulating protective layer; 600-side wall structure.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
The semiconductor device cleavage method provided by the embodiment of the invention comprises the following steps:
s10, forming a concave structure 400 which is concave towards one side of the lower surface on the upper surface of the semiconductor device 100 in a plasma etching or chemical etching mode, wherein the width of the concave structure 400 is gradually reduced from the upper surface of the semiconductor device 100 to the lower surface. The size of the recess structure 400 obtained by plasma etching or chemical etching can reach micron level, and the size is far smaller than the line groove scribed by the scribing knife. Furthermore, the width of the recess structure 400 gradually decreases toward the inside of the semiconductor device 100, and cleavage is performed from this position, so that stress can be more concentrated during cleavage, and the semiconductor device 100 can be more easily cleaved.
The semiconductor device cleaving method further includes the step performed before step S10 of:
s1, a photoresist layer 200 is formed on the upper surface of the semiconductor device 100, and the photoresist layer 200 has a first opening 210 penetrating the upper and lower surfaces of the photoresist layer.
As shown in fig. 1, a photoresist layer 200 may be formed on the upper surface of the semiconductor device 100 by spin coating, and then a first opening 210 is formed in the photoresist layer 200 by exposure, development, or the like, wherein the first opening 210 penetrates through the upper and lower surfaces of the photoresist layer 200, and the first opening 210 exposes the upper surface of the semiconductor device 100, so that the upper surface of the semiconductor device 100 may be processed through the first opening 210.
S2, using the photoresist layer 200 with the first opening 210 as a mask, etching the semiconductor device 100 and forming a first trench 110.
As shown in fig. 1, from top to bottom, the upper surface of the semiconductor device 100 may be etched by photolithography, so as to obtain a first trench 110 extending toward the lower surface. The front and rear ports of the first trench 110 are respectively communicated with two opposite edges of the semiconductor device.
And S3, forming first side walls 310 on two opposite side walls of the first groove 110 respectively, wherein the two first side walls 310 are arranged at intervals.
Specifically, as shown in fig. 2, in one manner that the first sidewall 310 may be formed, a capping layer material may be deposited from top to bottom toward the entire first trench 110, the capping layer material may uniformly fall on the bottom surface of the first trench 110 and may be adsorbed on the two opposite sidewalls of the first trench 110 during the falling process, so as to form a capping layer on the inner walls of the first trench 110, the capping layer material may be silicon oxide or silicon nitride, and then, selective etching is performed, so that only a portion of the capping layer attached to the sidewalls of the first trench 110 remains, and a portion of the capping layer in the middle region of the bottom of the first trench 110 is removed, so as to form the first sidewall 310.
In another manner of forming the first sidewall 310, the first sidewall 310 may also be formed by chemical vapor deposition, wherein silicon oxide or silicon nitride is deposited from top to bottom at the positions of the two opposite sidewalls of the first trench 110, respectively, and the silicon oxide or silicon nitride may be attached to the sidewalls of the first trench 110 to gradually deposit and form the first sidewall 310. The first sidewall 310 is formed by deposition and deposition, and the first sidewall material is deposited above the sidewall of the first trench 110 from top to bottom, most of the material falls to the bottom of the first trench 110 under the action of gravity, and a part of the material is attracted by the sidewall of the first trench 110 and adheres to the sidewall of the first trench 110, and as the deposition time is prolonged, more material is deposited on the lower portion of the first sidewall 310, and less material adheres to the sidewall of the first trench 110. The first sidewalls 310 are narrow at the top and wide at the bottom, so that the gap between two first sidewalls 310 in the same first groove 110 is gradually increased from bottom to top.
S4, etching the bottom of the first trench 110 with the two first sidewalls 310 as masks to form a second trench 120, wherein the bottom surface of the second trench 120 is used to form the recess structure 400.
As shown in fig. 3, a gap is formed between two first sidewalls 310 in the same first trench 110, and the second trench 120 can be processed by etching using the first sidewalls 310 as a mask, and the width of the second trench 120 is significantly smaller than that of the first trench 110, and the recess structure 400 can be disposed on the bottom surface of the second trench 120. In this embodiment, after the secondary trench processing, a deeper trench structure may be formed in both the first trench 110 and the second trench 120, and the cleavage position is also on the bottom surface of the deeper trench structure, that is, a deeper trench structure is opened on the surface of the semiconductor device 100 in advance, so that the subsequent cleavage of the semiconductor device 100 may be easier.
The step of forming the recess structure 400 recessed toward the lower surface side on the upper surface of the semiconductor device 100 by plasma etching in step S10 specifically includes:
s111, forming second sidewalls 320 on two opposite sidewalls of the second trench 120 by chemical vapor deposition, wherein the distance between the two second sidewalls 320 is gradually decreased from top to bottom, and the bottoms of the two second sidewalls 320 are in contact with each other.
As shown in fig. 4, the material of the second sidewall 320 may be silicon oxide or silicon nitride, and when depositing the second sidewall material, since the corners of the bottom surface of the second trench 120 are easy to attract atomic structures, the second sidewall material may be firstly accumulated at the corners of the bottom surface of the second trench 120, and the second sidewall material at the middle position of the bottom of the second trench is relatively less. Since the second sidewall material and the material of the semiconductor device 100 cannot be bonded immediately, the second sidewall material is deposited from top to bottom above the sidewall of the second trench 120, most of the material falls to the bottom of the second trench 120 under the action of gravity, a portion of the material is attracted by the sidewall of the first sidewall 310 and the sidewall of the second trench 120 and adheres to the sidewall of the first sidewall 310 and the sidewall of the second trench 120, as the deposition time increases, more material is deposited on the lower portion of the second sidewall 320, and less material adheres to the upper portion of the sidewall of the first sidewall 310 and the sidewall of the second trench 120, so that the stacked second sidewall 320 has a shape in which the lower portion is thicker and the upper portion is thinner, and the distance between the two second sidewalls 320 adhering to the sidewalls of the first sidewall 310 and the second trench 120 also decreases from top to bottom, as the deposition continues, the bottoms of the two second sidewalls 320 on both sides of the deeper trench structure are contacted together, and a Y-shaped opening is formed between the two second sidewalls 320.
S112, using the photoresist layer 200, the first sidewall 310 and the second sidewall 320 as masks, performing plasma etching on the bottom surface of the second trench 120, and forming a recess structure 400 on the bottom surface of the second trench 120 after the second sidewall 320 structure and the semiconductor device 100 are etched.
As shown in fig. 5, the second sidewall 320 structure and the semiconductor device 100 may be etched by using an inductively coupled plasma process, because a gap exists between the contact regions of the two second sidewalls 320, and the shape of the gap is Y-shaped. Etching the second side walls 320 from the middle position, namely the position where the two second side walls 320 are in contact, wherein the second side walls 320 in the middle part are etched by the plasma along with the etching, a part of the semiconductor device 100 is exposed in the middle position, and the part of the semiconductor device 100 is etched firstly; with the progress of the etching, portions of the second sidewall 320 near both sides are gradually etched away, portions of the semiconductor device 100 are exposed near both sides, and then the portions of the semiconductor device 100 are etched again, and the time for etching the later exposed portion of the semiconductor device 100 is always less than that for etching the other portion of the semiconductor device 100 that leaks out first, so that the portion of the semiconductor device near the middle is etched deepest and extends to both sides, and the etching depth is gradually reduced, so that a V-shaped opening is formed on the bottom surface of the second trench 120, that is, the recess structure 400 is formed.
A deeper trench structure is formed by the first side wall 310 and the second side wall 320, and the recessed structure 400 is formed on the bottom surface of the second trench 120 by the second side wall 320, so that, compared with the conventional etching in which a deviation is likely to occur in the cleavage direction or the accuracy of a diamond-scribed cleavage line is poor, by controlling the positions of the first side wall 310 and the second side wall 320, a better recessed structure 400 with a V-shaped opening can be formed at the bottom of the second trench 120, the position of the cleavage line can be better controlled, and accurate cleavage can be achieved.
In the inductively coupled plasma process, the source power is 1400W-1600W, the bias power is 90W-110W, the chlorine flow is 18ml/min-22ml/min, the boron trichloride flow is 6ml/min-10ml/min, and the argon flow is 4 ml/min-6 ml/min. Specifically, the source power is 1500W, the bias power is 100W, the chlorine flow is 20ml/min, the boron trichloride flow is 8ml/min, and the argon flow is 5 ml/min. By adopting the parameters in the range for etching, the V-shaped opening with complete morphological characteristics can be obtained.
S20, an insulating protection layer 500 is formed on the upper surface of the semiconductor device.
As shown in fig. 6, the upper surface of the semiconductor device 100 may be coated before the semiconductor device 100 is cleaved. In this embodiment, after the recess structure 400 is formed, the photoresist layer 200, the first sidewall 310 and the second sidewall 320 are removed, and then the surface of the semiconductor device 100 is coated, so as to form the insulating protection layer 500, wherein the insulating protection layer 500 may be made of silicon nitride or silicon oxide. The thickness of the insulating protection layer 500 may be 100nm to 200nm, and although the insulating protection layer 500 may also be formed in the recess structure 400, since the thickness of the insulating protection layer 500 is in the nanometer level, the V-shaped opening may not be completely filled, and even if there is a portion of the filling, since the material of the filling is different from that of the semiconductor device, and the degree of compactness is different from that of the internal structure of the semiconductor device 100, the portion of the recess structure 400 may still be stress-concentrated during cleavage, which is convenient for better cleavage. The formation of the insulating protective layer 500 can prevent the P-side electrons from electrically contacting the N-side substrate to form short circuits and leakage current due to the easy migration of solder from the side surface to the side surface of the semiconductor device during the subsequent packaging process, so that the short circuits and sparking phenomena can not be formed even if the solder climbs.
In addition, in this embodiment, the deeper trench structure formed by the first trench 110 and the second trench 120 is stepped, so that after coating, the stepped surface of the stepped structure can make the insulating protection layer 500 adhere better, thereby reducing the risk of collapse of the insulating protection layer 500, and when a single semiconductor device is formed subsequently, the structural stability of the insulating protection layer 500 is better, thereby improving the yield.
S30, the semiconductor device 100 is cleaved in the depth direction of the recess structure 400.
Further, the semiconductor device cleavage method further includes the steps of: providing a chamber comprising a passivation station and a cleaving station; a step of forming an insulating protection layer 500 on the upper surface of the semiconductor device 100 at a passivation station; performing a step of cleaving the semiconductor device 100 in a depth direction of the recess structure 400 at a cleaving station; after the semiconductor device 100 is cleaved, the cleaved semiconductor device 100 is transported to a passivation station and subjected to a passivation process to form a passivation layer on the cleaved surface of the semiconductor device 100.
The semiconductor device 100 with the recessed structure 400 is placed in a passivation station to form the insulating protection layer 500, after the insulating protection layer 500 is formed, the semiconductor device 100 is conveyed to a cleavage station from the passivation station to cleave, and the V-shaped recessed structure 400 is formed in a cleavage region of the semiconductor device 100, so that stress concentration is facilitated, and cleavage can be better performed along a groove. The cleaved semiconductor device 100 forms a single semiconductor device, which is transported to a passivation station again, and then the cleaved facets of the single semiconductor device are passivated to form passivation layers protecting the front and back facets. The passivation layer is nitride, and the passivation station and the cleavage station are positioned in the same chamber, and are directly sent to the passivation station for passivation after cleavage, so that the cleavage chamber surface can be prevented from being polluted due to long-time exposure, and the passivation layer and the insulating protection layer 500 are formed at the same station, so that the time of vacuumizing and passivation can be saved, the passivation time is further shortened, and the working procedures are saved. After cleavage, the cleavage cavity surface of the single small semiconductor device is passivated again, so that the stability of the single small semiconductor device can be improved, and the performance change of the single small semiconductor device caused by oxidation can be prevented.
The thickness of the passivation layer is less than that of the insulating protection layer 500, and the passivation layer can also play a certain role in preventing current leakage.
Example 2
Unlike embodiment 1, in the present embodiment, the method of forming the recessed structure 400 is different, and the step of forming the recessed structure 400 recessed toward the lower surface side on the upper surface of the semiconductor device 100 by means of chemical etching in step S10 specifically includes the steps of:
s121, forming a light resistance layer 200 on the upper surface of the semiconductor device 100, wherein the light resistance layer 200 is provided with a first opening 210 penetrating through the upper surface and the lower surface of the light resistance layer; s122, using the photoresist layer 200 with the first opening 210 as a mask, etching the semiconductor device 100 and forming a first trench 110.
A photoresist layer 200 may be formed on the upper surface of the semiconductor device 100 by spin coating, and then a first opening 210 may be formed in the photoresist layer 200 by exposure, development, etc., wherein the first opening 210 penetrates through the upper and lower surfaces of the photoresist layer 200. From top to bottom, the upper surface of the semiconductor device 100 may be etched by photolithography, thereby obtaining a first trench 110 extending to the lower surface.
And S123, forming side wall structures 600 on two opposite side walls of the first groove 110 by using a photoresist material, wherein the height value of each side wall structure 600 is greater than or equal to the depth value of the first groove 110, and a gap is formed between the two side wall structures 600. And S124, chemically etching the bottom surface of the first groove 110 by using an etching solution, and forming a concave structure 400 on the bottom surface of the first groove 110.
As shown in fig. 7, a photoresist material may be filled in the first trench 110 and the first opening 210, then a mask plate with an opening smaller than the first opening 210 is used to align the center of the opening on the mask plate with the center of the first opening 210, and then the mask plate is used to expose and develop the photoresist filled in the first trench 110 and the first opening 210, so as to obtain two sidewall structures 600 located at two opposite sides of the first trench, and the photoresist material between the two sidewall structures 600 is removed. The height value of the sidewall structure 600 is greater than or equal to the depth value of the first trench 110, and the top of the sidewall structure 600 may be connected to the photoresist layer 200, so as to protect the sidewall of the first trench 110 from being corroded, and only the portion of the bottom of the first trench 110 that needs to be etched is left. Putting the semiconductor device 100 into an etching solution, and preparing the etching solution by using saturated bromine water, phosphoric acid and pure water, wherein the volume ratio can be 2: 1: 15. since the crystal lattice of the semiconductor device 100 has horizontal and vertical orientations, the etching liquid is etched in the direction of the crystal lattice during chemical etching. The semiconductor device 100 is etched at a rate greater in the vertical direction than in the horizontal direction, so that the recess structure 400 having a V-shaped cross-sectional shape is formed. Since the recess structure 400 is made by chemical etching, no material debris is generated. The surface of the cleaved semiconductor device is ensured to be clean, and the quality and the yield of chips are improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. A semiconductor device cleaving method, comprising:
s10, forming a concave structure (400) which is concave towards one side of the lower surface on the upper surface of the semiconductor device (100) through plasma etching, wherein the width of the concave structure (400) is gradually reduced from the upper surface of the semiconductor device (100) towards the direction of the lower surface;
s20, forming an insulating protection layer (500) on the upper surface of the semiconductor device (100);
s30, cleaving the semiconductor device (100) along the depth direction of the recessed structure (400);
the semiconductor device cleaving method further includes the step performed before step S10 of:
s1, forming a photoresist layer (200) on the upper surface of the semiconductor device (100), wherein the photoresist layer (200) has a first opening (210) penetrating the upper and lower surfaces of the photoresist layer;
s2, etching the semiconductor device (100) by taking the photoresist layer (200) with the first opening (210) as a mask to form a first groove (110);
s3, forming first side walls (310) on two opposite side walls of the first groove (110) respectively, wherein a gap is formed between the two first side walls (310) in the same first groove (110);
s4, etching the bottom of the first groove (110) by using the two first side walls (310) in the same first groove (110) as masks to form a second groove (120), wherein the bottom surface of the second groove (120) is used for forming a concave structure (400);
the step of forming the recess structure (400) recessed to the lower surface side on the upper surface of the semiconductor device (100) by means of plasma etching in step S10 specifically includes:
s111, forming second side walls (320) on two opposite side walls of the second groove (120) respectively in a chemical vapor deposition mode, wherein the distance between the two second side walls (320) is gradually reduced from top to bottom, and the bottoms of the two second side walls (320) are contacted;
and S112, using the photoresist layer (200), the first side wall (310) and the second side wall (320) as masks, carrying out plasma etching on the bottom surface of the second groove (120), and forming a concave structure (400) on the bottom surface of the second groove (120) after the second side wall (320) structure and the semiconductor device (100) are etched.
2. The semiconductor device cleaving method according to claim 1, wherein the step S3 specifically includes the steps of:
forming a covering layer on the inner wall of the first groove (110), etching and removing the middle part of the covering layer, and forming first side walls (310) on the two remaining side parts of the covering layer;
alternatively, the first side walls (310) are formed using chemical vapor deposition.
3. The semiconductor device cleaving method according to claim 1, wherein the material of the first sidewall spacers (310) and the second sidewall spacers (320) is silicon oxide or silicon nitride.
4. The semiconductor device cleaving method according to claim 1, wherein in the step S112: the plasma etching adopts an inductively coupled plasma process, wherein the source power of the inductively coupled plasma process is 1400W-1600W, the bias power is 90W-110W, the chlorine flow is 18ml/min-22ml/min, the boron trichloride flow is 6ml/min-10ml/min, and the argon flow is 4 ml/min-6 ml/min.
5. The method as claimed in claim 1, wherein the thickness of the insulating protection layer (500) is 100-200 nm.
6. A semiconductor device cleaving method according to claim 1, further comprising the steps of:
providing a chamber comprising a passivation station and a cleaving station;
performing a step of forming an insulating protection layer (500) on an upper surface of the semiconductor device (100) at a passivation station;
performing a step of cleaving the semiconductor device (100) in a depth direction of the recess structure (400) at a cleaving station;
after the semiconductor device (100) is cleaved, the cleaved semiconductor device (100) is transported to a passivation station and subjected to a passivation process to form a passivation layer on the cleaved surface of the semiconductor device (100).
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