CN113342715A - On-site programmable gate array device and memory power supply control method - Google Patents
On-site programmable gate array device and memory power supply control method Download PDFInfo
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- CN113342715A CN113342715A CN202110649146.9A CN202110649146A CN113342715A CN 113342715 A CN113342715 A CN 113342715A CN 202110649146 A CN202110649146 A CN 202110649146A CN 113342715 A CN113342715 A CN 113342715A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The embodiment of the application discloses a field programmable gate array device and a power supply control method of a memory in the field programmable gate array device. The memory does not need to work in a full-enabled state all the time, and the power consumption of the memory in the field programmable gate array device is greatly reduced. And further, the problems that the field programmable gate array device is too high in working temperature and difficult to radiate heat are solved.
Description
Technical Field
The present application relates to the field of digital circuits, and in particular, to a field programmable gate array device and a memory power control method.
Background
A Field Programmable Gate Array (FPGA) device belongs to a semi-custom circuit in an application-specific integrated circuit, is a Programmable logic Array, and can effectively solve the problem of less Gate circuits of the original device.
Memory utilization in an FPGA chip is low, for example, the memory utilization in the FPGA chip is 50%, and the remaining 50% of the memory resources are not utilized, but the useless memory resources still consume power. In addition, even the memory resources being used are not always in a read-write state. In many cases, the memory is in a read-write state only for a few times, and only the content needs to be saved for most of the time.
However, in the configuration of the existing FPGA chip, all functional logics of the memory are powered on and enabled at one time, which causes waste of power consumption of the FPGA chip. When the solar cell is applied on a large scale, the problem that the temperature is too high, the heat dissipation is difficult and the like can be caused by the overlarge power consumption.
Disclosure of Invention
It is an object of the present application to provide a field programmable gate array device and a memory power control method therein, which can improve the above-mentioned problems.
The embodiment of the application is realized as follows:
in a first aspect, the present application provides a field programmable gate array device, comprising:
a memory including a power down signal port and a sleep signal port; and the memory respectively controls the working state of the memory according to the control signals received by the power-off signal port and the dormancy signal port.
In an optional embodiment of the present application, the memory includes a power control module, a sleep control module, a storage module, and a read/write control circuit; the power supply control module is provided with the power-off signal port, and the dormancy control module is provided with the dormancy signal port; the power supply control module, the dormancy control module and the read-write control circuit are respectively connected with the storage module.
Correspondingly, the present application provides a method for controlling a memory power supply of a field programmable gate array device, where the method is applied to any one of the field programmable gate array devices of the first aspect, and the method includes:
control signals respectively received through a power-off signal port on the memory and a sleep signal port on the memory;
and controlling the working state of the memory according to the type of the received control signal.
In an alternative embodiment of the present application, the controlling the operating state of the memory according to the type of the received control signal includes: controlling to stop supplying power to the storage module according to the control signal received by the power supply control module through the power supply signal port; and controlling the memory to be in a dormant state and stopping reading and writing operations by the dormant control module according to the control signal received by the dormant signal port.
In this embodiment, the control signal received by the power-off signal port may be a power-off signal; the control signal received by the sleep signal port may be a sleep signal.
In the embodiment of the application, under the condition that the power-off signal is at a high level, the power supply of all circuits in the memory is closed, the content stored in the storage module is also destroyed, and the memory does not consume any electric quantity in the state. And under the condition that the power-off signal is at a low level, the power supply of all circuits in the memory is started, all functions of the memory are enabled, and the consumed electric quantity of the memory is the maximum under the state.
In the embodiment of the application, under the condition that the sleep signal is at a high level, the memory is in a sleep state, all functional circuits except the memory module which continues to supply power to save the stored data content are powered off, and the memory operates at low power consumption in the state. When the sleep signal is at a low level, the memory is in a non-sleep state, and other functional circuits except the memory module can also selectively continue to supply power, wherein the memory operates at high power consumption.
It can be understood that, in the field programmable gate array device and the memory power control method thereof disclosed in the first aspect, the power-off signal port and the sleep signal port are additionally arranged on the memory, so that the memory can be flexibly switched among a low power consumption state (sleep state), a high power consumption state, a full enable state and a full power-off state according to the power-off signal and the sleep signal. The memory does not need to work in a full-enabled state all the time, and the power consumption of the memory in the field programmable gate array device is greatly reduced. And further, the problems that the field programmable gate array device is too high in working temperature and difficult to radiate heat are solved.
In a second aspect, the present application further provides another field programmable gate array device, based on the field programmable gate array device disclosed in the first aspect, the field programmable gate array device further includes: and configuring a code stream memory, a first selector and a second selector.
The first selector and the second selector both comprise a high-level input end and a low-level input end, the gating ends of the first selector and the second selector are electrically connected with the configuration code stream storage, the output end of the first selector is electrically connected with the power-off signal port, and the output end of the second selector is electrically connected with the sleep signal port.
In an alternative embodiment of the present application, the field programmable gate array device further includes a programmable logic module; the first selector further comprises a first custom input end, and the second selector further comprises a second custom input end; the first user-defined input end and the second user-defined input end are electrically connected with the programmable logic module.
Correspondingly, the present application also provides another method for controlling a memory power supply of a field programmable gate array device, where the method is applied to the field programmable gate array device according to any one of the second aspects, and the method further includes, on the basis of the method of the first aspect:
three input ends of the first selector respectively receive a high level signal, a low level signal and a first self-defining signal, and three input ends of the second selector respectively receive a high level signal, a low level signal and a second self-defining signal;
receiving a first selection signal configuration code stream sent by the configuration code stream storage through the first selector, and receiving a second selection signal configuration code stream sent by the configuration code stream storage through the second selector;
and configuring a code stream through the first selection signal to output a power-off signal, and configuring the code stream through the second selection signal to output a sleep signal.
In an optional embodiment of the present application, configuring, by the first selector according to the first selection signal, a code stream to output the power-off signal includes: selecting one signal from the high level signal, the low level signal and the first user-defined signal as the power-off signal according to the first selection signal configuration code stream through the first selector; configuring a code stream to output the sleep signal according to the second selection signal through the second selector, including: and selecting one signal from the high level signal, the low level signal and the second user-defined signal as the sleep signal according to the second selection signal configuration code stream through the second selector.
In an optional embodiment of the present application, the programmable logic module is electrically connected to the configuration code stream memory, and the programmable logic module is electrically connected to the memory through a read-write line.
Correspondingly, the method further comprises the following steps: receiving a user-defined configuration code stream sent from the configuration code stream memory through the programmable logic module; outputting the first user-defined signal to the first selector through the programmable logic module according to the user-defined configuration code stream; and outputting the second custom signal to the second selector through the programmable logic module according to the custom configuration code stream.
It will be appreciated that the user can perform dynamic control of the memory power supply according to his own logic. The programmable logic module can be configured according to a self-defined configuration code stream output by the configuration code stream memory, and outputs a first self-defined signal as the self definition of a power-off signal by a user, namely, the user can control the time period of the memory in a full-enabled working state and a full-power-off working state through the first self-defined signal. The programmable logic module can be configured according to the user-defined configuration code stream output by the configuration code stream memory, and outputs a second user-defined signal as the user-defined of the sleep signal, namely, the user can control the time period of the memory in the sleep state and the high-power-consumption working state through the second user-defined signal.
According to the technical scheme, the power-off signal port and the dormancy signal port are additionally arranged on the memory, so that the memory can be flexibly switched among a low power consumption state, a high power consumption state, a full enabling state and a full power-off state according to the power-off signal and the dormancy signal. The memory does not need to work in a full-enabled state all the time, and the power consumption of the memory in the field programmable gate array device is greatly reduced. And further, the problems that the field programmable gate array device is too high in working temperature and difficult to radiate heat are solved.
In addition, the user can dynamically control the power supply of the memory according to own logic. The programmable logic module can be configured according to a self-defined configuration code stream output by the configuration code stream memory, and outputs a first self-defined signal as the self definition of a power-off signal by a user, namely, the user can control the time period of the memory in a full-enabled working state and a full-power-off working state through the first self-defined signal. The programmable logic module can be configured according to the user-defined configuration code stream output by the configuration code stream memory, and outputs a second user-defined signal as the user-defined of the sleep signal, namely, the user can control the time period of the memory in the sleep state and the high-power-consumption working state through the second user-defined signal.
To make the aforementioned objects, features and advantages of the present application more comprehensible, alternative embodiments accompanied with figures are described in detail below.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions, and it will be understood by those skilled in the art that the drawings are not necessarily drawn to scale, in which:
FIG. 1 is an internal circuit diagram of a prior art field programmable gate array device and memory power control method therein;
fig. 2 is a schematic structural diagram of a field programmable gate array device disclosed in the first aspect of the present application;
FIG. 3 is a flow diagram of a memory power control method matched to the field programmable gate array device shown in FIG. 2;
FIG. 4 is a schematic diagram of a field programmable gate array device disclosed in a second aspect of the present application;
fig. 5 is a flow chart illustrating a memory power control method matched to the field programmable gate array device shown in fig. 4.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely exemplary of some, and not all, of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1, in the configuration of the conventional FPGA chip, all functional logic of the memory is powered on and enabled at one time. However, the memory utilization in the FPGA chip is low, for example, the memory utilization in the FPGA chip is 50%, and the remaining 50% of the memory resources are not utilized, but the useless memory resources still consume power. In addition, even the memory resources being used are not always in a read-write state. In many cases, the memory is in a read-write state only for a few times, and only the content needs to be saved for most of the time.
Therefore, the technical solution in the prior art causes the waste of the power consumption of the FPGA chip. When the solar cell is applied on a large scale, the problem that the temperature is too high, the heat dissipation is difficult and the like can be caused by the overlarge power consumption.
In a first aspect, as shown in fig. 2, the present application provides a field programmable gate array device 200, which includes: a memory 210, the memory 210 including a power down signal port A1 and a sleep signal port A2; the memory 210 controls the operating state of the memory according to the control signal received by the power-down signal port A1 and the control signal received by the sleep signal port A2.
In the embodiment of the present application, the control signal received by the power-off signal port a1 may be a power-off signal; the control signal received by sleep signal port a2 may be a sleep signal.
In an alternative embodiment of the present application, the memory 210 includes a power control module 230, a sleep control module 240, a storage module 220, and a read/write control circuit 250; the power control module 230 is provided with a power-off signal port A1, and the sleep control module 240 is provided with a sleep signal port A2; the power control module 230, the sleep control module 240 and the read/write control circuit 250 are electrically connected to the memory module 220, respectively.
Correspondingly, as shown in fig. 3, the present application provides a memory power control method 300 for a field programmable gate array device, where the method 300 is applied to the field programmable gate array device 200 of any one of the first aspect, and the method includes:
step 301, a control signal received through a power down signal port on the memory and a sleep signal port on the memory.
And step 302, controlling the working state of the memory according to the type of the received control signal.
In an alternative embodiment of the present application,
controlling the operating state of the memory according to the type of the received control signal, including:
controlling to stop supplying power to the storage module according to the control signal received by the power supply control module through the power supply signal port;
and controlling the memory to be in a dormant state and stopping reading and writing operations by the dormant control module according to the control signal received by the dormant signal port.
In the embodiment of the present application, the control signal received by the power-off signal port a1 may be a power-off signal; the control signal received by sleep signal port a2 may be a sleep signal.
In the embodiment of the application, under the condition that the power-off signal is at a high level, the power supply of all circuits in the memory is closed, the content stored in the storage module is also destroyed, and the memory does not consume any electric quantity in the state. And under the condition that the power-off signal is at a low level, the power supply of all circuits in the memory is started, all functions of the memory are enabled, and the consumed electric quantity of the memory is the maximum under the state.
In the embodiment of the application, under the condition that the sleep signal is at a high level, the memory is in a sleep state, all functional circuits except the memory module which continues to supply power to save the stored data content are powered off, and the memory operates at low power consumption in the state. When the sleep signal is at a low level, the memory is in a non-sleep state, and other functional circuits except the memory module can also selectively continue to supply power, wherein the memory operates at high power consumption.
It is understood that in the field programmable gate array device 200 and the memory power control method 300 thereof disclosed in the first aspect, a power-off signal port a1 and a sleep signal port a2 are added to the memory 210, so that the memory 210 can flexibly switch among a low power consumption state (sleep state), a high power consumption state, a full-enabled state and a full-power-off state according to the power-off signal and the sleep signal. The memory 210 does not need to work in a full-enabled state all the time, so that the power consumption of the memory 210 in the field programmable gate array device is greatly reduced, and the problems that the field programmable gate array device is too high in working temperature and difficult to dissipate heat are further solved.
In a second aspect, as shown in fig. 4, the present application further provides another field programmable gate array device 400, and on the basis of the field programmable gate array device 200 disclosed in the first aspect, the field programmable gate array device 400 further includes: the code stream memory 600, the first selector 701 and the second selector 702 are configured.
The first selector 701 and the second selector 702 both include a high level input end and a low level input end, the gating ends of the first selector 701 and the second selector 702 are electrically connected with the configuration code stream memory 600, the output end of the first selector 701 is electrically connected with the power-off signal port, and the output end of the second selector 702 is electrically connected with the sleep signal port.
In an alternative embodiment of the present application, the field programmable gate array device further comprises a programmable logic module 800; the first selector 701 further comprises a first custom input, and the second selector 702 further comprises a second custom input; the first custom input and the second custom input are both electrically connected to the programmable logic module 800.
Correspondingly, as shown in fig. 5, the present application further provides another method 500 for controlling a memory power supply of a field programmable gate array device, where the method 500 is applied to the field programmable gate array device 400 of any one of the second aspects, and the method 500 further includes, on the basis of the method 300 of the first aspect:
step 501, three input ends of a first selector respectively receive a high level signal, a low level signal and a first self-defined signal, and three input ends of a second selector respectively receive a high level signal, a low level signal and a second self-defined signal.
Step 502, receiving a first selection signal configuration code stream sent by a configuration code stream storage through a first selector, and receiving a second selection signal configuration code stream sent by the configuration code stream storage through a second selector.
And 503, configuring the code stream through the first selection signal to output a power-off signal, and configuring the code stream through the second selection signal to output a sleep signal.
In an optional embodiment of the present application, configuring a code stream to output a power-off signal according to a first selection signal through a first selector, including: selecting one signal from a high level signal, a low level signal and a first user-defined signal as a power-off signal according to a first selection signal configuration code stream through a first selector; configuring a code stream to output a sleep signal according to a second selection signal through a second selector, comprising: and selecting one signal from the high level signal, the low level signal and the second user-defined signal as a sleep signal through the second selector according to the second selection signal configuration code stream.
In an alternative embodiment of the present application, the programmable logic module 800 is electrically connected to the configuration code stream memory 600, and the programmable logic module 800 is electrically connected to the memory through a signal line, where the signal line may enable a signal line, read/write an address line, a data line, and the like.
Correspondingly, the method further comprises the following steps: receiving a custom configuration code stream sent from the configuration code stream memory 600 through the programmable logic module 800; outputting a first custom signal to the first selector 701 according to the custom configuration code stream through the programmable logic module 800; the second self-defined signal is output to the second selector 702 through the programmable logic module 800 according to the self-defined configuration code stream.
It will be appreciated that the user can perform dynamic control of the memory power supply according to his own logic. The programmable logic module 800 may perform configuration according to a custom configuration code stream output by the configuration code stream memory 600, and output a first custom signal as a user-defined for the power-off signal, that is, the user may control a time period when the memory is in a full-enabled operating state and a full-power-off operating state through the first custom signal. The programmable logic module 800 may perform configuration according to the custom configuration code stream output by the configuration code stream memory 600, and output a second custom signal as a user-defined for the sleep signal, that is, the user may control a time period when the memory is in the sleep state and the high power consumption working state through the second custom signal.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. Especially, as for the device, apparatus and medium type embodiments, since they are basically similar to the method embodiments, the description is simple, and the related points may refer to part of the description of the method embodiments, which is not repeated here.
Thus, particular embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may be advantageous.
The expressions "first", "second", "said first" or "said second" used in various embodiments of the present disclosure may modify various components regardless of order and/or importance, but these expressions do not limit the respective components. The above description is only configured for the purpose of distinguishing elements from other elements. For example, the first user equipment and the second user equipment represent different user equipment, although both are user equipment. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
When an element (e.g., a first element) is referred to as being "operably or communicatively coupled" or "connected" (operably or communicatively) to "another element (e.g., a second element) or" connected "to another element (e.g., a second element), it is understood that the element is directly connected to the other element or the element is indirectly connected to the other element via yet another element (e.g., a third element). In contrast, it is understood that when an element (e.g., a first element) is referred to as being "directly connected" or "directly coupled" to another element (a second element), no element (e.g., a third element) is interposed therebetween.
The above description is only an alternative embodiment of the application and is illustrative of the technical principles applied. It will be appreciated by those skilled in the art that the scope of the invention herein disclosed is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the spirit of the invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A field programmable gate array device, comprising:
the memorizer comprises a power-off signal port and a sleep signal port, and the memorizer respectively controls the working state of the memorizer according to control signals received by the power-off signal port and the sleep signal port.
2. The field programmable gate array device of claim 1, further comprising a configuration codestream memory, a first selector, and a second selector;
the first selector and the second selector both comprise a high-level input end and a low-level input end, the gating ends of the first selector and the second selector are electrically connected with the configuration code stream storage, the output end of the first selector is electrically connected with the power-off signal port, and the output end of the second selector is electrically connected with the sleep signal port.
3. The field programmable gate array device of claim 2, further comprising a programmable logic module;
the first selector further comprises a first custom input end, and the second selector further comprises a second custom input end;
the first user-defined input end and the second user-defined input end are electrically connected with the programmable logic module.
4. The field programmable gate array device of claim 3,
the programmable logic module is electrically connected with the configuration code stream memory and is electrically connected with the memory through a signal line.
5. The field programmable gate array device of any one of claims 1 to 4,
the memory comprises a power supply control module, a dormancy control module, a storage module and a read-write control circuit; the power supply control module is provided with the power-off signal port, and the dormancy control module is provided with the dormancy signal port;
the power supply control module, the dormancy control module and the read-write control circuit are connected with the storage module.
6. A memory power control method of a field programmable gate array device, the method being applied to the field programmable gate array device according to any one of claims 1 to 5, the method comprising:
respectively receiving control signals through a power-off signal port and a sleep signal port on the memory;
and controlling the working state of the memory according to the type of the received control signal.
7. The method of claim 6, further comprising:
receiving a first selection signal configuration code stream sent by the configuration code stream storage through the first selector, and receiving a second selection signal configuration code stream sent by the configuration code stream storage through the second selector;
and configuring a code stream through the first selection signal to output a power-off signal, and configuring the code stream through the second selection signal to output a sleep signal.
8. The method of claim 7, wherein configuring the code stream to output a power-off signal via the first selection signal and configuring the code stream to output a sleep signal via the second selection signal comprises:
selecting one signal from high level signals, low level signals and first self-defined signals received from three input ends of the first selector by the first selector according to the first selection signal configuration code stream;
and configuring a code stream through the second selection signal to select one signal from high level signals, low level signals and second self-defined signals received from three input ends of the second selector as the sleep signal.
9. The method of claim 8, further comprising:
receiving a user-defined configuration code stream output from the configuration code stream memory through the programmable logic module;
outputting the first self-defined signal to the first selector through the self-defined configuration code stream;
and outputting the second self-defined signal to the second selector through the self-defined configuration code stream.
10. The method for controlling the power supply of the memory of the field programmable gate array device according to any one of claims 6 to 9, wherein the controlling the operating state of the memory according to the type of the received control signal comprises:
controlling to stop supplying power to the storage module according to the control signal received by the power supply control module through the power supply signal port;
and controlling the memory to be in a dormant state and stopping reading and writing operations by the dormant control module according to the control signal received by the dormant signal port.
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| CN108983945A (en) * | 2017-06-05 | 2018-12-11 | 美国莱迪思半导体公司 | The selective power gating of interconnection resource configuration bit for programmable logic device |
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| CN112597096A (en) * | 2020-12-15 | 2021-04-02 | 中国科学院计算技术研究所 | Low-power-consumption FPGA (field programmable Gate array) partial reconfigurable method and device |
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