CN113328753A

CN113328753A - Switch selection circuit, digital-analog conversion circuit and source electrode drive circuit

Info

Publication number: CN113328753A
Application number: CN202110799467.7A
Authority: CN
Inventors: 张孝珩; 吴佳璋
Original assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Priority date: 2021-07-15
Filing date: 2021-07-15
Publication date: 2021-08-31

Abstract

The present disclosure provides a switch selection circuit, a digital-to-analog conversion circuit and a source driving circuit. The switch selection circuit is configured to receive a plurality of input signals and selection signals and output a first signal and a second signal different from the first signal according to the selection signals and the input signals, wherein the switch selection circuit includes a plurality of selection modules, the first the group selection module includes at least two selection modules of the plurality of selection modules and is configured to select the first signal from the plurality of input signals according to the selection signal, the second group selection module includes at least two selection modules of the plurality of selection modules, and is configured to select the second signal from the plurality of input signals according to the selection signal, the first group of selection modules and the second group of selection modules share at least one selection module. Therefore, the number of switch circuits used in the switch selection circuit can be reduced without affecting the stability of the output voltage.

Description

Switch selection circuit, digital-analog conversion circuit and source electrode drive circuit

Technical Field

Embodiments of the present disclosure relate to a switch selection circuit, a digital-analog conversion circuit, and a source driver circuit.

Background

In the high-resolution source driving circuit, a Digital-to-Analog converter (DAC) is used to select a gray-scale Analog voltage output from a GAMMA (GAMMA) resistor and then transmit the selected voltage to an output port, thereby applying a data voltage to data lines in a display panel. With the improvement of the resolution, the number of transistors of the switch selection circuit used in the DAC circuit is inevitably increased, so that how to reduce the number of transistors of the switch selection circuit used in the DAC circuit without affecting the stability of the output voltage is a problem to be solved.

Disclosure of Invention

Embodiments of the present disclosure provide a switch selection circuit, a digital-to-analog conversion circuit, and a source driver circuit, so as to solve the problem in the prior art how to reduce the number of transistors used in the switch selection circuit on the premise of not affecting the stability of an output voltage.

At least one embodiment of the present disclosure provides a switch selection circuit configured to receive a plurality of input signals and a selection signal and output a first signal and a second signal different from the first signal according to the selection signal and the input signals, wherein the switch selection circuit includes a plurality of selection blocks, a first group of the selection blocks includes at least two selection blocks of the plurality of selection blocks and is configured to select a first signal from the plurality of input signals according to the selection signal, a second group of the selection blocks includes at least two selection blocks of the plurality of selection blocks and is configured to select a second signal from the plurality of input signals according to the selection signal, and the first group of the selection blocks and the second group of the selection blocks share at least one selection block.

For example, in a switch selection circuit provided in an embodiment of the present disclosure, the plurality of selection modules includes a plurality of first level selection modules and at least one second level selection module, and the plurality of first level selection modules are coupled to the at least one second level selection module; the selection signal comprises a first part byte and a second part byte, and the first part byte and the second part byte do not overlap with each other; the plurality of first-stage selection modules receive the plurality of input signals as a whole, and select the plurality of input signals according to the first part of bytes to generate a plurality of intermediate signals; the at least one second-level selection module receives the plurality of intermediate signals, and selects the plurality of intermediate signals according to the second part of bytes to respectively obtain the first signal and the second signal; wherein the plurality of first level selection modules belong to the first group of selection modules and/or the second group of selection modules; said at least one second level selection module belongs to said first group of selection modules and/or said second group of selection modules.

For example, in a switch selection circuit provided in an embodiment of the present disclosure, an output of the at least one selection block that is shared is coupled to two selection blocks of the plurality of selection blocks.

For example, in a switch selection circuit provided in an embodiment of the present disclosure, the at least one second level selection module includes a first second level selection module and a second level selection module, the plurality of intermediate signals includes a first group and a second group, and the first second level selection module receives the first group of the plurality of intermediate signals and obtains the first signal according to the second partial byte; the second level selection module receives a second set of the plurality of intermediate signals and obtains the second signal based on the second portion of bytes.

For example, in a switch selection circuit provided in an embodiment of the present disclosure, the first group selection module includes the plurality of first stage selection modules and the first second stage selection module; the second set of selection modules comprises the plurality of first level selection modules and the second level selection module; the first group of the plurality of intermediate signals and the second group of the plurality of intermediate signals comprise at least one common intermediate signal, and the at least one selection module common to the first group selection module and the second group selection module comprises at least one first level selection module generating the at least one common intermediate signal.

For example, in the switch selection circuit provided in an embodiment of the present disclosure, the first part of bytes is an upper byte (MSB), the second part of bytes is a lower byte (LSB), and the selection signal is composed of the upper byte (MSB) and the lower byte (LSB).

For example, in the switch selection circuit provided in an embodiment of the present disclosure, the number of the upper bits (MSB) is equal to or different from the number of the lower bits (LSB).

For example, in the switch selection circuit provided in an embodiment of the present disclosure, each of the plurality of first-stage selection modules selects one selection module for N, the at least one second-stage selection module selects one selection module for M, the number of bits of the first part of bytes of the selection signal is N, and N ^ 2^ N; the bit number of the second part of bytes of the selection signal is M, and M is 2^ M; wherein n and m are both positive integers.

For example, in a switch selection circuit provided in an embodiment of the present disclosure, at least two of the plurality of first-stage selection modules receive input signals that are partially identical.

For example, in a switch selection circuit provided in an embodiment of the present disclosure, the first and second groups of the plurality of intermediate signals include at least one common intermediate signal.

For example, in the switch selection circuit provided in an embodiment of the present disclosure, the number of input signals of the first stage selection module is different from the number of input signals of the second stage selection module, where M is₁Selecting the number of input signals of the module for said first stage, M₂For the number of input signals of the second stage selection module, M₁And said M₂If the number of the selection modules in the switch selection circuit is a positive integer, the number of the selection modules in the switch selection circuit is M₂+3。

At least one embodiment of the present disclosure provides a digital-to-analog conversion circuit, including: the switch selection circuit, the arithmetic circuit, and the reference signal generation circuit described in the above embodiments, the reference signal generation circuit being configured to supply the plurality of input signals to the switch selection circuit; wherein the switch selection circuit is coupled to the operational circuit, the switch selection circuit outputting a first signal and a second signal to the operational circuit according to the plurality of input signals and the selection signal; the arithmetic circuit generates an output signal based on the first signal, the second signal, and an additional selection signal.

For example, in a digital-to-analog conversion circuit provided in an embodiment of the present disclosure, the output signal is a result of performing a difference operation using a value of the first signal and a value of the second signal as two endpoints and a value of the additional selection signal as a parameter.

For example, in a digital-to-analog conversion circuit provided in an embodiment of the present disclosure, the reference signal generating circuit includes a gamma voltage generating circuit to generate a plurality of gray-scale voltages as the plurality of input signals, respectively.

At least one embodiment of the present disclosure provides a source driving circuit, including: the digital-analog conversion circuit and the input signal receiving circuit according to the above embodiments are configured to receive the selection signal and the additional selection signal and provide the selection signal and the additional selection signal to the digital-analog conversion circuit.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it should be apparent that the drawings described below only relate to some embodiments of the present disclosure and are not limiting on the present disclosure.

FIGS. 1A-1B are schematic diagrams of a switch selection circuit;

FIG. 1C is a schematic diagram of the generation of a target voltage based on the output voltage of the switch selection circuit of FIGS. 1A-1B;

fig. 2A is a schematic diagram of a switch selection circuit provided in at least one embodiment of the present disclosure;

fig. 2B is a schematic diagram of a specific example of a switch selection circuit provided by at least one embodiment of the present disclosure;

FIG. 3A is a schematic diagram of the number of transistors required for a switch selection circuit of the prior art provided by at least one embodiment of the present disclosure versus the number of transistors required for the switch selection circuit of the present disclosure and the number of DAC bits;

fig. 3B is a schematic diagram of a ratio of the number of transistors of the switch selection circuit of the present disclosure to the number of transistors of the switch selection circuit of the prior art provided by at least one embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a selection module provided in at least one embodiment of the present disclosure;

fig. 5 is a block diagram of a digital-to-analog conversion circuit provided by an embodiment of the present disclosure;

fig. 6 is a block diagram of a source driving circuit provided in an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

At least one embodiment of the present disclosure provides a switch selection circuit configured to receive a plurality of input signals and a selection signal and output a first signal and a second signal different from the first signal according to the selection signal and the input signals. The switch selection circuit comprises a plurality of selection modules, a first group of selection modules comprises at least two selection modules in the plurality of selection modules and is configured to select a first signal from a plurality of input signals according to a selection signal; the second set of selection modules includes at least two selection modules of the plurality of selection modules and is configured to select a second signal from the plurality of input signals according to the selection signal, the first set of selection modules sharing at least one selection module with the second set of selection modules.

At least one embodiment of the present disclosure provides a digital-to-analog conversion circuit, including: the switch selection circuit and the arithmetic circuit of the above embodiments. The switch selection circuit is coupled with the operational circuit and outputs a first signal and a second signal to the operational circuit according to a plurality of input signals and selection signals; the arithmetic circuit generates an output signal based on the first signal, the second signal, and the additional selection signal.

At least one embodiment of the present disclosure provides a source driving circuit, including: the digital-analog conversion circuit and the input signal receiving circuit according to the above embodiments are configured to generate the selection signal and the additional selection signal and supply the selection signal and the additional selection signal to the digital-analog conversion circuit.

The switch selection circuit, the digital-to-analog conversion circuit and the source driver circuit provided in the above embodiments of the present disclosure may reduce the size of the switch selection circuit (how many circuits are used) by sharing at least one selection module, for example, in at least one embodiment, partial sharing of the switch circuits (e.g., transistors) used to form the switch selection circuit may be implemented, so as to reduce the size of the switch selection circuit, and achieve the effect of saving the number of used switch circuits (e.g., transistors).

Embodiments of the present disclosure will be described below with reference to the accompanying drawings.

FIGS. 1A-1B show a schematic diagram of a switch selection circuit. Fig. 1A and 1B together form a switch selection circuit.

For the sake of easy viewing of the drawings, description will be made with reference to fig. 1A and 1B. The switch selection circuit comprises 10 selection modules, the selection modules K1-K4 in fig. 1A are all coupled with the selection module K5, similarly the selection modules K6-K9 in fig. 1B are all coupled with the selection module K0. These selection blocks are all 4-to-1 selection blocks (MUX4to1), i.e. 1 is selected as output from 4 input signals. Wherein, the input signals G0, G4, G8 and G12 are the input signals of the selection module K1, and the output of the selection module K1 is denoted as V0; the input signals G16, G20, G24 and G28 are input signals of the select block K2, and the output of the select block K2 is denoted as V1; the input signals G32, G36, G40 and G44 are input signals of the select block K3, and the output of the select block K3 is denoted as V2; the input signals G48, G52, G56 and G60 are input signals of the select block K4, and the output of the select block K4 is denoted as V3; the input signals G4, G8, G12 and G16 are input signals of the select block K6, and the output of the select block K6 is denoted as V4; the input signals G20, G24, G28 and G32 are input signals of the select block K7, and the output of the select block K7 is denoted as V5; the input signals G36, G40, G44 and G48 are input signals of the select block K8, and the output of the select block K8 is denoted as V6; the input signals G52, G56, G60 and G64 are input signals of the select block K9, and the output of the select block K9 is denoted as V7. The input signals G0-G64 are, for example, reference signals, such as gray scale voltage signals, for example, analog voltage signals corresponding to gray scales of 0-64, respectively.

V0, V1, V2 and V3 are input signals of the selection block K5, and the output of the selection block K5 is VL; v4, V5, V6, and V7 are input signals of the select block K0, and the output of the select block K0 is VH.

The selection modules K1-K4 and K6-K9 also receive the selection signals D2 and D3 and their inverse values D2B and D3B, and the selection modules K1-K4 and K6-K9 select the input signals according to these 4 selection signals. The selection blocks K5 and K0 also receive selection signals D4 and D5 and their inverse values D4B and D5B, and the selection blocks K5 and K0 select the input signals according to these 4 selection signals.

TABLE 1

Table 1 is a truth table for the switch selection circuit shown in fig. 1A and 1B. In table 1, D5, D4, D3, and D2 are control signals (not shown in the figure) of a selection block in the switch selection circuit, which control the on or off of a switching element (e.g., a transistor) in the selection block. VH and VL are 2 output voltages, respectively, which are G4-G64 and G0-G60 in Table 1. As described above, G0-G64 are input signals (e.g., input voltage signals, such as reference voltage signals) that are input to the switch selection circuit. D5-D2 select VH and VL of the final output by controlling the transistors. The control signals include a high byte (MSB) and a low byte (LSB), for example, D4 and D5 are MSBs and D2 and D3 are LSBs.

Fig. 1C is a schematic diagram of generating a target voltage based on an output voltage of the switch selection circuit of fig. 1A-1B.

In fig. 1C, the output voltages of the switch selection circuits are VH and VL, and are input to an operational circuit such as an operational amplifier, which also generates the target voltage Vout in accordance with additional selection signals D1 and D0. The operation circuit in fig. 1C can be referred to as an operation circuit in the prior art, and is not limited herein.

First, the switch selection circuit in fig. 1A and 1B is applied to a 4+ 2-bit resistor string digital-to-analog conversion circuit as an example, for example, the analog conversion circuit converts an input 6-bit (i.e., 4+ 2-bit) digital signal into a corresponding gray scale voltage signal. More specifically, the description is made in conjunction with table 1. In the 4+ 2-bit R-DAC, each gray scale voltage is represented by 6 bits, of which 6 bits, the upper 4 bits are D5-D2 and the lower 2 bits are D1D0, and as a whole, each gray scale voltage is represented by D5D4D3D2D1D0, and D1D0 is used to further divide the output voltages VH and VL determined by D5D4D3D2 as described above, thereby obtaining a finer output voltage. The division operation is, for example, an interpolation operation.

For example, when D1D0 is 00, 01, 10, and 11, that is, gray scale voltages are expressed as (D5D4D3D2)00, (D5D4D3D2)01, (D5D4D3D2)10, and (D5D4D3D2)11, respectively, the corresponding voltage values are obtained by quartering (that is, three nodes) the voltage intervals defined by the output voltages VH and VL corresponding to D5D4D3D2, that is, specific voltage values are VL, VL + (VH-VL)/4, VL + (VH-VL)/2, VL +3 (VH-VL)/4, and VH, respectively. For example, interpolation operations performed by G0 and G4 can result in G0, G1, G2, G3, and G4, respectively, corresponding to gray levels of 0, 1, 2, 3, and 4; similarly, interpolation operations performed by G4 and G8 can yield G4, G5, G6, G7, and G8, respectively, corresponding to gray levels of 4, 5, 6, 7, and 8.

As shown in table 1, when the MSB (D4 and D5) is in the same state, VH and VL repeat, for example, when D5 is 1 and D4 is 0, values of VH and VL such as G36, G40, and G44 repeat. Therefore, each output (VH or VL) needs 5 selection modules to be realized, and the selection modules corresponding to each output cannot be shared.

When the selection blocks are formed using transistors (e.g., field effect transistors or thin film transistors), different types of selection blocks are implemented using different numbers of transistors.

Table 2 gives the correspondence of the type of selection module to the number of transistors required by the selection module. The correspondence satisfies the formula M-2 n-2, n corresponding to the type of the selection module, and M being the required number of transistors. It should be noted that table 2 only gives examples of n being 2, 4, 8, or 16, and n may be other positive integers. A total of 10 × 6 to 60 transistors are required for the switch selection circuits shown in fig. 1A and 1B.

TABLE 2

Selecting a type of module	Number of transistors required
		2 to1	2
1 from 4	6
		1 from 8	14
1 in 16 options	30

Fig. 2A illustrates a block diagram of a switch selection circuit provided by at least one embodiment of the present disclosure.

In fig. 2A, the switch selection circuit 20 is configured to receive a plurality of input signals and a selection signal and output a first signal and a second signal different from the first signal according to the selection signal and the input signals. For example, the plurality of input signals are gray scale voltage signals, the selection signal is a part of the control signal, and the control signal is a digital signal.

As shown, the switch selection circuit 20 includes a plurality of selection modules, specifically including a selection module 200, selection modules 201 and … …, a selection module 20(n-1), a selection module 20n, a selection module 210, and a selection module 211, where n is a positive integer.

The plurality of selection modules can be divided into a first group of selection modules and a second group of selection modules; the first group of selection modules comprises at least two selection modules in the plurality of selection modules and is configured to select a first signal from the plurality of input signals according to a selection signal; the second set of selection modules includes at least two selection modules of the plurality of selection modules and is configured to select a second signal from the plurality of input signals according to the selection signal. The first group of selection modules shares at least one selection module with the second group of selection modules.

As shown in FIG. 2A, the first set of selection blocks is shown surrounded by dashed lines and includes selection blocks 200-20(n-1) and selection block 210, the output of selection block 200-20(n-1) is provided to selection block 210, and selection block 210 selects the output of the first signal, here signal VL. Similarly, although the second set of selection modules is not explicitly shown in the figure, it will be appreciated that the second set of selection modules includes selection modules 201-20n and selection module 211, the outputs of selection modules 201-20n are provided to selection module 211, and selection module 211 selects the output of the second signal, here signal VH. Here, the first group selection block and the second group selection block share, for example, the selection block 201-20 (n-1).

For example, in the switch selection circuit 20, the plurality of selection blocks includes a plurality of first level selection blocks and at least one second level selection block, and the plurality of first level selection blocks are coupled with the at least one second level selection block. In one example, the plurality of selection modules may be divided into a first level selection module and a second level selection module according to a source of the received input signal or a corresponding selection signal.

As shown in FIG. 2A, selection modules 200-20n are first level selection modules, and selection modules 210 and 211 are second level selection modules. Here, the first stage selection module directly receives an input signal, i.e., an input signal external to the switch selection circuit 20; the second level selection module receives the selection output of the first level selection module.

The selection signal input to the selection circuit 20 includes a plurality of bytes, for example, a first partial byte and a second partial byte, where the first partial byte and the second partial byte do not overlap each other. As shown in FIG. 2A, according to the control of the first part of the selection signal, the output of the selection block 200 is V0, the outputs of the selection block 201 are V1, … …, the output of the selection block 20(n-1) is Vn-1, and the output of the selection block 20n is Vn. The selection block 210 is coupled to the selection block 200-the selection block 20(n-1) and has an input signal V0-Vn-1. The selection module 211 is coupled to the selection modules 201-20n and has input signals V1-Vn. The selection module 210 selects one of V0-Vn-1 as the VL output and the selection module 211 selects one of V1-Vn as the VH output, as controlled by the second portion of the selection signal.

It should be noted that the first part of the selection signal in fig. 2A is the first part of the byte of the selection signal, and the second part of the selection signal is the second part of the byte of the selection signal. Optionally, the first part of bytes is a high-order byte (MSB), the second part of bytes is a low-order byte (LSB), and the selection signal is composed of the high-order byte (MSB) and the low-order byte (LSB).

Similarly, the resulting output signal VH and output signal VL are used, for example, for further operations to obtain an output voltage, which will be described in more detail below.

Fig. 2B is a schematic diagram of a specific example of a switch selection circuit provided in at least one embodiment of the present disclosure. Table 3 is an example of a truth table corresponding to the switch selection circuit 20 shown in fig. 2B.

The specific example takes the case where the number of bits of the selection signal is 4 and each selection module is a 4-to-1 selection module, and the switch selection circuit 20' includes a selection module K10, a selection module K11, a selection module K12, a selection module K13, a selection module K14, a selection module K20, and a selection module K21. The selection modules K10-K13 are respectively coupled with the selection module K20, and the selection modules K11-K14 are respectively coupled with the selection module K21. It should be noted that fig. 2B is only an example, and the switch selection circuit 20' may include 5 or more selection modules. The input signals to the selection blocks K10-K14 are voltages, such as gray scale voltages, from outside the switch selection circuit 20'. The input signals of the selection modules K20 and K21 are voltages output from other selection modules in the switch selection circuit 20', for example, the input signal of the selection module K20 is the voltage output from the selection modules K10-K13, and the input signal of the selection module K21 is the voltage output from the selection modules K11-K14. The outputs of the selection modules K20 and K21 are the output voltages VL and VH, for example, of the selection modules K20 and K21 as inputs to one operational circuit.

Correspondingly, in the example shown in FIG. 2B, the first set of selection modules includes selection modules K10-K13 and K20, and the second set of selection modules includes selection modules K11-K14 and K21. The first group of selection modules and the second group of selection modules share the selection modules K11-K13.

More specifically, as shown in fig. 2B, the switch selection circuit 20' includes 7 selection blocks each of which is a 1-out-of-4 selection block. The switch selection circuit corresponds to table 3 below, in which input signals of the selection module K10 are G0, G16, G32, and G48, input signals of the selection module K11 are G4, G20, G36, and G52, input signals of the selection module K12 are G8, G24, G40, and G56, input signals of the selection module K13 are G12, G28, G44, and G60, and input signals of the selection module K14 are G16, G32, G48, and G64. Similarly, for example, G0-G64 are gray scale voltage signals, such as analog voltage signals corresponding to gray scales of 0-64, respectively.

The output of the select block K10 is denoted as V0, the output of the select block K11 is denoted as V1, the output of the select block K12 is denoted as V2, the output of the select block K13 is denoted as V3, and the output of the select block K14 is denoted as V4. The input signals of the selection module K20 are V0-V3, and the output is VL. The input signals of the selection module K21 are V1-V4, and the output is VH.

Here, the select signal includes 4 bytes, where the first part of bytes are D4 and D5 as the upper byte MSB, and the second part of bytes are D2 and D3 as the lower byte LSB.

D4 and D5 and their inversed values D4B and D5B are selection signals for selecting modules K10-K14, and D3 and D2 and their inversed values D2B and D3B are selection signals for selecting modules K20 and K21. For example, when D3D2D5D4 is 0101 (i.e., D5D4D3D2 is 0101), the selection modules K10, K11, K12, K13, and K14 respectively select G16, G20, G24, G28, and G32 as V0, V1, V2, V3, and V4 to be output to the selection module K20 and the selection module K21, according to the first portion D4D5 of the selection signal being 10. The selection modules K20 and K21 select V1 as VL output and V2 as VH output, respectively, according to the second portion D2D3 of the selection signal being 10.

TABLE 3

D3	D2	D5	D4	VH	VL
						0	0	0	0	G4	G0
0	0	0	1	G20	G16
						0	0	1	0	G36	G32
0	0	1	1	G52	G48
						0	1	0	0	G8	G4
0	1	0	1	G24	G20
						0	1	1	0	G40	G36
0	1	1	1	G56	G52
						1	0	0	0	G12	G8
1	0	0	1	G28	G24
						1	0	1	0	G44	G40
1	0	1	1	G60	G56
						1	1	0	0	G16	G12
1	1	0	1	G32	G28
						1	1	1	0	G48	G44
1	1	1	1	G64	G60

It should be noted that, in this embodiment, the dividing manners for the first-level selection module and the second-level selection module, and the dividing manners for the first-group selection module and the second-group selection module do not conflict. The plurality of first level selection modules may belong to the first group of selection modules and/or the second group of selection modules. At least one second level selection module belongs to the first group of selection modules and/or the second group of selection modules. For example, in fig. 2A, the first group of selection modules in the switch selection circuit 20 includes selection modules 200-20(n-1) and 210, and the second group of selection modules includes selection modules 201-20n and 211, where the selection modules 201-20(n-1) belong to both the first group of selection modules and the second group of selection modules, the selection module 200 only belongs to the first group of selection modules, and the selection module 20n only belongs to the second group of selection modules.

The selection modules 200-20n collectively receive a plurality of input signals (e.g., 16 signals in the example shown in fig. 2B, receiving G0-G64), but there is no limitation as to which input signals (e.g., 2, 4, 8, or 16) of the plurality of input signals each selection module actually receives. The selection modules 200-20n select the plurality of input signals based on the first portion of bytes to generate a plurality of intermediate signals. The at least one second-stage selection module receives the plurality of intermediate signals, and the at least one second-stage selection module selects the plurality of intermediate signals according to the second part of bytes to respectively obtain the first signal and the second signal. For example, in the example shown in FIG. 2B, select blocks K10-K14 generate intermediate signals V0-V4 based on select signals D5 and D4. For example, in the example shown in fig. 2B, the selection modules K20 and K21 acquire VL and VH as the first signal and the second signal according to the selection signals D3 and D2.

Optionally, the output of the at least one selection module that is shared is coupled to two selection modules of the plurality of selection modules. For example, in FIG. 2A, shared selection modules 201-20(n-1) are coupled to selection modules 210 and 211, respectively.

Optionally, the at least one second-level selection module includes a first second-level selection module and a second-level selection module, the plurality of intermediate signals includes a first group and a second group, and the first second-level selection module receives the first group of the plurality of intermediate signals and obtains the first signal according to the second partial byte; the second level selection module receives a second set of the plurality of intermediate signals and obtains a second signal based on the second portion of bytes. For example, as shown in FIG. 2A, the selection module 210 receives a first set of intermediate signals V0-Vn-1 and then selects an output among the first set of intermediate signals as VL; the selection module 211 receives the second set of intermediate signals V1-V4 and then selects an output among the second set of intermediate signals as VH. In the example shown in FIG. 2B, the selection module K20 receives the intermediate signals V0-V3 and selects one of the V0-V3 signals, VL, based on D2 and D3 as the first signal output; the selection module K21 receives the intermediate signals V1-V4 and selects one of the V1-V4 outputs, i.e., VH, based on D2 and D3 as the second signal output.

Optionally, the first group selection module comprises a plurality of first level selection modules and a first second level selection module; the second group of selection modules comprises a plurality of first-level selection modules and second-level selection modules; the first group of the plurality of intermediate signals and the second group of the plurality of intermediate signals comprise at least one common intermediate signal; the at least one selection module common to the first and second sets of selection modules comprises at least one first level selection module generating at least one common intermediate signal. As shown in FIG. 2A, the common intermediate signal is V1-Vn-1, which is shared by the selection module 210 and 211; for example, in the example shown in FIG. 2B, there are 3 common intermediate signals, V1-V3, shared by the select modules K20-K21.

Further, as shown in table 3, by prepending the MSB, there is no overlapping value of the output voltages VH and VL when the state of the LSB is the same. However, when the LSB states are different, there are a plurality of sets of VL and VH which take exactly the same value. For example, where D3 is 0 and D2 is 0, values of VH include G4, G20, G36, and G52. When D3 is 0 and D2 is 1, values of VL also include G4, G20, G36, and G52. In this embodiment, since the selection blocks that obtain the same VL and VH values are present in different LSB states, these selection blocks can be shared between the two paths VL and VH. The size of the switch selection circuit 20 is reduced compared to the size of the switch selection circuit shown in fig. 1A-1B due to the sharing of the selection modules, and in the case that the switch modules are formed of transistors, the number of transistors required by the switch selection circuit 20 is greatly reduced compared to the switch selection circuit shown in fig. 1A-1B. For example, the switch selection circuit shown in fig. 1A-1B requires 10 4-to-1 selection modules, i.e., 60 transistors, to output VL and VH, while the switch selection circuit 20' shown in fig. 2B requires only 7 4-to-1 selection modules, i.e., 42 transistors, to complete the same VL and VH outputs.

Fig. 3A shows a relationship diagram of the number of transistors required by the switch selection circuit using the 4-from-1 selection module in the prior art, such as fig. 1A-1B and similar architectures, and the number of DAC bits (the number of bits of the selection signal input to the DAC) provided by the embodiment of the present disclosure. Fig. 3B is a diagram illustrating a ratio of the number of transistors required by the switch selection circuit provided in the embodiment of the present disclosure to the number of transistors required by the switch selection circuit in the related art, corresponding to fig. 3A.

In fig. 3A, when the number of bits of the DAC is 3 bits (bit), the switch selection circuit of the related art requires 28 transistors, and the switch selection circuit of the embodiment of the present disclosure requires 22 transistors. When the bit number of the DAC is 7 bits, the switch selection circuit of the related art requires 508 transistors, and the switch selection circuit of the embodiment of the present disclosure requires 298 transistors. Fig. 3B is the ratio of the number of transistors required for the present disclosure to the number of transistors required for the prior art corresponding to fig. 3A.

As shown in fig. 3A and 3B, as the number of bits of the selection signal increases, the transistor growth speed of the switch selection circuit of the embodiment of the present disclosure is different from that of the transistor required in the prior art, and the transistor growth speed of the switch selection circuit of the embodiment of the present disclosure is significantly lower than that of the switch selection circuit of the prior art. And with the increase of the number of bits of the selection signal, the ratio of the number of transistors of the switch selection circuit of the embodiment of the disclosure to the number of transistors of the switch selection circuit of the prior art is reduced, that is, when the number of bits of the selection signal is large, a large number of transistors can be saved by using the switch selection circuit provided by the embodiment of the disclosure. For example, the number of transistors of the switch selection circuit in the related art is 4 × (2^ DAC bit number-1). When the DAC bit number is odd, the number of transistors of the switch selection circuit of the present disclosure is 2^ (DAC bit number +1) +3 ^ (2^ ((DAC bit number +1)/2) -2). When the DAC bit number is even, the number of transistors of the switch selection circuit of the present disclosure is 2^ (DAC bit number +1) +2^ (DAC bit number/2 +2) -6.

Further alternatively, for example, the number of upper bits (MSB) and the number of lower bits (LSB) of the selection signal input to the switch selection circuit may be equal or different.

For example, as shown in fig. 2B, for the switch selection circuit 20', the selection signal is 4 bytes, and the number of MSBs and the number of LSBs are both 2. As another example, in other examples, for example, when the selection signal is 6 bytes, the number of MSBs may be 4, and correspondingly the number of LSBs may be 2. In different embodiments of the present disclosure, the number of the selection modules, the number of the transistors, and the number of the selection signals are different according to the number of the input signals.

Table 4 gives a truth table for one example where the MSB is equal to the LSB, in this example the select signal comprises 6 bytes. The number of MSBs and LSBs in table 4 is 3.

TABLE 4

D4	D3	D2	D7	D6	D5	VH	VL	D4	D3	D2	D7	D6	D5	VH	VL
																0	0	0	0	0	0	G4	G0	1	0	0	0	0	0	G20	G16
0	0	0	0	0	1	G36	G32	1	0	0	0	0	1	G52	G48
																0	0	0	0	1	0	G68	G64	1	0	0	0	1	0	G84	G80
0	0	0	0	1	1	G100	G96	1	0	0	0	1	1	G116	G112
																0	0	0	1	0	0	G132	G128	1	0	0	1	0	0	G148	G144
0	0	0	1	0	1	G164	G160	1	0	0	1	0	1	G180	G176
																0	0	0	1	1	0	G196	G192	1	0	0	1	1	0	G212	G208
0	0	0	1	1	1	G228	G224	1	0	0	1	1	1	G244	G240
																0	0	1	0	0	0	G8	G4	1	0	1	0	0	0	G24	G20
0	0	1	0	0	1	G40	G36	1	0	1	0	0	1	G56	G52
																0	0	1	0	1	0	G72	G68	1	0	1	0	1	0	G88	G84
0	0	1	0	1	1	G104	G100	1	0	1	0	1	1	G120	G116
																0	0	1	1	0	0	G136	G132	1	0	1	1	0	0	G152	G148
0	0	1	1	0	1	G168	G164	1	0	1	1	0	1	G184	G180
																0	0	1	1	1	0	G200	G196	1	0	1	1	1	0	G216	G212
0	0	1	1	1	1	G232	G228	1	0	1	1	1	1	G248	G244
																0	1	0	0	0	0	G12	G8	1	1	0	0	0	0	G28	G24
0	1	0	0	0	1	G44	G40	1	1	0	0	0	1	G60	G56
																0	1	0	0	1	0	G76	G72	1	1	0	0	1	0	G92	G88
0	1	0	0	1	1	G108	G104	1	1	0	0	1	1	G124	G120
																0	1	0	1	0	0	G140	G136	1	1	0	1	0	0	G156	G152
0	1	0	1	0	1	G172	G168	1	1	0	1	0	1	G188	G184
																0	1	0	1	1	0	G204	G200	1	1	0	1	1	0	G220	G216
0	1	0	1	1	1	G236	G232	1	1	0	1	1	1	G252	G248
																0	1	1	0	0	0	G16	G12	1	1	1	0	0	0	G32	G28
0	1	1	0	0	1	G48	G44	1	1	1	0	0	1	G64	G60
																0	1	1	0	1	0	G80	G76	1	1	1	0	1	0	G96	G92
0	1	1	0	1	1	G112	G108	1	1	1	0	1	1	G128	G124
																0	1	1	1	0	0	G144	G140	1	1	1	1	0	0	G160	G156
0	1	1	1	0	1	G176	G172	1	1	1	1	0	1	G192	G188
																0	1	1	1	1	0	G208	G204	1	1	1	1	1	0	G224	G220
0	1	1	1	1	1	G240	G236	1	1	1	1	1	1	G256	G252

Corresponding to table 4, table 5 gives a truth table for an example when the MSB is not equal to the LSB, in which case the select signal still comprises 6 bytes. The number of MSBs in table 5 is 4 and the number of LSBs is 2.

TABLE 5

D3	D2	D7	D6	D5	D4	VH	VL	D3	D2	D7	D6	D5	D4	VH	VL
																0	0	0	0	0	0	G4	G0	1	0	0	0	0	0	G12	G8
0	0	0	0	0	1	G20	G16	1	0	0	0	0	1	G28	G24
																0	0	0	0	1	0	G36	G32	1	0	0	0	1	0	G44	G40
0	0	0	0	1	1	G52	G48	1	0	0	0	1	1	G60	G56
																0	0	0	1	0	0	G68	G64	1	0	0	1	0	0	G76	G72
0	0	0	1	0	1	G84	G80	1	0	0	1	0	1	G92	G88
																0	0	0	1	1	0	G100	G96	1	0	0	1	1	0	G108	G104
0	0	0	1	1	1	G116	G112	1	0	0	1	1	1	G124	G120
																0	0	1	0	0	0	G132	G128	1	0	1	0	0	0	G140	G136
0	0	1	0	0	1	G148	G144	1	0	1	0	0	1	G156	G152
																0	0	1	0	1	0	G164	G160	1	0	1	0	1	0	G172	G168
0	0	1	0	1	1	G180	G176	1	0	1	0	1	1	G188	G184
																0	0	1	1	0	0	G196	G192	1	0	1	1	0	0	G204	G200
0	0	1	1	0	1	G212	G208	1	0	1	1	0	1	G220	G216
																0	0	1	1	1	0	G228	G224	1	0	1	1	1	0	G236	G232
0	0	1	1	1	1	G244	G240	1	0	1	1	1	1	G252	G248
																0	1	0	0	0	0	G8	G4	1	1	0	0	0	0	G16	G12
0	1	0	0	0	1	G24	G20	1	1	0	0	0	1	G32	G28
																0	1	0	0	1	0	G40	G36	1	1	0	0	1	0	G48	G44
0	1	0	0	1	1	G56	G52	1	1	0	0	1	1	G64	G60
																0	1	0	1	0	0	G72	G68	1	1	0	1	0	0	G80	G76
0	1	0	1	0	1	G88	G84	1	1	0	1	0	1	G96	G92
																0	1	0	1	1	0	G104	G100	1	1	0	1	1	0	G112	G108
0	1	0	1	1	1	G120	G116	1	1	0	1	1	1	G128	G124
																0	1	1	0	0	0	G136	G132	1	1	1	0	0	0	G144	G140
0	1	1	0	0	1	G152	G148	1	1	1	0	0	1	G160	G156
																0	1	1	0	1	0	G168	G164	1	1	1	0	1	0	G176	G172
0	1	1	0	1	1	G184	G180	1	1	1	0	1	1	G192	G188
																0	1	1	1	0	0	G200	G196	1	1	1	1	0	0	G208	G204
0	1	1	1	0	1	G216	G212	1	1	1	1	0	1	G224	G220
																0	1	1	1	1	0	G232	G228	1	1	1	1	1	0	G240	G236
0	1	1	1	1	1	G248	G244	1	1	1	1	1	1	G256	G252

Both table 4 and table 5 can be used as truth tables of the switch selection circuit when the DAC bit number is 6 bits. When the number of MSBs and the number of LSBs are equal, it can be seen from table 4 that the difference between adjacent gray scale voltages of the circuit is large, but the number of transistors in this case is 154, and the number of transistors required is relatively small. The difference between the gray scale voltages corresponding to the adjacent gray scale voltages in table 5 is significantly smaller, and the required number of transistors is 162, which is slightly increased. Alternatively, the number of MSBs and LSBs may be flexibly adjusted when the number of bits of the DAC is constant, as long as the sum of the MSBs and LSBs is guaranteed to be equal to the number of bits of the DAC. For example, when the number of bits of the DAC is 4 bits, the following cases are included: LSB includes D2, MSB includes D3, D4 and D5; LSB includes D2 and D3, MSB includes D4 and D5; the LSB includes D2, D3, and D4, and the MSB includes D5. It should be noted that the DAC bit number in this disclosure refers to a bit number that does not include interpolation simplification.

When the switch state in the switch selection circuit is switched, there are cases where one transistor as the switch circuit is not turned off yet and the other transistor is turned on, and at this time, instantaneous leakage occurs, and adjacent gray-scale voltages interfere with each other with noise. And the larger the voltage difference between adjacent gray scales is, the more obvious the noise interference is. The first-level selection module needs the largest number of gray scale voltages to be selected, so that the problem of noise interference is the most serious. Therefore, the number of transistors and the adjacent gray-scale voltage difference can be controlled by adjusting the number of MSBs and LSBs, as shown in tables 4 and 5, for example, so that a balance is obtained between the number of transistors and circuit performance.

Table 6 gives several examples of the number of transistors required for the switch selection circuit in the prior art and the number of transistors required for the switch selection circuit in the present disclosure. T is the number of bits of the DAC, m is the number of MSBs, n is the number of LSBs, TR1 is the number of transistors required by the prior art switch selection circuit, TR2 is the number of transistors required by the switch selection circuit in this disclosure, and TR1-TR2 are the differences between the two.

TABLE 6

t	m	n	TR1	TR2	TR1-TR2
						4	3	1	60	46	14
4	2	2	60	42	18
						5	4	1	124	94	30
5	3	2	124	82	42
						6	5	1	252	190	62
6	4	2	252	162	90
						6	3	3	252	154	98

As shown in table 6, the number of MSBs and LSBs can be set according to actual requirements, thereby flexibly taking a trade-off between the number of transistors and reducing noise interference.

With continuing reference to the embodiment shown in FIG. 2A, optionally, each of the plurality of first level selection modules selects one selection module for N, the at least one second level selection module selects one selection module for M, the number of bits of the first portion of bytes of the selection signal is N, and N is 2^ N; selecting the bit number of the second part of bytes of the signal as M, wherein M is 2^ M; wherein n and m are both positive integers.

Optionally, at least two of the plurality of first level selection modules receive input signals that are partially identical. For example, only a portion of the signals received by the selection module 210 and the selection module 211 are the same.

Optionally, the first and second sets of the plurality of intermediate signals comprise at least one common intermediate signal. For example, the intermediate signals V1 and V3 are included in both the first and second groups.

Optionally, the number of input signals of the first stage selection module is different from the number of input signals of the second stage selection module, wherein M₁Selecting the number of input signals of the module for the first stage, M₂For the number of input signals of the second stage selection module, M₁And M₂Is a positive integer, the number of the selection modules in the switch selection circuit is M₂+3. For example, in the example shown in fig. 2B, the number of input signals of each of the first-stage selection blocks in the switch selection circuit 20' is 4, the number of input signals of each of the second-stage selection blocks is 4, and the total number of selection blocks is 7. For another example, in other examples, if the number of input signals of the first stage selection module in the switch selection circuit is 4, and the number of input signals of the second stage selection module is 8, then the number of selection modules is 11.

Fig. 4 shows a schematic diagram of a selection module provided by an embodiment of the present disclosure. As shown in fig. 4, the selection module 40 is a 1-out-of-4 selection module, and includes 6 transistors. The input signals are Vin0-Vin4, the selection signals are S0 and S1, and the output is Vout. The selection signal S0 and its inverse S0B control 2 transistors, respectively, to enable a first selection of 4 input signals. The exemplary construction of other types of selection modules, such as 2-from-1 selection, 8-from-1 selection modules, is not repeated, as is known in the art.

At least one embodiment of the present disclosure provides a digital-to-analog conversion circuit (or a numerical-to-analog converter) for converting a digital signal into a corresponding analog voltage signal, the digital-to-analog conversion circuit including the switch selection circuit, the arithmetic circuit, and the reference signal generation circuit of any of the above embodiments, the reference signal generation circuit configured to provide a plurality of input signals to the switch selection circuit. The switch selection circuit is coupled with the operational circuit and outputs a first signal and a second signal to the operational circuit according to a plurality of input signals and selection signals; the arithmetic circuit generates an output signal based on the first signal, the second signal, and the additional selection signal.

Fig. 5 is a block diagram of a digital-to-analog conversion circuit according to at least one embodiment of the disclosure. The digital-analog conversion circuit 50 includes a switch selection circuit 510, an arithmetic circuit 520, and a reference signal generation circuit 530. The switch selection circuit 510 is, for example, the switch selection circuit described above with reference to fig. 2A-2B. The reference signal generating circuit 530 provides a plurality of input signals, such as a plurality of reference voltage signals, such as the gray scale voltages referred to in tables 1-5 above; the switch selection circuit 510 outputs the first signal VL and the second signal VH to the arithmetic circuit 520 based on a plurality of input signals and a selection signal. The arithmetic circuit 520 generates an output signal, i.e., a resultant analog voltage signal, based on VL, VH and the additional selection signal. The converted digital signal comprises the selection signal as well as the additional selection signal.

Optionally, the output signal is a result of performing a difference operation using the value of the first signal and the value of the second signal as two endpoints and the value of the additional selection signal as a parameter. For example, referring to fig. 1C, the operational circuit is an operational amplifier, so that the operational amplifier performs a difference operation with VH and VL of the inputs as two terminals and an additional selection signal as a parameter.

Alternatively, the reference signal generating circuit includes a Gamma voltage generating circuit (Gamma circuit) to generate a plurality of gray-scale voltages as the plurality of input signals, respectively. The gamma voltage generating circuit includes, for example, one or more resistor strings to generate, for example, a plurality of equal-voltage-difference reference voltage signals for generating gray scale voltage signals. Also for example, the Gamma voltage generation circuit includes a resistor network string, and thus the Gamma voltage generation circuit may be a programmable Gamma voltage generation circuit (P-Gamma circuit).

At least one embodiment of the present disclosure provides a source driving circuit, including: the digital-analog conversion circuit of the above embodiment, and the input signal receiving circuit configured to receive the digital signal and supply the digital signal to the digital-analog conversion circuit, the digital-analog conversion circuit obtains the selection signal and the additional selection signal using the digital signal, and converts the analog voltage signal corresponding to the digital signal. For example, the input signal receiving circuit 620 receives a data signal for display from, for example, a timing control circuit (T-con) of the display device.

Fig. 6 is a block diagram of a source driving circuit provided in an embodiment of the present disclosure. The source drive circuit 60 includes a digital-analog conversion circuit 610 and an input signal receiving circuit 620. The digital-analog conversion circuit 610 is, for example, a digital-analog conversion circuit 50 as shown in the figure. The input signal receiving circuit receives the digital signal, thereby obtaining a selection signal and an additional selection signal, so that the digital-analog conversion circuit 610 generates an output voltage signal according to the selection signal and the additional selection signal.

The source driving circuit of the embodiment of the present disclosure may be used, for example, in a display device, which may be, for example, a liquid crystal display device, an organic light emitting diode display device, an electronic paper display device, a plasma display device, or the like, and is configured to provide a data signal (analog voltage signal after digital-to-analog conversion) to a pixel unit through a data line in a display panel. The display device can be used for any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A switch selection circuit, characterized by being configured to receive a plurality of input signals and selection signals and to output a first signal and a second signal different from the first signal according to the selection signals and the input signals ,in,

The switch selection circuit includes a plurality of selection modules, a first set of selection modules includes at least two selection modules of the plurality of selection modules, and is configured to select a first selection module from the plurality of input signals according to the selection signal Signal,

The second set of selection modules includes at least two selection modules of the plurality of selection modules and is configured to select a second signal from the plurality of input signals based on the selection signal,

The first group of selection modules and the second group of selection modules share at least one selection module.

2. The switch selection circuit of claim 1, wherein the plurality of selection modules comprise a plurality of first-level selection modules and at least one second-level selection module,

the plurality of first-level selection modules are coupled to the at least one second-level selection module;

the selection signal includes a first partial byte and a second partial byte, the first partial byte and the second partial byte do not overlap each other;

The plurality of first-level selection modules as a whole receive the plurality of input signals, select the plurality of input signals according to the first partial byte, and generate a plurality of intermediate signals;

The at least one second-level selection module receives the plurality of intermediate signals, and the at least one second-level selection module selects the plurality of intermediate signals according to the second partial byte to obtain the a first signal and the second signal;

Wherein, the plurality of first-level selection modules belong to the first group of selection modules and/or the second group of selection modules; the at least one second-level selection module belongs to the first group of selection modules and/or the second set of selection modules.

3. The switch selection circuit of claim 1 or 2, wherein the output of the at least one selection module that is shared is coupled to two selection modules of the plurality of selection modules.

4. The switch selection circuit of claim 2, wherein the at least one second stage selection module comprises a first second stage selection module and a second second stage selection module,

the plurality of intermediate signals includes a first group and a second group,

The first and second-level selection module receives the first group of the plurality of intermediate signals, and obtains the first signal according to the second partial byte;

The second second-level selection module receives the second group of the plurality of intermediate signals, and obtains the second signal according to the second partial byte.

5. The switch selection circuit of claim 4, wherein the first group of selection modules comprises the plurality of first-level selection modules and the first and second-level selection modules;

the second set of selection modules includes the plurality of first-level selection modules and the second second-level selection module;

the first group of the plurality of intermediate signals and the second group of the plurality of intermediate signals include at least one common intermediate signal,

The at least one selection module common to the first set of selection modules and the second set of selection modules includes at least one first-stage selection module that generates the at least one common intermediate signal.

6. The switch selection circuit according to claim 4 or 5, wherein the first partial byte is a high-order byte, the second partial byte is a low-order byte, and

The selection signal consists of the high-order byte and the low-order byte.

7 . The switch selection circuit of claim 6 , wherein the number of the high-order bytes and the number of the low-order bytes are equal or different. 8 .

8. The switch selection circuit according to claim 4 or 5, wherein each of the plurality of first-level selection modules is a selection module selected from N, and the at least one second-level selection module is selected from M select module,

The number of bits of the first partial byte of the selection signal is n, and N=2^n;

The number of bits of the second part of the byte of the selection signal is m, M=2^m;

where n and m are both positive integers.

9 . The switch selection circuit of claim 8 , wherein at least two of the plurality of first-stage selection modules receive partially the same input signal. 10 .

10. The switch selection circuit of claim 4 or 5, wherein the first and second groups of the plurality of intermediate signals comprise at least one common intermediate signal.

11. The switch selection circuit of claim 2, wherein the number of input signals of the first-stage selection module is different from the number of input signals of the second-stage selection module, wherein,

M ₁ is the number of input signals of the first-stage selection module,

M ₂ is the number of input signals of the second-stage selection module,

If the M ₁ and the M ₂ are positive integers, the number of selection modules in the switch selection circuit is M ₂ +3.

12. A digital-to-analog conversion circuit, characterized in that, comprising:

The switch selection circuit and the arithmetic circuit according to any one of claims 1-11,

a reference signal generation circuit configured to provide the plurality of input signals to the switch selection circuit;

Wherein, the switch selection circuit is coupled with the operation circuit,

The switch selection circuit outputs a first signal and a second signal to the operation circuit according to the plurality of input signals and the selection signal;

The arithmetic circuit generates an output signal based on the first signal, the second signal and the additional selection signal.

13. The digital-to-analog conversion circuit according to claim 12, wherein the output signal adopts the value of the first signal and the value of the second signal as two endpoints and the additional selection signal The value is the result of the difference operation on the parameter.

14 . The source driving circuit of claim 12 , wherein the reference signal generating circuit comprises a gamma voltage generating circuit to generate a plurality of gray-scale voltages as the plurality of input signals, respectively. 15 .

15. A source drive circuit, comprising:

The digital-to-analog conversion circuit of any of claims 12-14, and

An input signal receiving circuit configured to receive the selection signal and the additional selection signal and provide the selection signal and the additional selection signal to the digital-to-analog conversion circuit.