CN113328748B - Analog to digital conversion circuit - Google Patents

Abstract

The application provides an analog-to-digital conversion circuit, and relates to the technical field of circuits. Comprising the following steps: the system comprises a pipeline analog-digital converter formed by N stages of analog-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; if i is an integer smaller than N, the digital end of the ith analog-to-digital converter is electrically connected with the first detection input end of a detection circuit; the digital end of the (i+1) th stage analog-to-digital converter is electrically connected with the second detection input end of a detection circuit; a first detection output end of the detection circuit is electrically connected with a first calibration input end of a calibration circuit; the first calibration output end of a calibration circuit is electrically connected with the digital end of a first calibration voltage generation circuit; the analog end of the first calibration voltage generation circuit is electrically connected with the first input end of the comparator in the ith stage of analog-to-digital converter. The number of the calibration circuits is reduced, the calibration offset voltage is tracked in real time, and the processing speed of the analog-to-digital converter is improved.

Description

Analog to digital conversion circuit

Technical field

The present invention relates to the field of circuit technology, and in particular, to an analog-to-digital conversion circuit.

Background technique

The pipeline analog-to-digital converter is an analog-to-digital conversion structure that has the advantages of high speed and high precision. It is widely used in 5G (5th generation mobile networks, fifth generation mobile communication technology) and next-generation high-speed and high-capacity communication systems. Due to the asymmetry of the manufacturing process, offset voltage will be introduced and the conversion result will be inaccurate. Therefore, reducing the offset voltage is of great significance to the equipment pipeline analog-to-digital converter.

In the related art, a correction circuit is provided for each device in the pipeline analog-to-digital converter. For example, a correction circuit is provided for each analog-to-digital converter in the pipeline analog-to-digital converter. By connecting the comparator in the analog-to-digital converter The input port is short-circuited to achieve calibration.

However, in the related art, a correction circuit needs to be provided for each device, which requires a lot of correction circuits, requires extra time for short-circuiting, and also reduces the processing speed of the pipeline analog-to-digital converter.

Contents of the invention

The purpose of the present invention is to provide an analog-to-digital conversion circuit to solve the above-mentioned shortcomings in the prior art, so as to solve the problem that in related technologies, each device needs to be provided with a correction circuit, which requires many correction circuits and requires additional The short circuit also reduces the processing speed of the pipeline analog-to-digital converter.

In order to achieve the above objects, the technical solutions adopted in the embodiments of the present invention are as follows:

In a first aspect, embodiments of the present invention provide an analog-to-digital conversion circuit, including: a pipeline analog-to-digital converter composed of N-stage analog-to-digital converters, N-1 detection circuits, N-1 calibration circuits, and N-1 A first calibration voltage generating circuit; N is an integer greater than or equal to 2;

Among them, if i is an integer less than N, the digital terminal of the i-th stage analog-to-digital converter is electrically connected to the first detection input terminal of a detection circuit to output the i-th digital code; the digital terminal of the i+1-th stage analog-to-digital converter The terminal is electrically connected to the second detection input terminal of the one detection circuit to output the i+1th digital code, so that the one detection circuit outputs the ith digital code based on the ith digital code and the i+1th digital code. Voltage symbol detection value; the first detection output terminal of the one detection circuit is electrically connected to the first calibration input terminal of a calibration circuit, so that the one calibration circuit outputs the i-th voltage calibration code based on the i-th voltage symbol detection value ;

The first calibration output terminal of the one calibration circuit is electrically connected to the digital terminal of a first calibration voltage generation circuit, so that the one first calibration voltage generation circuit outputs the i-th calibration voltage signal based on the i-th voltage calibration code; The analog terminal of the first calibration voltage generating circuit is electrically connected to the first input terminal of the comparator in the i-th stage analog-to-digital converter, so that the comparator in the i-th stage analog-to-digital converter operates according to the The i calibration voltage signal and the corresponding input analog signal output the i-th target digital code.

Optionally, the analog-to-digital conversion circuit further includes: a second calibration voltage generating circuit;

The second detection output terminal of the N-1th detection circuit is electrically connected to the second calibration input terminal of the N-1th calibration circuit, so that the N-1th detection circuit is based on the output of the N-th stage analog-to-digital converter. The Nth digital code outputs the Nth voltage detection value;

The second calibration output terminal of the N-1th calibration circuit is electrically connected to the digital terminal of the second calibration voltage generation circuit, so that the N-1th calibration circuit outputs the Nth voltage detection value based on the N voltage calibration code, so that the second calibration voltage generation circuit outputs the Nth calibration voltage signal based on the Nth voltage calibration code;

The analog terminal of the second calibration voltage generating circuit is electrically connected to an input terminal of the comparator in the N-th stage analog-to-digital converter, so that the comparator in the N-th stage analog-to-digital converter is calibrated based on the N-th stage. The voltage signal and the corresponding input analog signal generate and output the Nth target digital code.

Optionally, the first calibration voltage generation circuit and the second calibration voltage generation circuit are calibration voltage generation circuits with the same structure. The calibration voltage generation circuit includes: a first switch array, M first resistors, M -1 second resistor and third resistor; where M is equal to the number of digits of the voltage calibration code;

Wherein, the first end of the M-1 second resistors connected in series is connected to the ground through the third resistor, and the second end connected in series is the analog end of the calibration voltage generating circuit;

The input terminal of the first switch array is the digital terminal of the calibration voltage generating circuit, the power terminal of the first switch array is electrically connected to the preset reference voltage; the M output terminals of the first switch array are electrically connected respectively One end of the M first resistors, and two ends of each of the M-1 second resistors are electrically connected to the other ends of the two first resistors respectively.

Optionally, the resistance of the first resistor is twice the resistance of the second resistor.

Optionally, the analog-to-digital conversion circuit also includes: N-1 amplifiers;

The margin output end of the i-th stage analog-to-digital converter is also electrically connected to the input end of an amplifier, and the output end of the one amplifier is also electrically connected to the analog end of the i+1-th stage analog-to-digital converter.

Optionally, each stage of the analog-to-digital converter includes: a comparator and a digital-to-analog converter, the second input terminal of the comparator is electrically connected to the analog terminal of each stage of the analog-to-digital converter, and the output terminal of the comparator is the digital end of each stage of the analog-to-digital converter;

The output end of the comparator is also electrically connected to the digital end of the digital-to-analog converter, and the analog end of the digital-to-analog converter is also electrically connected to the analog end of each stage of the analog-to-digital converter. The residual output of the digital converter.

Optionally, the digital-to-analog converter includes: a second switch array and a capacitor array; wherein the input terminal of the second switch array is the digital terminal of the digital-to-analog converter;

The plurality of output terminals of the second switch array are respectively electrically connected to one end of each capacitor in the capacitor array, and the other end of each capacitor in the capacitor array is an analog terminal of the digital-to-analog converter.

Optionally, each calibration circuit also has a trigger terminal; each calibration circuit is specifically configured to output a voltage calibration code according to the received voltage detection value when the trigger signal received by the trigger terminal is valid.

Optionally, each of the calibration circuits also has a restart terminal, and each of the calibration circuits is also configured to reset the output voltage calibration code to a preset code value when detecting that the restart signal input by the restart port is valid. ; When it is detected that the restart signal is invalid, and when the trigger signal is valid, output the voltage calibration code according to the received voltage detection value.

Optionally, each calibration circuit also has an enable terminal, and each calibration circuit is specifically configured to operate when the restart signal is invalid and the trigger signal is valid, and the enable signal input to the enable terminal When valid, the voltage calibration code is output based on the received voltage detection value.

The beneficial effects of the present invention are: the embodiment of the present application provides an analog-to-digital conversion circuit, including: a pipeline analog-to-digital converter composed of N-stage analog-to-digital converters, N-1 detection circuits, N-1 calibration circuits, and N -1 first calibration voltage generating circuit; N is an integer greater than or equal to 2; where, if i is an integer less than N, the digital terminal of the i-th stage analog-to-digital converter is electrically connected to the first detection input terminal of a detection circuit , to output the i-th digital code; the digital terminal of the i+1-th stage analog-to-digital converter is electrically connected to the second detection input terminal of a detection circuit to output the i+1-th digital code, so that a detection circuit is based on the i-th digital code and the i+1th digital code, outputting the i-th voltage symbol detection value; the first detection output terminal of a detection circuit is electrically connected to the first calibration input terminal of a calibration circuit, so that a calibration circuit outputs based on the i-th voltage symbol detection value The i-th voltage calibration code; a first calibration output terminal of a calibration circuit is electrically connected to a digital terminal of a first calibration voltage generation circuit, so that a first calibration voltage generation circuit outputs an i-th calibration voltage signal based on the i-th voltage calibration code; The analog terminal of a first calibration voltage generating circuit is electrically connected to the first input terminal of the comparator in the i-th stage analog-to-digital converter, so that the comparator in the i-th stage analog-to-digital converter is based on the i-th calibration voltage signal and the corresponding input The analog signal outputs the i-th target digital code. Only N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits need to be set up to realize the calibration of the pipeline analog-to-digital converter composed of N-stage analog-to-digital converters, reducing the number of The number of offset calibration circuits required. Moreover, the i-th voltage symbol detection value is generated based on the i-th digital code and the i+1-th digital code, the i-th voltage calibration code can be determined based on the i-th voltage symbol detection value, and the i-th voltage calibration code is determined in real time based on the i-th voltage calibration code. The i-calibrated voltage signal eliminates the need for additional time for short circuiting, improves the processing speed of the pipeline analog-to-digital converter, and enables real-time tracking and calibration of the offset voltage generated by the circuit.

Description of drawings

In order to explain the technical solutions of the embodiments of the present invention more clearly, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and therefore do not It should be regarded as a limitation of the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic structural diagram of an analog-to-digital conversion circuit provided by an embodiment of the present invention;

Figure 2 is a schematic structural diagram of an analog-to-digital conversion circuit provided by an embodiment of the present invention;

Figure 3 is a schematic structural diagram of a calibration voltage generation circuit provided by an embodiment of the present invention;

Figure 4 is a schematic structural diagram of an analog-to-digital conversion circuit provided by an embodiment of the present invention;

Figure 5 is a schematic structural diagram of an analog-to-digital converter provided by an embodiment of the present invention;

Figure 6 is a schematic structural diagram of a comparator in an analog-to-digital converter provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of an analog-to-digital conversion circuit provided by an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, rather than all embodiments.

Accordingly, the following detailed description of the embodiments of the application provided in the appended drawings is not intended to limit the scope of the claimed application, but rather to represent selected embodiments of the application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

In the description of this application, it should be noted that if the terms "upper", "lower", etc. indicate an orientation or positional relationship, it is based on the orientation or positional relationship shown in the drawings, or it is customary when using the product of the application. The placement of the orientation or positional relationship is only to facilitate the description of the present application and simplify the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. limits.

In addition, the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the invention described herein are capable of being practiced in sequences other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus that encompasses a series of steps or units and need not be limited to those explicitly listed. Those steps or elements may instead include other steps or elements not expressly listed or inherent to the process, method, product or apparatus.

It should be noted that, as long as there is no conflict, the features in the embodiments of the present application can be combined with each other.

Figure 1 is a schematic structural diagram of an analog-to-digital conversion circuit provided by an embodiment of the present invention. As shown in Figure 1, the analog-to-digital conversion circuit may include: a pipeline analog-to-digital converter 101 composed of N-stage analog-to-digital converters, N- 1 detection circuit 102, N-1 calibration circuits 103 and N-1 first calibration voltage generating circuits 104; N is an integer greater than or equal to 2.

Among them, if i is an integer less than N, i can be an integer greater than 0, less than or equal to N-1. The i-th stage analog-to-digital converter 101 may be any analog-to-digital converter among the N-stage analog-to-digital converters except the N-th stage analog-to-digital converter 101.

The digital terminal of the i-th stage analog-to-digital converter 101 is electrically connected to the first detection input terminal of a detection circuit 102 to output the i-th digital code; the digital terminal of the i+1-th stage analog-to-digital converter 101 is electrically connected to a detection circuit 102 The second detection input terminal is to output the i+1 digital code, so that a detection circuit 102 outputs the i-th voltage symbol detection value based on the i-th digital code and the i+1 digital code; the first detection value of a detection circuit 102 The output terminal is electrically connected to a first calibration input terminal of a calibration circuit 103, so that a calibration circuit 103 outputs the i-th voltage calibration code based on the i-th voltage symbol detection value.

In some embodiments, an analog voltage is input to the i-th level analog-to-digital converter 101, the i-th level analog-to-digital converter 101 can convert the input analog voltage, and the digital terminal of the i-th level analog-to-digital converter 101 can output the i-th level analog-to-digital converter 101. i digital encoding; input the margin voltage to the i+1-th stage analog-to-digital converter 101, the i+1-th stage analog-to-digital converter 101 can convert the input margin voltage, and the i+1-th stage analog-to-digital converter 101 The digital terminal can output the i+1th digital code. The remaining voltage may be the remaining unprocessed analog voltage of the i-th stage analog-to-digital converter 101 .

Correspondingly, a detection circuit 102 electrically connected to the i-th stage analog-to-digital converter 101 and the i+1-th stage analog-to-digital converter 101 can obtain the i-th digital code and the i+1-th digital code; and according to the i-th The digital code and the i+1th digital code determine the i-th voltage symbol detection value, and the i-th voltage symbol detection value is input to the first calibration input terminal of the calibration circuit 103; the calibration circuit 103 can obtain the i-th voltage symbol detection value, and calculate it according to the i-th voltage symbol detection value. The i voltage symbol detection value outputs the i voltage calibration code.

It should be noted that a detection circuit 102 may include a series of combinational logic circuits, and a detection circuit 102 may determine the polarity of the offset voltage based on the size relationship between the preset bit values in the i-th digital code and the i+1-th digital code. Detection is performed to determine the i-th voltage symbol detection value. When the offset voltage is determined to be positive, the i-th voltage sign detection value may be 1; when the offset voltage is determined to be negative, the i-th voltage sign detection value may be 0.

In addition, the calibration circuit 103 generates and outputs the i-th voltage calibration code based on the i-th voltage symbol detection value, and the i-th voltage calibration code may be a multi-bit binary code. When the i-th voltage calibration code has more digits, the step size of the calibration voltage is smaller, and the calibration accuracy is higher, but the hardware consumption of the circuit will also increase, and the convergence time of the calibration will also be extended; conversely, the i-th voltage calibration code When the number of digits is small, the calibration step is large, the accuracy is low, the hardware consumption is small, and the convergence time is short. The design of the number of digits of the i-th voltage calibration code can be determined based on the overall performance and requirements of the circuit.

A first calibration output terminal of a calibration circuit 103 is electrically connected to a digital terminal of a first calibration voltage generation circuit 104, so that a first calibration voltage generation circuit 104 outputs the i-th calibration voltage signal based on the i-th voltage calibration code; a first The analog terminal of the calibration voltage generation circuit 104 is electrically connected to the first input terminal of the comparator in the i-th stage analog-to-digital converter 101, so that the comparator in the i-th stage analog-to-digital converter 101 is based on the i-th calibration voltage signal and the corresponding input. The analog signal outputs the i-th target digital code. Wherein, every time the i-th voltage calibration code increases or decreases by "1", the i-th calibration voltage signal can correspondingly increase or decrease by one voltage step.

In some embodiments, the first calibration output terminal of a calibration circuit 103 can input the i-th voltage calibration code to the digital terminal of an electrically connected first calibration voltage generation circuit 104; the first calibration voltage generation circuit 104 can obtain the i-th voltage calibration code. i voltage calibration code, and output the i-th calibration voltage signal according to the i-th voltage calibration code. Wherein, the i-th calibration voltage signal may be an analog voltage.

In the embodiment of the present application, both the i-th calibration voltage signal and the analog signal are input to the comparator in the i-th stage analog-to-digital converter 101. The i-th calibration voltage signal can balance the comparator in the i-th stage analog-to-digital converter 101. The generated offset voltage, in turn, makes the i-th target digital encoding of the conversion output more accurate, thereby reducing the impact of the offset voltage on the equipment pipeline analog-to-digital converter.

In addition, the i-th calibration voltage signal can calibrate the offset voltages generated by the i-th stage analog-to-digital converter 101 and the i+1-th stage analog-to-digital converter 101, so that the i-th stage analog-to-digital converter 101 and the i-th stage analog-to-digital converter 101 can be calibrated. The relative offset voltage value of both +1-stage analog-to-digital converters 101 is 0.

It should be noted that an offset calibration circuit may include a detection circuit 102, a calibration circuit 103, and a first calibration voltage generating circuit 104.

Optionally, the analog voltage input by the i-th level analog-to-digital converter 101 can be expressed as Vi, the analog voltage input by the i+1-th level analog-to-digital converter 101 can be expressed as Vresi, and the i+1-th level analog-to-digital converter 101 can be expressed as Vresi. The output analog voltage can be expressed as Vresi+1. The i-th digital code can be expressed as Di, the i+1-th digital code can be expressed as Di+1, the i-th voltage symbol detection value can be expressed as Deci, the i-th voltage calibration code can be expressed as Dcali, and the i-th calibration voltage signal It can be expressed as Vcali.

To sum up, embodiments of the present application provide an analog-to-digital conversion circuit, including: a pipeline analog-to-digital converter composed of N-stage analog-to-digital converters, N-1 detection circuits, N-1 calibration circuits, and N-1 a first calibration voltage generating circuit; N is an integer greater than or equal to 2; where, if i is an integer less than N, the digital terminal of the i-th stage analog-to-digital converter is electrically connected to the first detection input terminal of a detection circuit, so as to Output the i-th digital code; the digital terminal of the i+1-th stage analog-to-digital converter is electrically connected to the second detection input terminal of a detection circuit to output the i+1-th digital code, so that a detection circuit is based on the i-th digital code and the i-th digital code. The i+1 digital code outputs the i-th voltage symbol detection value; the first detection output terminal of a detection circuit is electrically connected to the first calibration input terminal of a calibration circuit, so that a calibration circuit outputs the i-th voltage symbol detection value based on the i-th voltage symbol detection value. Voltage calibration code; a first calibration output terminal of a calibration circuit is electrically connected to a digital terminal of a first calibration voltage generation circuit, so that a first calibration voltage generation circuit outputs an i-th calibration voltage signal based on the i-th voltage calibration code; a first calibration voltage signal; The analog terminal of a calibration voltage generating circuit is electrically connected to the first input terminal of the comparator in the i-th stage analog-to-digital converter, so that the comparator in the i-th stage analog-to-digital converter is based on the i-th calibration voltage signal and the corresponding input analog signal. Output the i-th target digital code. Only N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits need to be set up to realize the calibration of the pipeline analog-to-digital converter composed of N-stage analog-to-digital converters, reducing the number of The number of offset calibration circuits required. Moreover, the i-th voltage symbol detection value is generated based on the i-th digital code and the i+1-th digital code, the i-th voltage calibration code can be determined based on the i-th voltage symbol detection value, and the i-th voltage calibration code is determined in real time based on the i-th voltage calibration code. The i-calibrated voltage signal eliminates the need for additional time for short circuiting, improves the processing speed of the pipeline analog-to-digital converter, and enables real-time tracking and calibration of the offset voltage generated by the circuit.

Moreover, the analog-to-digital conversion circuit provided by the embodiment of the present application can make the converted digital code more accurate during the normal operation of the pipeline analog-to-digital converter.

Optionally, Figure 2 is a schematic structural diagram of an analog-to-digital conversion circuit provided by an embodiment of the present invention. As shown in Figure 2, the analog-to-digital conversion circuit also includes: a second calibration voltage generation circuit 105;

The second detection output terminal of the N-1th detection circuit 102 is electrically connected to the second calibration input terminal of the N-1th calibration circuit 103, so that the N-1th detection circuit 102 is based on the Nth stage analog-to-digital converter 101 The output Nth digital code outputs the Nth voltage detection value;

The second calibration output terminal of the N-1th calibration circuit 103 is electrically connected to the digital terminal of the second calibration voltage generation circuit 105, so that the N-1th calibration circuit 103 outputs the Nth voltage calibration code based on the Nth voltage detection value, causing the second calibration voltage generation circuit 105 to output the Nth calibration voltage signal based on the Nth voltage calibration code;

The analog terminal of the second calibration voltage generation circuit 105 is electrically connected to an input terminal of the comparator in the N-th stage analog-to-digital converter 101, so that the comparator in the N-th stage analog-to-digital converter 101 is based on the N-th calibration voltage signal and the corresponding The input analog signal generates and outputs the Nth target digital code.

Among them, the Nth stage analog-to-digital converter 101 may be the last analog-to-digital converter in the pipeline analog-to-digital converter. The last offset calibration circuit may include a detection circuit 102, a calibration circuit 103, a first calibration voltage generation circuit 104, and a second calibration voltage generation circuit 105.

In some embodiments, the N-1th detection circuit 102 may be based on the N-1th digital code output by the N-1th stage analog-to-digital converter 101 and the Nth digital code output by the N-th stage analog-to-digital converter 101, Determine the N-1th voltage detection value; the N-1th calibration circuit 103 can output the N-1th voltage calibration code based on the N-1th voltage detection value; the first calibration electrically connected to the N-1th calibration circuit 103 The voltage generation circuit 104 outputs the N-1 calibration voltage signal according to the N-1 voltage calibration code. The N-1 calibration voltage signal can be used to calibrate the N-1 level analog-to-digital converter 101 and the N-th level analog-to-digital converter. The offset voltage generated by the comparator of converter 101.

In addition, the N-1th calibration circuit 103 outputs the Nth voltage calibration code based on the Nth voltage detection value, and the second calibration voltage generation circuit 105 outputs the Nth calibration voltage signal based on the Nth voltage calibration code. The Nth calibration voltage signal may also be Used to calibrate the offset voltage generated by the comparator of the N-th stage analog-to-digital converter 101, which can make the calibration of the offset voltage generated by the N-th stage analog-to-digital converter 101 more accurate, thereby making the N-th stage analog-to-digital converter more accurate. The Nth target digital code output by 101 is more accurate and can also calibrate the offset voltage of the overall output code of the pipeline analog-to-digital converter to 0.

Optionally, the analog voltage input by the N-1th stage analog-to-digital converter 101 can be expressed as Vn-1, and the analog voltage input by the N-th stage analog-to-digital converter 101 can be expressed as Vresn-1. The N-1th digital code can be expressed as Dn-1, and the Nth digital code can be expressed as Dn; the N-1th voltage detection value can be expressed as Decn-1, and the Nth voltage detection value can be expressed as Decn; the Nth The -1 voltage calibration code can be expressed as Dcaln-1, the Nth voltage calibration code can be expressed as Dcaln; the N-1th calibration voltage signal can be expressed as Vcaln-1, and the Nth calibration voltage signal can be expressed as Vcaln.

Optionally, FIG. 3 is a schematic structural diagram of a calibration voltage generation circuit provided by an embodiment of the present invention. The first calibration voltage generation circuit 104 and the second calibration voltage generation circuit 105 can be calibration voltage generation circuits with the same structure, as shown in FIG. As shown in 3, the calibration voltage generation circuit includes: a first switch array 107, M first resistors R1, M-1 second resistors R2 and a third resistor R3; where M is equal to the number of digits of the voltage calibration code, which is optional. , the number of the third resistor R3 can be two.

Among them, the first end of M-1 second resistors R2 connected in series is connected to the ground through the third resistor R3, and the second end connected in series is the analog end of the calibration voltage generating circuit. The voltage calibration code input by the first switch array 107 can be expressed as Dcal.

The input terminal of the first switch array 107 is the digital terminal of the calibration voltage generating circuit. The power terminal of the first switch array 107 is electrically connected to the preset reference voltage. The M output terminals of the first switch array 107 are respectively electrically connected to M first resistors. One end of R1 and two ends of each of the M-1 second resistors R2 are electrically connected to the other ends of the two first resistors R1 respectively. Optionally, two ends of each second resistor R2 among the M-1 second resistors R2 are electrically connected to the other ends of two adjacent first resistors R1 respectively.

The preset reference voltage may include: VRP (high level voltage), VRN (low level voltage).

In addition, the digital terminal of the calibration voltage generating circuit can output the i-th voltage calibration code, and the i-th voltage calibration code can be a multi-bit binary code. The i-th voltage calibration code controls one end of each first resistor R1 to be connected to the reference voltage VRP or VRN. The highest weight bit of the i-th voltage calibration code controls the leftmost first resistor R1, and so on. The i-th voltage calibration The lowest weight bit of the code controls the first rightmost resistor R1. Among them, when a weight bit of the i-th voltage calibration code is 1, the first resistor R1 controlled by the weight bit is connected to the reference voltage VRP; when a weight bit of the i-th voltage calibration code is 0, the weight bit controls The controlled first resistor R1 is connected to the reference voltage VRN.

It should be noted that, every time the i-th voltage calibration code increases or decreases by "1", the i-th calibration voltage signal can correspondingly increase or decrease by one voltage step.

Among them, the voltage step can be expressed as: Among them, VRP and VRN are reference voltages, and n represents the number of digits of the i-th voltage calibration code. The number of digits of the i-th voltage calibration code can be the same as the number of first resistors R1, that is, n can be equal to M.

Optionally, the resistance of the first resistor R1 may be twice the resistance of the second resistor R2, that is, R1=2*R2.

Optionally, Figure 4 is a schematic structural diagram of an analog-to-digital conversion circuit provided by an embodiment of the present invention. As shown in Figure 4, the analog-to-digital conversion circuit may also include: N-1 amplifiers 106;

Among them, the amplifier 106 can be a margin voltage amplifier. The margin output terminal of the i-th stage analog-to-digital converter 101 is also electrically connected to the input terminal of an amplifier 106. The output terminal of an amplifier 106 is also electrically connected to the i+1-th stage analog-to-digital converter. Analog side of converter 101.

It should be noted that in the related art, when the analog-to-digital conversion circuit also includes amplifiers 106, a correction circuit also needs to be provided for each amplifier 106. In the embodiment of the present application, based on N-1 detection circuits 102, N-1 calibration circuits 103 and N-1 first calibration voltage generating circuits 104, it is possible to implement N analog-to-digital converters, N-1 The offset voltage of the amplifier 106 is adjusted, further reducing the number of correction circuits required.

In addition, the i-th calibration voltage signal can also calibrate the offset voltage generated by the amplifier 106 between the i-th stage analog-to-digital converter 101 and the i+1-th stage analog-to-digital converter 101, so that the i-th stage analog-to-digital converter 101, The relative offset voltage value of the amplifier 106 between the i+1-th stage analog-to-digital converter 101, the i-th stage analog-to-digital converter 101, and the i+1-th stage analog-to-digital converter 101 is 0.

Optionally, the analog voltage output by the i-th stage analog-to-digital converter 101 can be expressed as Vresi. The amplifier 106 amplifies Vresi and outputs the analog voltage Vrai. Vrai can be used as the input of the i+1-th stage analog-to-digital converter 101.

Optionally, Figure 5 is a schematic structural diagram of an analog-to-digital converter provided by an embodiment of the present invention. As shown in Figure 5, each stage of the analog-to-digital converter includes: a comparator 110 and a digital-to-analog converter. The second input terminal is electrically connected to the analog terminal of each stage of the analog-to-digital converter, and the output terminal of the comparator 110 is the digital terminal of each stage of the analog-to-digital converter;

The output terminal of the comparator 110 is also electrically connected to the digital terminal of the digital-to-analog converter, and the analog terminal of the digital-to-analog converter is also electrically connected to the analog terminal of each stage of the analog-to-digital converter and the margin output terminal of each stage of the analog-to-digital converter.

Optionally, the analog-to-digital converter 101 in the embodiment of the present application may be a successive approximation type analog-to-digital converter.

Figure 6 is a schematic structural diagram of a comparator in an analog-to-digital converter provided by an embodiment of the present invention. As shown in Figure 6, the first input terminal 1101 of the comparator 110 can be a non-inverting input terminal, and the i-th calibration voltage signal can be The analog signal can be input into the comparator 110 through the first input terminal 1101, and the analog signal can be input into the comparator 110 through the second input terminal 1102 of the comparator 110, thereby superimposing the i-th calibration voltage signal and the analog signal. In addition, the comparator 110 may also include a ground terminal 1104 and an output terminal 1103.

It should be noted that the comparator shown in Figure 6 is a schematic diagram of a single-ended circuit structure. In actual design, the analog-to-digital converter can adopt a fully differential circuit structure, that is, it includes a forward signal port and a reverse signal port. The two ports apply Voltage signals have the characteristics of equal voltage values and opposite directions. Therefore, in a fully differential circuit structure, the comparator 110 may include two forward input terminals, a first input terminal 1101 and a second input terminal 1102, and a corresponding input terminal corresponding to the signal. The negative input terminal may no longer include the ground terminal 1104.

Optionally, as shown in Figure 5, the digital-to-analog converter may also include: a second switch array 108 and a capacitor array 109; wherein the input terminal of the second switch array 108 is the digital terminal of the digital-to-analog converter;

The plurality of output terminals of the second switch array 108 are respectively electrically connected to one terminal of each capacitor in the capacitor array 109. The other terminal of each capacitor in the capacitor array 109 is an analog terminal of the digital-to-analog converter.

Optionally, as shown in Figure 4, each calibration circuit 103 also has a trigger terminal; each calibration circuit 103 is specifically configured to output a voltage calibration code according to the received voltage detection value when the trigger signal received by the trigger terminal is valid.

Among them, the trigger signal can be expressed as TRIG.

In a possible implementation, every time there is a rising edge of the trigger signal, the calibration circuit 103 adjusts the i-th voltage calibration code according to the i-th voltage symbol detection value. When the i-th voltage symbol detection value is 1, the i-th voltage calibration code is subtracted by "1"; when the i-th voltage symbol detection value is 0, the i-th voltage calibration code is added with "1"; where "1" represents The minimum weight bit of the i-th voltage calibration code.

It should be noted that when the i-th voltage calibration code reaches the upper boundary, that is, "111...1", the next rising edge of the trigger signal comes, and when the i-th voltage symbol detection value is 0, the i-th voltage calibration code is output Remain unchanged; when the i-th voltage symbol detection value is 1, the i-th voltage calibration code is subtracted by "1". If the i-th voltage calibration code reaches the lower boundary, that is, "000...0", and the next rising edge of the trigger signal comes, when the i-th voltage symbol detection value is 1, the output code remains unchanged; when the i-th voltage symbol detection value When the symbol detection value is 0, "1" is added to the i-th voltage calibration code.

Optionally, as shown in Figure 4, each calibration circuit 103 also has a restart terminal. Each calibration circuit 103 is also used to reset the output voltage calibration code to the preset when detecting that the restart signal input by the restart terminal is valid. Coding value; when the restart signal is detected to be invalid, and when the trigger signal is valid, the voltage calibration code is output according to the received voltage detection value.

Among them, the restart signal can be expressed as RST, and the restart signal can also be called a reset signal.

In the embodiment of the present application, when the restart signal is 0, the restart signal is valid; when the restart signal is 1, the restart signal is invalid. When the restart signal is 0, the output voltage calibration code is reset to the preset code value "100...0". The first bit of the preset code value is the highest weight bit and can be used to control the highest value in the calibration voltage generation circuit. bit capacitance; when the restart signal is 1, the restart signal does not affect the circuit. The calibration circuit 103 is controlled by other signals, and the calibration circuit 103 can be controlled by the trigger signal.

Optionally, as shown in Figure 4, each calibration circuit 103 also has an enable terminal. Each calibration circuit 103 is specifically used when the restart signal is invalid, the trigger signal is valid, and the enable signal input to the enable terminal is valid. , output the voltage calibration code according to the received voltage detection value.

Among them, the enable signal can be represented by EN. When the enable signal is 0, the enable signal is invalid; when the enable signal is 1, the enable signal is valid.

It should be noted that when RST=1, EN=0, the calibration circuit 103 keeps the output of the current voltage calibration code unchanged, and TRIG does not work; when RST=1, EN=1, TRIG works, and the calibration circuit 103 normal work.

The following description takes a pipeline analog-to-digital converter including a two-stage analog-to-digital converter as an example. Figure 7 is a schematic structural diagram of an analog-to-digital conversion circuit provided by an embodiment of the present invention. As shown in Figure 7, the pipeline analog-to-digital converter It may include: a first-stage analog-to-digital converter 101, an amplifier 106, and a second-stage analog-to-digital converter 101. Correspondingly, the offset calibration circuit includes a detection circuit 102, a calibration circuit 103, a first calibration voltage generation circuit 104 and a second calibration voltage generation circuit 105.

Among them, the input analog voltage information Vin is first sampled by the first-stage analog-to-digital converter 101, and then quantized by the comparator of the first-stage analog-to-digital converter 101 to obtain the first-stage digital code (D1), and at the same time generate the first-stage digital code. Margin voltage (Vres1). Due to the offset of the comparator, an offset voltage (Vos1) will be introduced. Vos1 will be included in D1 and Vres1.

In addition, when the conversion of the first-stage analog-to-digital converter is completed, Vres1 is passed to the amplifier 106, and the amplifier 106 amplifies Vres1 by G times and outputs the voltage Vra. The amplification factor of the amplifier 106 is not related to the calibration. The amplification factor of the amplifier 106 can be set according to the power consumption and accuracy of the first-stage analog-to-digital converter 101, the amplifier 106, and the second-stage analog-to-digital converter 101. During the amplification process, the amplifier 106 will also introduce an offset voltage (Vosra) due to transistor mismatch and other effects. Vosra will be superimposed on Vra and passed to the next-stage analog-to-digital converter.

In the embodiment of the present application, the second-stage analog-to-digital converter 101 can sample Vra, and then the comparator in the second-stage analog-to-digital converter 101 performs quantization to obtain the second-stage digital code (D2). The comparator of the second-stage analog-to-digital converter 101 will introduce an offset voltage (Vos2), which will also be included in D2. During the amplification process of the amplifier 106, Vres1 needs to be maintained by the first-stage analog-to-digital converter 101, and the first-stage analog-to-digital converter 101 is in a static state; after the amplification is completed, the first-stage analog-to-digital converter 101 performs the next cycle. Sampling and conversion, the second-stage analog-to-digital converter 101 simultaneously converts Vra.

It should be noted that, assuming that the amplification factor of the interstage amplifier 106 is G, the total offset voltage Vosin can be: Among them, the first voltage detection value generated according to D1 and D2 is to determine the polarity of Vosin. The first voltage detection value output by the detection circuit 102 can be expressed as Dec1; the second voltage detection value generated according to D2 is to determine the polarity of Vos2. The polarity is determined, and the second voltage detection value output by the detection circuit 102 can be expressed as Dec2. The calibration circuit 103 outputs a first voltage calibration code (Dcal1) based on Dec1 and a second voltage calibration code (Dcal2) based on Dec2.

In addition, for the analog-to-digital conversion circuit as shown in Figure 7, the first calibration voltage signal of the first-stage analog-to-digital converter 101 can be expressed as Vcal1, and the second calibration voltage signal of the second-stage analog-to-digital converter 101 can be expressed as Vcal2, after calibration, the total input offset voltage of the analog-to-digital converter 101 can be expressed as: After several calibration processes, Vcal2 finally completely offsets Vos2, and Vcal1 will/> Completely offset to achieve offset calibration function.

To sum up, the analog-to-digital conversion circuit provided by the embodiment of the present application only needs to set up N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits, so as to realize N-level Calibration of the ADC consists of pipelined ADCs, reducing the number of offset calibration circuits required. Moreover, the i-th voltage symbol detection value is generated based on the i-th digital code and the i+1-th digital code, the i-th voltage calibration code can be determined based on the i-th voltage symbol detection value, and the i-th voltage calibration code is determined in real time based on the i-th voltage calibration code. i calibrates the voltage signal without requiring additional time for short circuiting, improving the processing speed of the pipeline analog-to-digital converter. Furthermore, there is no need to provide a correction circuit for each amplifier in the analog-to-digital conversion circuit, reducing the number of offset calibration circuits required.

Embodiments of the present application may also provide an electronic device, which may include the above-mentioned analog-to-digital conversion circuit.

The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims (10)

1. An analog-to-digital conversion circuit, comprising: the system comprises a pipeline analog-digital converter formed by N stages of analog-digital converters, N-1 detection circuits, N-1 calibration circuits and N-1 first calibration voltage generation circuits; n is an integer greater than or equal to 2;

if i is an integer smaller than N, the digital end of the ith analog-to-digital converter is electrically connected with the first detection input end of a detection circuit to output the ith digital code; the digital end of the (i+1) -th level analog-to-digital converter is electrically connected with the second detection input end of the one detection circuit to output an (i+1) -th digital code, so that the one detection circuit outputs an (i) -th voltage symbol detection value based on the (i+1) -th digital code and the (i+1) -th digital code; the first detection output end of the detection circuit is electrically connected with the first calibration input end of a calibration circuit, so that the calibration circuit outputs an ith voltage calibration code based on the ith voltage symbol detection value;

the first calibration output end of the one calibration circuit is electrically connected with the digital end of the one first calibration voltage generation circuit, so that the one first calibration voltage generation circuit outputs an ith calibration voltage signal based on the ith voltage calibration code; the analog end of the first calibration voltage generating circuit is electrically connected with the first input end of the comparator in the ith analog-to-digital converter, so that the comparator in the ith analog-to-digital converter outputs an ith target digital code according to the ith calibration voltage signal and the corresponding input analog signal.

2. The analog-to-digital conversion circuit of claim 1, further comprising: a second calibration voltage generation circuit;

the second detection output end of the (N-1) -th detection circuit is electrically connected with the second calibration input end of the (N-1) -th calibration circuit, so that the (N-1) -th detection circuit outputs an (N) -th voltage detection value based on the (N) -th digital code output by the (N) -th analog-to-digital converter;

a second calibration output end of the N-1 th calibration circuit is electrically connected with a digital end of the second calibration voltage generation circuit, so that the N-1 th calibration circuit outputs an N-th voltage calibration code based on the N-th voltage detection value, and the second calibration voltage generation circuit outputs an N-th calibration voltage signal based on the N-th voltage calibration code;

the analog end of the second calibration voltage generating circuit is electrically connected with one input end of the comparator in the N-th stage analog-to-digital converter, so that the comparator in the N-th stage analog-to-digital converter generates and outputs an N-th target digital code based on the N-th calibration voltage signal and the corresponding input analog signal.

3. The analog-to-digital conversion circuit according to claim 2, wherein the first calibration voltage generation circuit and the second calibration voltage generation circuit are calibration voltage generation circuits of the same structure, the calibration voltage generation circuit comprising: the first switch array, M first resistors, M-1 second resistors and a third resistor; wherein M is equal to the number of bits of the voltage calibration code;

the first ends of the M-1 second resistors which are sequentially connected in series are grounded through the third resistor, and the second ends of the M-1 second resistors which are sequentially connected in series are analog ends of the calibration voltage generating circuit;

the input end of the first switch array is a digital end of the calibration voltage generation circuit, and the power end of the first switch array is electrically connected with a preset reference voltage; the M output ends of the first switch array are respectively and electrically connected with one ends of M first resistors, and two ends of each second resistor in the M-1 second resistors are respectively and electrically connected with the other ends of the two first resistors.

4. The analog-to-digital conversion circuit of claim 3, wherein a resistance of the first resistor is twice a resistance of the second resistor.

5. The analog-to-digital conversion circuit of claim 1, further comprising: n-1 amplifiers;

the residual output end of the ith analog-to-digital converter is also electrically connected with the input end of an amplifier, and the output end of the amplifier is also electrically connected with the analog end of the (i+1) th analog-to-digital converter.

6. The analog-to-digital conversion circuit of claim 5, wherein each stage of analog-to-digital converter comprises: the second input end of the comparator is electrically connected with the analog end of each stage of analog-to-digital converter, and the output end of the comparator is the digital end of each stage of analog-to-digital converter;

the output end of the comparator is also electrically connected with the digital end of the digital-to-analog converter, and the analog end of the digital-to-analog converter is also electrically connected with the analog end of each stage of analog-to-digital converter and the residual output end of each stage of analog-to-digital converter.

7. The analog-to-digital conversion circuit of claim 6, wherein the digital-to-analog converter comprises: a second switch array, a capacitor array; the input end of the second switch array is the digital end of the digital-to-analog converter;

the output ends of the second switch array are respectively and electrically connected with one end of each capacitor in the capacitor array, and the other end of each capacitor in the capacitor array is an analog end of the digital-to-analog converter.

8. The analog-to-digital conversion circuit of claim 1, wherein each calibration circuit further has a trigger terminal; each calibration circuit is specifically configured to output a voltage calibration code according to the received voltage detection value when the trigger signal received by the trigger terminal is valid.

9. The analog-to-digital conversion circuit of claim 8, wherein each calibration circuit further has a restart terminal, and wherein each calibration circuit is further configured to reset the output voltage calibration code to a preset code value when a restart signal input from the restart terminal is detected to be valid; and outputting a voltage calibration code according to the received voltage detection value when the restarting signal is detected to be invalid and the triggering signal is detected to be valid.

10. The analog-to-digital conversion circuit of claim 8, wherein each calibration circuit further has an enable terminal, and wherein each calibration circuit is specifically configured to output a voltage calibration code according to the received voltage detection value when the restart signal is inactive and the trigger signal is active and the enable signal input from the enable terminal is active.