CN113327846B - Analog circuit including high-resistance resistor and GGNMOS ESD and method of making same - Google Patents

Abstract

The application discloses an analog circuit comprising a high-resistance resistor and GGNMOS ESD and a manufacturing method thereof. Forming a first STI, a second STI, a first high-voltage P well and a second high-voltage P well on a semiconductor substrate; performing polysilicon deposition on the surface of the semiconductor substrate to form a polysilicon region; opening a window in a polysilicon region on a semiconductor substrate; and performing high-resistance injection and high-energy injection to form high-resistance polysilicon, N+ polysilicon, a first ESD injection well and a second ESD injection well. The high-resistance implantation and the high-energy implantation are utilized to combine the two photomasks into one photomask, the problem of complex process for manufacturing the analog circuit comprising the high-resistance resistor and the GGNMOS ESD is solved, and the manufacturing cost is saved.

Description

Analog circuit including high-resistance resistor and GGNMOS ESD and manufacturing method thereof

technical field

The invention relates to the field of semiconductor manufacturing, in particular to an analog circuit including a high-resistance resistor and a GGNMOS ESD and a manufacturing method thereof.

Background technique

High-resistance resistors and GGNMOS ESD (gate-grounded NMOS electrostatic discharge) are widely used in analog circuits in chip design. A schematic cross-sectional view of a high-resistance resistor device in an analog circuit in the prior art is shown in FIG. P-type body region 2 and high-resistance polysilicon 4 . A schematic cross-sectional view of a GGNMOS ESD device in an analog circuit in the prior art is shown in FIG. 2. The GGNMOS ESD includes several second STIs 5, a second high-voltage P well 6, a second P-type body region 7, and two N-type body regions 8. , The first ESD is implanted into the well 9 and the N+ polysilicon 10 .

According to Figure 1 and Figure 2, there are certain differences in the structure of standard high-resistance resistors and GGNMOS ESD devices. Standard high-resistance resistors do not have ESD injection wells, while GGNMOS ESD devices contain ESD injection wells. And the analog circuit of GGNMOS ESD, generally after the high-resistance resistance device is fabricated by high-resistance injection, the GGNMOS ESD device is fabricated by ESD injection. There are the problems of complicated manufacturing process steps and relatively high manufacturing cost.

Contents of the invention

The technical problem to be solved in the present invention is in order to overcome the manufacturing process steps of the analog circuit comprising high-impedance resistor and GGNMOSESD complex in the prior art, and the defect that manufacturing cost is higher, proposes a kind of analog circuit that comprises high-impedance resistor and GGNMOS ESD and its production method.

The present invention solves the above technical problems through the following technical solutions:

In a first aspect, the present invention provides an analog circuit including a high-resistance resistor and a GGNMOS ESD and a manufacturing method thereof, the high-resistance resistor including a first STI, a first high-voltage P well, a first P-type body region, and a high-resistance polysilicon The GGNMOS ESD includes several second STIs, a second high-voltage P well, a second P-type body region, two N-type body regions, a first ESD implant well and N+ polysilicon; the manufacturing method includes the following steps:

forming the first STI, the second STI, the first high voltage P well, and the second high voltage P well on a semiconductor substrate;

performing polysilicon deposition on the surface of the semiconductor substrate to form a polysilicon region;

opening a window in the polysilicon region on the semiconductor substrate;

performing high-resistance implantation and high-energy implantation to form the high-resistance polysilicon, the N+ polysilicon, the first ESD injection well, and the second ESD injection well, and the second ESD injection well is located in the GGNMOS ESD above the second high-voltage P-well;

The first P-type body region, the second P-type body region, and two of the N-type body regions are formed.

Preferably, the steps of performing high-resistance implantation and high-energy implantation include:

performing high-resistance implantation to form a high-resistance structure in the region where the high-resistance polysilicon and the N+ polysilicon are located;

performing high-energy implantation to form the first ESD implantation well and the second ESD implantation well.

Preferably, the steps of performing high-resistance implantation and high-energy implantation include:

performing high-energy implantation to form the first ESD implant well and the second ESD implant well;

Perform high-resistance implantation to form a high-resistance structure in the area where the high-resistance polysilicon and the N+ polysilicon are located.

Preferably, the step of forming the first P-type body region, the second P-type body region, and the two N-type body regions includes:

Perform P+ type ion implantation on both sides of the first STI and the region between the second STI above the second ESD implant well and the second high voltage P well to form the first P a body region and said second P-type body region;

N+ type ion implantation is performed in the upper region between both sides of the region where the N+ polysilicon is located and the second ESD implantation well to form two N type body regions.

Preferably, the concentration of the N+ type ion implantation is 3E15/cm ² -4E15/cm ² .

Preferably, the high-resistance implantation adopts boron ion implantation, and the boron ion stays in the polysilicon region.

Preferably, the high-energy implantation adopts P-type ion implantation, and the P-type ions are gathered under the region where the high-resistance polysilicon and the N+ polysilicon are located.

Preferably, during the high-energy implantation, the concentration of implanted P-type ions is adjusted according to the performance requirements of the first ESD implantation well.

Preferably, the boron ion implantation concentration is 4.5-5E14/cm ² , and the boron ion implantation dose is 1-5E13/cm ² .

In a second aspect, the present invention provides an analog circuit comprising a high-impedance resistor and a GGNMOS ESD, the high-impedance resistor and the GGNMOS ESD using the manufacturing method of an analog circuit comprising a high-impedance resistor and a GGNMOS ESD described in the first aspect Make Generate.

The positive progress effect of the present invention is: the analog circuit that the present invention provides comprises high-resistance resistance and GGNMOS ESD and manufacturing method thereof, utilizes high-resistance injection to insert high-energy ESD injection to replace independent ESD injection well photomask, promptly utilizes high-resistance injection and High-energy injection realizes the combination of two photomasks into one photomask, realizes free GGNMOS ESD, solves the problem of complex process of making analog circuits including high-resistance resistors and GGNMOS ESD, and saves manufacturing costs.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a high-resistance resistor device in an analog circuit in the prior art.

FIG. 2 is a schematic cross-sectional view of a GGNMOS ESD device in an analog circuit in the prior art.

FIG. 3 is a flowchart of a method for manufacturing an analog circuit including a high-resistance resistor and a GGNMOS ESD in Embodiment 1 of the present invention.

FIG. 4 is a first schematic cross-sectional view of the high-resistance resistor device in step S4 in FIG. 3 .

FIG. 5 is a first cross-sectional schematic view of the GGNMOS ESD device in step S4 in FIG. 3 .

FIG. 6 is a second schematic cross-sectional view of the high-resistance resistor device in step S4 in FIG. 3 .

FIG. 7 is a second schematic cross-sectional view of the GGNMOS ESD device in step S4 in FIG. 3 .

FIG. 8 is a schematic cross-sectional view of a high-resistance resistor device produced based on the fabrication method of Embodiment 1. FIG.

FIG. 9 is a schematic cross-sectional view of a GGNMOS ESD device produced based on the manufacturing method of Embodiment 1. FIG.

Detailed ways

The present invention is further illustrated below by means of examples, but the present invention is not limited to the scope of the examples.

Example

This embodiment provides a method for manufacturing an analog circuit including a high-impedance resistor and a GGNMOS ESD. As shown in FIG. 3 , the method disclosed in this embodiment includes the following steps:

Step S1 , forming a first STI1 , a second STI5 , a first high voltage P well 3 , and a second high voltage P well 6 on the semiconductor substrate.

In this embodiment, when the first STI1 and the second STI5 are fabricated on the semiconductor substrate, in other words, the STI region is fabricated. In the first high-voltage P well 3 and the second high-voltage P well 6, etch grooves in preset regions through a mask, and then fill the grooves with SiO ₂ (silicon dioxide), and use instruments to fill the grooves of SiO ₂ Polishing is performed to form regions corresponding to the first STI1 and the second STI5 , that is, shallow trench isolation regions.

Step S2, performing polysilicon deposition on the surface of the semiconductor substrate to form a polysilicon region.

A polysilicon layer, that is, a polysilicon region, is formed after polysilicon deposition is performed on the first STI1 and the second STI5 formed.

Step S3, opening a window in the polysilicon region on the semiconductor substrate.

A photoresist is coated on the polysilicon layer, and the photoresist is used to block boron ion implantation or other ion implantation during subsequent high-resistance implantation and high-energy implantation. Therefore, as shown in FIG. 4 and FIG. 5 , a window is opened in the gate polysilicon area not covered by photoresist.

Step S4 , performing high-resistance implantation and high-energy implantation to form high-resistance polysilicon, N+ polysilicon 10 , first ESD implantation well 9 and second ESD implantation well 11 . The cross-sectional schematic diagrams of the high-resistance resistor and the GGNMOS ESD device after this step are shown in Fig. 6 and Fig. 7 .

Wherein, the high-resistance implantation adopts boron ion implantation, and the boron ion stays in the polysilicon region.

Specifically, referring to FIG. 4 and FIG. 5 , boron ions are implanted into the polysilicon region along the direction indicated by the arrow. The boron ions may be heavily doped boron ions, so that the boron ions stay in the polysilicon region. The high-resistance injection is a technical term in the field, and those skilled in the art are aware of the energy range used for the high-resistance injection. In this embodiment, the process mainly applies to 10V-12V (volt) devices, and no diffusion is required.

In a possible implementation manner, the depth of boron ion implantation can be 0.5-1 micron, and the implantation angle can be 3-6 degrees. Those skilled in the art can understand that the implantation depth and implantation angle can be adjusted according to the specific process. , no specific limitation is made here.

Wherein, the high-energy implantation adopts P-type ion implantation, and the P-type ions are gathered under the region where the high-resistance polysilicon and N+ polysilicon 10 are located.

Further, referring to FIG. 6 and FIG. 7 , when high-energy implantation is performed above the region where the gate high-resistance polysilicon and N+ polysilicon 10 are not covered by photoresist, the implantation is performed along the direction indicated by the arrow. P-type ions are continuously implanted from the polysilicon region after the high-resistance implantation, so that the P-type ions penetrate the N+ polysilicon 10 and the region where the high-resistance polysilicon is located. In other words, the P-type ions gather under the regions where the high-resistance polysilicon and N+ polysilicon 10 are located, forming the first ESD implantation well 9 and the second ESD implantation well 11 .

Preferably, during the high-energy implantation process, the concentration of implanted P-type ions can be adjusted according to the performance requirements of the first ESD implantation well 9 .

In this embodiment, the concentration of implanted P-type ions can be adjusted according to the performance requirements of the first ESD implantation well 9 in the GGNMOS ESD device, so as to enhance the performance of the GGNMOS ESD device.

In a possible implementation manner, the steps of performing high-resistance implantation and high-energy implantation in step S4 include:

Perform high-resistance implantation first to form a high-resistance structure in the region where the high-resistance polysilicon and N+ polysilicon 10 are located;

High-energy implantation is then performed to form the first ESD implantation well 9 and the second ESD implantation well 11 .

In another possible implementation manner, the steps of performing high-resistance implantation and high-energy implantation in step S4 include:

Perform high-energy implantation first to form the first ESD implantation well 9 and the second ESD implantation well 11;

The high-resistance implantation is then performed to form a high-resistance structure in the area where the high-resistance polysilicon and the N+ polysilicon 10 are located.

The concentration of the boron ion implantation is 4.5-5E14/cm ² , and the dose of the boron ion implantation is 1-5E13/cm ² .

In this embodiment, when forming the first ESD injection well 9 and the second ESD injection well 11 , high-resistance implantation and high-energy implantation are required, and the order of the high-resistance implantation and the high-resistance implantation is not specifically limited. The implantation energy of a normal ESD implantation well is 100-150Kev. During the process of high-resistance implantation, it is necessary to increase the implantation energy due to the consideration that the polysilicon region where boron ions stay will have a certain degree of blocking effect. It can reach 200-300Kev, but the dose basically does not change much compared with the existing process. The embodiment of the present application adopts the implantation dose of 1-5E13/cm ² . Those skilled in the art can make adjustments according to actual conditions, so details will not be repeated here.

Step S5 , forming a first P-type body region 2 , a second P-type body region 7 , and two N-type body regions 8 . The cross-sectional schematic diagrams of the high resistance resistor and the GGNMOS ESD device after this step are shown in Fig. 8 and Fig. 9 .

In this embodiment, referring to FIG. 8 , on both sides of the first STI1 , the first P-type body region 2 in the high-resistance resistor is formed by performing P+ type ion implantation. Referring to FIG. 9 , in the region between the second STIs 5 , a second P-type body region 7 is formed by performing P+ type ion implantation. Those skilled in the art can understand that when implanting P+ type ions, the implantation depth and implantation angle can be determined according to specific processes.

Wherein, step S5 includes:

Perform P+ type ion implantation on both sides of the first STI1 and the area between the second STI5 above the second ESD implantation well 11 and the second high-voltage P well 6 to form the first P-type body region 2 and the second P-type body region. Body area 7.

N+ type ion implantation is performed in the upper region between both sides of the region where the N+ polysilicon 10 is located and the second ESD implantation well 11 to form two N type body regions 8 .

Wherein, the concentration of N+ type ion implantation is 3E15/cm ² -4E15/cm ² .

Specifically, since the first STI1 and the second ESD injection well 11 are isolated in the high-resistance resistor, there is no influence on its own resistance value. In other words, high-resistance polysilicon is a surface device, and its function is not affected by well implantation. In addition, GGNMOS ESD is a bulk device, and the resistance of boron ions staying in the polysilicon region has limited influence on the GGNMOS ESD device. Therefore, the performance of the high-resistance resistor and GGNMOS ESD device manufactured according to the manufacturing process in the embodiment of this application Meet the process requirements.

Further, referring to FIG. 9, in the process of making the GGNMOS ESD device, when N+ type ion implantation is performed in the region between the two sides of the N+ polysilicon 10 region and the second ESD implantation well 11, the P+ type ion above the gate of the GGNMOS ESD device The high-resistance implantation corresponding to the ions will produce a counterbalance to the high-concentration implantation corresponding to the N+ type ions.

In this embodiment, as shown in FIG. 9 , a sidewall barrier region 13 is formed on one side of the region corresponding to the N+ polysilicon mixed high-resistance polysilicon 12 , and the sidewall barrier region 13 can be an alloy barrier layer or a silicide barrier layer. Silicon oxide is deposited first, and then processed through a photomask, but in this process, the silicon oxide barrier layer is not exposed, and the non-gate polysilicon area not covered by photoresist is etched, and then the etched The etched polysilicon region is cleaned to form sidewalls of the gate, that is, sidewall barrier regions 13 .

This embodiment provides a method for manufacturing an analog circuit including a high-resistance resistor and a GGNMOS ESD. By forming the first STI, the second STI, the first high-voltage P well, and the second high-voltage P well on the semiconductor substrate; performing polysilicon deposition on the surface of the semiconductor substrate to form a polysilicon region; opening the polysilicon region on the semiconductor substrate window; perform high-resistance implantation and high-energy implantation to form high-resistance polysilicon, N+ polysilicon, first ESD injection well and second ESD injection well. Using high-resistance injection to insert high-energy ESD injection to replace a separate ESD injection well mask, that is, to use high-resistance injection and high-energy injection to realize the combination of two masks into one mask, to realize the production of free GGNMOS ESD, and to solve the problem of production including high The problem of complex analog circuit technology of resistors and GGNMOSESD saves manufacturing costs.

Example

This embodiment provides an analog circuit including a high-resistance resistor and GGNMOS ESD, and the high-resistance resistor and GGNMOS ESD are manufactured using the method for manufacturing an analog circuit including a high-resistance resistor and GGNMOS ESD in Embodiment 1.

Compared with the manufacturing method of traditional standard high-resistance resistor and GGNMOS ESD device, the analog circuit including high-resistance resistor and GGNMOS ESD provided by this embodiment uses high-resistance injection to insert high-energy ESD injection instead of a separate ESD injection well. mask, that is, the use of high-resistance injection and high-energy injection realizes the combination of two photomasks into one photomask, realizes the production of free GGNMOS ESD, solves the problem of complex analog circuit technology including high-resistance resistors and GGNMOS ESD, and saves manufacturing cost. At the same time, the efficiency of the GGNMOS ESD device is adjusted by adjusting the concentration of implanted ions according to the performance requirements of the first ESD implanted well, thereby improving the competitiveness of the power device.

Although the specific implementation of the present invention has been described above, those skilled in the art should understand that this is only an example, and the protection scope of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principle and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims (8)

1. A method of making an analog circuit comprising high-resistance resistors and GGNMOS ESD, said high-resistance resistors comprising the first STI, the first high-voltage P well, the first P-type body region, high-resistance polysilicon and the second ESD injection well ; The GGNMOS ESD includes several second STIs, a second high-voltage P well, a second P-type body region, two N-type body regions, a first ESD implant well, and N+ polysilicon; It is characterized in that the manufacturing method comprises the following steps: forming the first STI, the second STI, the first high voltage P well, and the second high voltage P well on a semiconductor substrate; performing polysilicon deposition on the surface of the semiconductor substrate to form a polysilicon region; opening a window in the polysilicon region on the semiconductor substrate; performing high-resistance implantation and high-energy implantation to form the high-resistance polysilicon, the N+ polysilicon, the first ESD injection well, and the second ESD injection well, and the second ESD injection well is located in the first high-voltage P well above; the first ESD injection well is located above the second high voltage P well; forming the first P-type body region, the second P-type body region, and two of the N-type body regions; Wherein, the steps of performing high-resistance implantation and high-energy implantation include: Performing high-resistance implantation to form a high-resistance structure in the region where the high-resistance polysilicon and the N+ polysilicon are located; performing high-energy implantation to form the first ESD injection well and the second ESD injection well, or Performing high-energy implantation to form the first ESD implantation well and the second ESD implantation well; performing high-resistance implantation to form a high-resistance structure in the area where the high-resistance polysilicon and the N+ polysilicon are located. 2. the manufacture method of the analog circuit that comprises high-resistance resistance and GGNMOS ESD as claimed in claim 1, is characterized in that, described forming described first P-type body region, described second P-type body region, two The steps of the N-type body region include: Perform P+ type ion implantation on both sides of the first STI and the region between the second STI above the second ESD implant well and the second high voltage P well to form the first P a body region and said second P-type body region; N+ type ion implantation is performed in the upper region between both sides of the region where the N+ polysilicon is located and the second ESD implantation well to form two N type body regions. 3 . The method for manufacturing an analog circuit comprising a high-resistance resistor and GGNMOS ESD according to claim 2 , wherein the concentration of the N+ type ion implantation is 3E15/cm ² -4E15/cm ² . 4. The method for manufacturing an analog circuit comprising a high-resistance resistor and a GGNMOS ESD according to claim 1, wherein the high-resistance implantation adopts boron ion implantation, and the boron ion stays in the polysilicon region. 5. the manufacturing method of the analog circuit comprising high-resistance resistor and GGNMOS ESD as claimed in claim 1, is characterized in that, described high-energy implantation adopts P-type ion implantation, and described P-type ion gathers in described high-resistance polysilicon and Below the region where the N+ polysilicon is located. 6. the manufacture method of the analog circuit comprising high-resistance resistor and GGNMOS ESD as claimed in claim 5, is characterized in that, in the process of described high-energy injection, according to the performance requirement of described first ESD injection well, adjust and inject the The concentration of P-type ions. 7. The method for manufacturing an analog circuit comprising high-resistance resistors and GGNMOS ESD as claimed in claim 4, wherein the concentration of the boron ion implantation is 4.5 to 5E14/cm ² , and the dose of the boron ion implantation is 1～5E13/cm ² . 8. An analog circuit comprising a high-impedance resistor and a GGNMOS ESD, characterized in that, the high-impedance resistor and the GGNMOS ESD use a circuit comprising a high-impedance resistor and a GGNMOS ESD as described in any one of claims 1-7. The production method of the analog circuit is produced and generated.