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CN113327537B - Shift register, grid drive circuit and display device - Google Patents

Shift register, grid drive circuit and display device Download PDF

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Publication number
CN113327537B
CN113327537B CN202110671295.5A CN202110671295A CN113327537B CN 113327537 B CN113327537 B CN 113327537B CN 202110671295 A CN202110671295 A CN 202110671295A CN 113327537 B CN113327537 B CN 113327537B
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transistor
circuit
pull
node
sub
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CN113327537A (en
Inventor
任锦宇
陆顺沙
彭宽军
张方振
王锦谦
王玮
马国靖
王丹
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)

Abstract

The disclosure provides a shift register, a grid driving circuit and a display device, and belongs to the technical field of display. The shift register comprises a first auxiliary control sub-circuit and a second auxiliary control sub-circuit, wherein the first auxiliary control sub-circuit is used for writing a first low level into a pull-down node and writing a second low level into a control node when the pull-up node is a high level, so that the working state of the first noise reduction sub-circuit is controlled by controlling the voltage difference between the first low level and the second low level, and the influence of the electric leakage of the first noise reduction sub-circuit on the electric potential of the pull-up node is avoided. The pull-up node is a connecting node of the input sub-circuit, the output sub-circuit, the pull-down sub-circuit, the first noise reduction sub-circuit, the first auxiliary control sub-circuit and the reset sub-circuit; the control node is a connection node of the first noise reduction sub-circuit, the first auxiliary control sub-circuit and the second auxiliary control sub-circuit.

Description

Shift register, grid drive circuit and display device
Technical Field
The invention belongs to the technical field of display, and particularly relates to a shift register, a grid drive circuit and a display device.
Background
The basic principle of a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) for displaying one frame of picture is to input a square wave with a certain width to each row of pixels in sequence from top to bottom through gate (gate) driving, and then output signals required for driving each row of pixels from top to bottom through source (source) in sequence.
The existing display device is manufactured by adopting a design of a gate Drive On array (goa) circuit, compared with the traditional Chip On Film (COF) or Chip On Glass (COG) process, the cost is saved, the attractive design of two symmetrical sides of the panel can be realized, and a Bonding area and a peripheral wiring space of a gate Drive circuit can be saved, so that the design of a narrow frame of a display device is realized, and the productivity and the yield of the display device are improved. The active layer material of the thin film transistor used in the GOA circuit can be selected from a-Si (amorphous silicon), LTPS (low temperature polysilicon), IGZO (Indium Gallium Zinc Oxide), and the like. The large-sized display screen usually selects the thin film transistor with IGZO as the thin film transistor in the GOA circuit, but when the display size and resolution are further increased, the oxide thin film transistor with higher mobility needs to be selected and applied to the GOA circuit.
The present invention provides a GOA circuit with high stability, which is a technical problem to be solved urgently, because the threshold voltage of a thin film transistor is unstable and negative bias fluctuation is liable to occur when a thin film transistor with higher mobility is selected, which may cause leakage current of the thin film transistor and affect the operating performance of the GOA circuit.
Disclosure of Invention
The present invention is directed to at least one of the technical problems in the prior art, and provides a shift register, a gate driving circuit and a display device.
The technical scheme adopted for solving the technical problem of the invention is a shift register, which comprises: the device comprises an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a first auxiliary control sub-circuit and a second auxiliary control sub-circuit; wherein,
the input sub-circuit is configured to charge a pull-up node under the control of an input signal; wherein the pull-up node is a connection node between the input sub-circuit, the output sub-circuit, the first noise reduction sub-circuit, the first auxiliary control sub-circuit, and the pull-down sub-circuit;
the output sub-circuit is configured to pull up the output of the signal output terminal by a clock signal under the control of the pull-up node potential;
the pull-down control sub-circuit is configured to be under the control of a first power supply voltage and control the potential of a pull-down node through the first power supply voltage; the pull-down node is a connection node among the pull-down control sub-circuit, the pull-down sub-circuit and the first noise reduction sub-circuit;
the pull-down sub-circuit is configured to pull down the potential of the pull-down node by the first non-operating level signal under the control of the potential of the pull-up node;
the first auxiliary control sub-circuit is configured to write a second non-working level into the control node and control the first noise reduction sub-circuit to be turned off when the pull-down node is at a first non-working level; wherein the control node is a connection node between the first noise reduction sub-circuit, the first auxiliary control sub-circuit, and the second auxiliary control sub-circuit;
the second auxiliary control sub-circuit is configured to write the first non-operating level into a control node when the potential of the pull-down node is a first power supply voltage, so as to control the first noise reduction sub-circuit to reduce noise of the pull-up node through the non-first operating level.
Optionally, the shift register further includes: and the reset module is used for resetting the potentials of the pull-up node and the signal output end through a non-working level signal under the control of a reset signal.
Optionally, the reset module includes: a second transistor and a fourth transistor; wherein,
the first pole of the second transistor is connected with the pull-up node, the second pole of the second transistor is connected with the non-working level end, and the control pole of the second transistor is connected with the reset signal end;
and a first pole of the fourth transistor is connected with the signal output end, a second pole of the fourth transistor is connected with the non-working level signal end, and a control pole of the fourth transistor is connected with the reset signal end.
Optionally, the shift register further includes: a second noise reduction sub-circuit configured to reduce noise of the signal output terminal by the second non-operating level when the potential of the pull-down node is the first power supply voltage.
Optionally, the second noise reduction sub-circuit comprises: a fourth transistor; wherein,
and a first pole of the fourth transistor is connected with the signal output end, a second pole of the fourth transistor is connected with the second non-working level end, and a control pole of the fourth transistor is connected with the pull-down node.
Optionally, the input sub-circuit comprises: a first transistor; wherein,
and the first pole and the control pole of the first transistor are both connected with a signal input end, and the second pole of the first transistor is connected with the pull-up node.
Optionally, the output sub-circuit comprises a third transistor and a storage capacitor; wherein,
the first pole of the third transistor is connected with a clock signal end, the second pole of the third transistor is connected with the signal output end and the second end of the storage capacitor, and the control pole of the third transistor is connected with the first end of the storage capacitor and the pull-up node.
Optionally, the pull-down control sub-circuit comprises a fifth transistor; wherein,
and a first pole and a control pole of the fifth transistor are connected with the first power supply voltage end, and a second pole of the fifth transistor is connected with the pull-down node.
Optionally, the pull-down sub-circuit comprises a sixth transistor and a seventh transistor, wherein:
a first pole of the seventh transistor is connected with the pull-down node, a second pole of the seventh transistor is connected with the second non-working level end, and a control pole of the seventh transistor is connected with the pull-up node;
and a first pole of the sixth transistor is connected with the pull-down node, a second pole of the sixth transistor is connected with the second non-working level end, and a control pole of the sixth transistor is connected with the pull-up node.
Optionally, the first auxiliary control sub-circuit comprises a tenth transistor, wherein:
the tenth transistor has a first electrode connected to the control node, a second electrode connected to the second non-operating level terminal, and a control electrode connected to the pull-up node.
Optionally, the second auxiliary control sub-circuit comprises a ninth transistor, wherein:
and a first pole of the ninth transistor is connected with the control node, a second pole of the ninth transistor is connected with the first non-working level end, and a control pole of the ninth transistor is connected with the pull-down node.
The technical scheme adopted for solving the technical problem of the invention is a gate drive circuit which comprises a plurality of cascaded shift registers.
The technical scheme adopted for solving the technical problem of the invention is a display device which comprises the grid drive circuit.
Drawings
FIG. 1 is a schematic diagram of an exemplary shift register structure;
FIG. 2 is a circuit schematic of an exemplary shift register;
FIG. 3 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;
FIG. 4 is a circuit diagram of a shift register according to an embodiment of the disclosure;
FIG. 5 is a schematic diagram of another shift register according to an embodiment of the present disclosure;
fig. 6 is a circuit diagram of another shift register according to an embodiment of the disclosure.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention is further described in detail with reference to the accompanying drawings and the detailed description below.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used are symmetrical, there is no difference in the source and drain functions. In the embodiment of the present invention, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, the N-type transistors are used for explanation, when the N-type transistors are used, the first electrode is the drain electrode of the N-type transistor, the second electrode is the source electrode of the N-type transistor, and when the high level is input to the gate electrode, the source and drain electrodes are conducted, and the P-type is opposite. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without inventive effort and, thus, are within the scope of the embodiments of the present invention.
It should be noted that, in this embodiment, the operating level refers to a high level, and the non-operating level refers to a low level; correspondingly, the first power voltage end refers to a signal end VDD; the first non-operating level end refers to a first low level end LVGL, and the first non-operating level refers to a first low level; the second non-operating level terminal is a second low level terminal VGL, and the second non-operating level terminal is a second low level.
FIG. 1 is a schematic diagram of an exemplary shift register structure; FIG. 2 is a circuit diagram of the shift register shown in FIG. 1; as shown in fig. 1 and 2, the shift register includes an input sub-circuit 1, an output sub-circuit 3, a reset sub-circuit 7, a pull-down control sub-circuit 2, a pull-down sub-circuit 5, a first noise reduction sub-circuit 4, and a second noise reduction sub-circuit 6. Wherein the input sub-circuit 1 comprises a first transistor M1; the reset sub-circuit 7 includes a second transistor M2; the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1; the pull-down control sub-circuit 2 includes a transistor M5; the pull-down sub-circuit 5 includes a sixth transistor M6 and a seventh transistor M7; the first noise reduction sub-circuit 4 comprises an eighth transistor M8; the second noise reduction sub-circuit 6 comprises a fourth transistor M4.
Specifically, the drain and the gate of the first transistor M1 are connected to the signal Input, and the source of the first transistor M1 is connected to the pull-up node PU. The drain of the third transistor M3 is connected to the clock signal terminal CLK, the gate of the third transistor M3 is connected to the first terminal of the storage capacitor C1 and the pull-up node PU, and the source of the third transistor M3 is connected to the second terminal of the storage capacitor C1 and the signal output terminal Gout. The drain of the second transistor M2 is connected to the pull-up node PU, the gate of the second transistor M2 is connected to the Reset signal terminal Reset, and the source of the second transistor M2 is connected to the first non-operating level terminal LVGL. The drain and gate of the fifth transistor M5 are connected to the first power voltage terminal VDD, and the source of the fifth transistor M5 is connected to the pull-down node PD. The drain of the fourth transistor M4 is connected to the second terminal of the storage capacitor C1 and the signal output terminal Gout, the gate of the fourth transistor M4 is connected to the pull-down node PD, and the source of the fourth transistor M4 is connected to the second non-operating level terminal VGL. The drain of the eighth transistor M8 is connected to the pull-up node PU, the gate of the eighth transistor M8 is connected to the pull-down node PD, and the source of the eighth transistor M8 is connected to the first low-level terminal LVGL. The drain of the sixth transistor M6 is connected to the pull-down node PD, the gate of the sixth transistor M6 is connected to the pull-up node PU, and the source of the sixth transistor M6 is connected to the first non-operating level terminal LVGL. The drain of the seventh transistor M7 is connected to the pull-down node PD, the gate of the seventh transistor M7 is connected to the Input signal terminal Input, and the source of the seventh transistor M7 is connected to the first low-level terminal LVGL.
For the shift register shown in fig. 2, the specific operation process may include the following stages:
a pre-charging stage: the signal Input terminal Input inputs a high level signal, the first transistor M1 is turned on, and the high level signal Input by the signal Input terminal Input at this time precharges the pull-up node PU and stores the high level signal through the storage capacitor C1.
An output stage: the signal Input inputs a low level signal, and the first transistor M1 is turned off. At this time, since the storage capacitor C1 is charged in the precharge stage, the potential of the pull-up node PU is further pulled high; since the gate of the third transistor M3 is connected to the pull-up node PU, the third transistor M3 is turned on, and the output signal terminal Gout outputs the clock signal of the clock signal terminal CLK as an output signal. At this time, the clock signal is a high level signal, and the output signal is also a high level signal.
A reset stage: the signal Input terminal Input inputs a low level signal, and the first transistor M1 is turned off. At this time, the Reset signal terminal Reset inputs a high level signal, the second transistor M2 is turned on, the pull-up node PU is written with the first low level signal of the first low level terminal LVGL, and the potential of the pull-up node PU is Reset.
And a noise reduction stage: the signal Input terminal Input inputs a low level signal, and the first transistor M1 is turned off. The Reset signal terminal Reset inputs a low level signal and the second transistor M2 is turned off. At this time, the potential of the pull-up node PU maintains the potential at the reset stage, which is the second low level potential. At this time, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the pull-down node PD maintain the operation state of the reset stage. The pull-up node PU and the signal output Gout are continuously denoised.
The inventor finds that: on one hand, in the pre-charging stage, the sixth transistor M6 and the seventh transistor M7 are turned on simultaneously, and divide the voltage with the fifth transistor M5; however, in the output phase, the seventh transistor M7 is turned off, and the sixth transistor M6 alone and the fifth transistor M5 divide the voltage, which causes the pull-down node PD to rise, and Vgs (gate-source voltage) >0 of the eighth transistor M8, which causes the pull-up node PU to leak through the eighth transistor M8.
On the other hand, when an oxide thin film transistor having higher mobility is selected, Vth (threshold voltage) of the thin film transistor is unstable, and the eighth transistor M8 is liable to negative bias fluctuation. When the eighth transistor M8 fluctuates negatively, the pull-up node PU is caused to leak through the eighth transistor M8.
In order to solve the above problems, the inventor improves the original shift register and provides the following technical solutions:
as shown in fig. 3 and 4, an embodiment of the present disclosure provides a structure of a shift register, which includes an input sub-circuit 1, an output sub-circuit 3, a pull-down control sub-circuit 2, a pull-down sub-circuit 5, a first noise reduction sub-circuit 4, a first auxiliary control sub-circuit 8, and a second auxiliary control sub-circuit 9.
The input sub-circuit 1 is configured to charge a pull-up node PU under the control of an input signal; the pull-up node PU is a connection node between the input sub-circuit 1, the output sub-circuit 3, the first noise reduction sub-circuit 4, the first auxiliary control sub-circuit 8 and the pull-down sub-circuit 5; the output sub-circuit 3 is configured to pull up the output of the signal output terminal Gout by a clock signal under the potential control of the pull-up node PU; the pull-down control sub-circuit 2 is configured under the control of the first power voltage, and controls the potential of the pull-down node PD by the first power voltage; the pull-down node PD is a connection node between the pull-down control sub-circuit 2, the pull-down sub-circuit 5, the first noise reduction sub-circuit 4, and the second noise reduction sub-circuit 6; the pull-down sub-circuit 5 is configured to pull down the potential of the pull-down node PD by a first low-level signal under the control of the potential of the pull-up node PD; the first auxiliary control sub-circuit 8 is configured to write a second low level into the control node PC and control the first noise reduction sub-circuit 4 to turn off when the pull-down node PD is a first low level; wherein, the control node PC is a connection node between the first noise reduction sub-circuit 4, the first auxiliary control sub-circuit 8 and the second auxiliary control sub-circuit 9; the second auxiliary control sub-circuit 9 is configured to write a first low level into the control node PC when the potential of the pull-down node PD is the first power voltage, so as to control the first noise reduction sub-circuit 4 to reduce the noise of the pull-up node PD by the first low level.
Due to the fact that the first auxiliary control sub-circuit 8 and the second auxiliary control sub-circuit 9 are added in the shift register of the embodiment of the disclosure, when the pull-up node PU is at a high level, the pull-down node PD is at a first low level, the control node PC is at a second low level, and by controlling the voltage of the first low level and the voltage of the second low level, the working state of the first noise reduction sub-circuit 4 is controlled, and further the potential of the pull-up node PU is prevented from being influenced by leakage of the first noise reduction sub-circuit 4. Meanwhile, when the potential of the pull-down node PD is at a high level, the second auxiliary control sub-circuit 9 and the first noise reduction sub-circuit 4 both operate, and at this time, noise reduction is performed on the pull-up node PU through a second low level, that is, noise reduction of the pull-up node PU is also achieved.
In some examples, fig. 4 is a circuit diagram of a shift register of an embodiment of the present disclosure; as shown in fig. 4, the input sub-circuit 1 may include a first transistor M1; the drain and gate of the first transistor M1 are connected to the Input signal terminal Input, and the source of the first transistor M1 is connected to the pull-up node PU.
In this case, in the Input phase, a high signal is written to the signal Input terminal Input, and the pull-up node PU is precharged.
In some examples, with continued reference to fig. 4, the output sub-circuit 3 may include a third transistor M3 and a storage capacitor C1; the drain of the third transistor M3 is connected to the clock signal terminal CLK, the gate of the third transistor M3 is connected to the pull-up node PU and the first terminal of the storage capacitor C1, and the source of the third transistor M3 is connected to the output signal terminal Gout and the second terminal of the storage capacitor C1.
In this case, when the potential of the pull-up node PU is at a high level, the third transistor M3 is turned on, outputting the clock signal of the clock signal terminal CLK to the output signal terminal Gout. In the output stage, the clock signal at the clock signal terminal CLK is at a high level, and the potential of the signal output terminal Gout is pulled high at this time, that is, a high level signal is output.
In some examples, with continued reference to fig. 4, the pull-down control sub-circuit 2 includes a fifth transistor M5; the drain and gate of the fifth transistor M5 are connected to the first power voltage terminal VDD, and the source of the fifth transistor M5 is connected to the pull-down node PD.
In this case, since the drain and the gate of the fifth transistor M5 are connected to the first power voltage terminal VDD, i.e., are written to the first power voltage, at this time, the fifth transistor M5 is turned on, and the potential of the pull-down node PD is the potential of the first power voltage, i.e., the potential of the pull-down node PD is at a high level.
In some examples, with continued reference to fig. 4, the pull-down sub-circuit 5 includes a sixth transistor M6 and a seventh transistor M7; the drain of the sixth transistor M6 is connected to the pull-down node PD. The drain of the sixth transistor M6 is connected to the pull-up node PU, and the source of the sixth transistor M6 is connected to the first low-level terminal LVGL. The drain of the seventh transistor M7 is connected to the pull-down node PD, the gate of the seventh transistor M7 is connected to the pull-up node PU, and the source of the seventh transistor is connected to the first low-level terminal LVGL.
In this case, since the gate of the seventh transistor M7 is connected to the pull-up node PU instead of being connected to the Input signal terminal Input, the pull-down node PD is pulled down more sufficiently, and the potential of the pull-down node PD is closer to the first low level, which finally results in that the first noise reduction sub-circuit 4 is not turned on due to the excessively high voltage of the pull-down node PD, and the pull-up node PU leaks electricity. When the pull-up node PU is at a high level, the sixth transistor M6 and the seventh transistor M7 are turned on, the sixth transistor M6 and the seventh transistor M7 constitute a parallel circuit, and the pull-down node PD is pulled down to a first low level. Since the first power voltage passes through the series circuit of the fifth transistor M5, the pull-down node PD, and the parallel circuit, the smaller the circuit resistance connected to the fifth transistor M5, the closer the potential of the pull-down node PD is to the potential of the first low level according to ohm's law. Since the resistance of the parallel circuit of the sixth transistor M6 and the seventh transistor M7 is smaller than the circuit resistance of only the sixth transistor M6, the potential of the pull-down node PD is pulled down more sufficiently, and the potential of the pull-down node PD is closer to the written first low level.
In some examples, with continued reference to fig. 4, the first noise reduction sub-circuit 4 includes an eighth transistor M8; the drain of the eighth transistor M8 is connected to the pull-up node PU, the gate of the eighth transistor M8 is connected to the pull-down node PD, and the source of the eighth transistor is connected to the control node PC.
In this case, when the pull-down node PD is at a high level, the eighth transistor M8 and the second auxiliary control sub-circuit 9 are both turned on, and due to the turning on of the second auxiliary control sub-circuit 9, a first low level is written into the control node PC, and at the same time, the eighth transistor M8 is turned on, and the potential of the pull-up node PU is the potential of the control node PC, that is, the potential of the pull-up node PU is pulled down to the first low level, thereby achieving noise reduction of the pull-up node PU. For convenience of understanding, the first noise reduction sub-circuit 4 including the eighth transistor M8 is described as an example in the following description.
In some examples, with continued reference to fig. 4, the second auxiliary control sub-circuit 9 includes a ninth transistor M9; the drain of the ninth transistor M9 is connected to the control node PC, the gate of the ninth transistor M9 is connected to the pull-down node PD, and the source of the ninth transistor M9 is connected to the first low-level terminal LVGL.
In this case, when the pull-down node PD is at a high level, the eighth transistor M8 and the ninth transistor M9 are both turned on, and the potential of the control node PC is written by the pull-up node PU, so that noise reduction of the pull-up node PU is achieved.
In some examples, with continued reference to fig. 4, the first auxiliary control sub-circuit 8 includes a tenth transistor M10; the drain of the tenth transistor M10 is connected to the control node PC, the gate of the tenth transistor M10 is connected to the pull-up node PU, and the source of the tenth transistor M10 is connected to the second low level terminal VGL.
In this case, when the pull-up node PU is at the high level, the tenth transistor M10 is turned on, and the potential of the control node PC is at the written second low level. At this time, the source potential of the eighth transistor M8 is the second low level VGL (e.g., -8V), the gate potential of the eighth transistor M8 is the potential of the pull-down node PD, that is, the first low level potential LVGL (e.g., -11V), Vgs of the eighth transistor M8 is LVGL-VGL <0, so that the eighth transistor M8 is in an off state, and the pull-up node PU does not leak current due to negative bias fluctuation.
FIG. 5 is a schematic diagram of another shift register according to an embodiment of the present disclosure; as shown in fig. 5, the shift register is different from the shift register shown in fig. 3 in that a reset sub-circuit 7 and a second noise reduction sub-circuit 6 are further included in the shift register. It should be noted that the shift register may include only one of the reset sub-circuit 7 and the second noise reduction sub-circuit 6, and fig. 5 illustrates the shift register including the reset sub-circuit 7 and the second noise reduction sub-circuit 6 as an example. Wherein the reset sub-circuit 7 is configured to reset the pull-up node PU by a first low level under the control of a reset signal; the second noise reduction sub-circuit 6 is configured to reduce noise of the output signal terminal Gout by the second low level when the potential of the pull-down node PD is the first power supply voltage.
Since the reset sub-circuit 7 and the second noise reduction sub-circuit 6 are added to the shift register according to the embodiment of the present disclosure, when the reset signal is at a high level, the reset sub-circuit 7 operates, and at this time, the pull-up node PU is reset by the first low level. Meanwhile, when the potential of the pull-down node PD is at a high level, the second noise reduction sub-circuit 6 is controlled to operate, and at this time, the output signal is subjected to noise reduction by a second low level.
In some examples, fig. 6 is a circuit diagram of another shift register of an embodiment of the present disclosure; as shown in fig. 6, the reset sub-circuit 7 includes a second transistor M2; the drain of the second transistor M2 is connected to the pull-up node PU, the gate of the second transistor M2 is connected to the Reset signal terminal Reset, and the source of the second transistor M2 is connected to the first low level terminal LVGL.
In this case, in the Reset phase, a high level is input to the Reset signal terminal Reset, the second transistor M2 is turned on, and the first low level is written into the pull-up node PU. The voltage level of the pull-up node PU is pulled low, i.e., the voltage level of the pull-up node PU is the first low level. Thereby realizing the reset of the pull-up node PU.
In some examples, with continued reference to fig. 6, the second noise reduction sub-circuit 6 includes a fourth transistor M4; the drain of the fourth transistor M4 is connected to the output signal terminal, the gate of the fourth transistor M4 is connected to the pull-down node PD, and the source of the fourth transistor is connected to the second low level terminal VGL.
In this case, when the pull-down node PD is at a high level, the fourth transistor M4 is turned on, a second low level is written into the output signal terminal Gout, and the output signal of the output signal terminal Gout is pulled down to the second low level, thereby achieving noise reduction of the output signal. In order to make the structure of the shift register according to the embodiment of the present disclosure more clear, the operation principle of the shift register will be described below by taking the circuit diagram of the shift register shown in fig. 6 as an example. As shown in fig. 6, the shift register includes an input sub-circuit 1, an output sub-circuit 3, a pull-down control sub-circuit 2, a pull-down sub-circuit 5, a first noise reduction sub-circuit 4, a second noise reduction sub-circuit 6, a first auxiliary control sub-circuit 8, a second auxiliary control sub-circuit 9, and a reset sub-circuit 7. Wherein the input sub-circuit 1 comprises a first transistor M1; the reset sub-circuit 7 includes a second transistor M2; the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1; pull-down control sub-circuit 2 includes transistor M5; the pull-down sub-circuit 5 includes a sixth transistor M6 and a seventh transistor M7; the first noise reduction sub-circuit 4 comprises an eighth transistor M8; the second noise reduction sub-circuit 6 includes a fourth transistor M4; the first auxiliary control sub-circuit 8 comprises a tenth transistor M10; the second auxiliary control sub-circuit 9 comprises a ninth transistor M9.
Specifically, the gate and the drain of the first transistor M1 are connected to the Input signal terminal Input, and the source of the first transistor M1 is connected to the pull-up node PU. The third transistor M3 has a drain connected to the output clock signal terminal CLK, a gate connected to the first terminal of the storage capacitor C1 and the pull-up node PU, and a source connected to the output signal terminal Gout and the second terminal of the storage capacitor C1. The drain and gate of the fifth transistor M5 are connected to the first power voltage terminal VDD, and the source of the fifth transistor M5 is connected to the pull-down node PD. The drain of the sixth transistor M6 is connected to the pull-down node PD, the gate of the sixth transistor M6 is connected to the pull-up node PU, and the source of the sixth transistor M6 is connected to the first low-level terminal LVGL. The drain of the seventh transistor M7 is connected to the pull-down node PD, the gate of the seventh transistor M7 is connected to the pull-up node PU, and the source of the seventh transistor M7 is connected to the first low-level terminal LVGL. The drain of the eighth transistor M8 is connected to the pull-up node PU, the gate of the eighth transistor M8 is connected to the pull-down node PD, and the source of the eighth transistor M8 is connected to the control node PC. The drain of the tenth transistor M10 is connected to the control node PC, the gate of the tenth transistor M10 is connected to the pull-up node PU, and the source of the tenth transistor M10 is connected to the second low level terminal VGL. The drain of the ninth transistor M9 is connected to the control node PC, the gate of the ninth transistor M9 is connected to the pull-down node PD, and the source of the ninth transistor M9 is connected to the first low-level terminal LVGL. The drain of the second transistor M2 is connected to the pull-up node PU, the gate of the second transistor M2 is connected to the Reset signal terminal Reset, and the source of the second transistor M2 is connected to the first low level terminal LVGL.
A pre-charging stage: the signal Input terminal Input inputs a high level signal, the first transistor M1 is turned on, and the high level signal Input by the signal Input terminal Input at this time precharges the pull-up node PU and stores the high level signal through the storage capacitor C1.
An output stage: the signal Input terminal Input inputs a low level signal, and the first transistor M1 is turned off. At this time, since the storage capacitor C1 is charged during the precharge phase, the potential of the pull-up node PU is further pulled high. Since the gate of the third transistor M3 is connected to the pull-up node PU, the third transistor M3 is turned on, and the output signal terminal Gout outputs the clock signal of the clock signal terminal CLK as an output signal. At this time, the clock signal is a high level signal, and the output signal is also a high level signal.
A reset stage: the Reset signal written by the Reset signal terminal Reset is a high level signal, at this time, the second transistor M2 is turned on, the pull-up node PU is written with a first low level signal, that is, the potential of the pull-up node PU is a first low level, and at this time, the pull-up node PU is Reset.
And a noise reduction stage: the potential of the node PU is reset to the first low level due to the pull-up. The third transistor M3, the sixth transistor M6, the seventh transistor M7, and the tenth transistor M10 are turned off. The pull-down node PD is recharged, the potential of the pull-down node PD is pulled up to the first power voltage level, the eighth transistor M8 and the ninth transistor M9 are turned on, so that the pull-up node PU is written into the first low level, and the pull-up node PU is continuously denoised. And meanwhile, under the control of the pull-down node PD, the fourth transistor M4 is turned on, so that the signal output end Gout is written into the second low level, and the output signal is subjected to noise reduction.
On the other hand, the present embodiment further provides a gate driving circuit and a display device, wherein the gate driving circuit includes a plurality of cascaded arbitrary shift registers. When cascade connection is carried out, the signal input end of the shift register of the current stage is connected with the signal output end of the shift register of the first stage; the reset signal end of the shift register of the current stage is connected with the signal input end of the shift register of the next stage; the signal output end of the shift register of the current stage is connected with the signal input end of the next stage.
The display device includes the gate driving circuit, wherein the display device in this embodiment may be any product or component having a display function, such as an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (14)

1. A shift register, comprising: the device comprises an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, a first noise reduction sub-circuit, a first auxiliary control sub-circuit and a second auxiliary control sub-circuit; wherein,
the input sub-circuit is configured to charge a pull-up node under the control of an input signal; wherein the pull-up node is a connection node between the input sub-circuit, the output sub-circuit, the first noise reduction sub-circuit, the first auxiliary control sub-circuit, and the pull-down sub-circuit;
the output sub-circuit is configured to pull up the output of the signal output terminal by a clock signal under the control of the pull-up node potential;
the pull-down control sub-circuit is configured to be under the control of a first power supply voltage and control the potential of a pull-down node through the first power supply voltage; the pull-down node is a connection node among the pull-down control sub-circuit, the pull-down sub-circuit and the first noise reduction sub-circuit;
the pull-down sub-circuit is configured to pull down the potential of the pull-down node through a first non-operating level signal under the control of the potential of the pull-up node;
the first auxiliary control sub-circuit is configured to write a second non-working level into the control node and control the first noise reduction sub-circuit to be turned off when the pull-down node is at a first non-working level; wherein the control node is a connection node among the first noise reduction sub-circuit, the first auxiliary control sub-circuit and the second auxiliary control sub-circuit;
the second auxiliary control sub-circuit is configured to write the first non-operating level into a control node when the potential of the pull-down node is a first power supply voltage, so as to control the first noise reduction sub-circuit to reduce noise of the pull-up node through the non-first operating level.
2. The shift register of claim 1, further comprising: a reset sub-circuit configured to reset the pull-up node by the second non-operating level under control of a reset signal.
3. The shift register of claim 2, wherein the reset subcircuit comprises: a second transistor; wherein,
the first pole of the second transistor is connected with the pull-up node, the second pole of the second transistor is connected with the first non-working level end, and the control pole of the second transistor is connected with the reset signal end.
4. The shift register of claim 1, further comprising: a second noise reduction sub-circuit configured to reduce noise of the signal output terminal by the second non-operating level when the potential of the pull-down node is the first power supply voltage.
5. The shift register of claim 4, wherein the second noise reduction sub-circuit comprises: a fourth transistor; wherein,
and a first pole of the fourth transistor is connected with the signal output end, a second pole of the fourth transistor is connected with the second non-working level end, and a control pole of the fourth transistor is connected with the pull-down node.
6. The shift register of claim 1, wherein the input sub-circuit comprises: a first transistor; wherein,
and the first pole and the control pole of the first transistor are both connected with a signal input end, and the second pole of the first transistor is connected with the pull-up node.
7. The shift register according to claim 1, wherein the output sub-circuit includes a third transistor and a storage capacitor; wherein,
the first pole of the third transistor is connected with a clock signal end, the second pole of the third transistor is connected with the signal output end and the second end of the storage capacitor, and the control pole of the third transistor is connected with the first end of the storage capacitor and the pull-up node.
8. The shift register of claim 1, wherein the pull-down control subcircuit includes, a fifth transistor; wherein,
and a first pole and a control pole of the fifth transistor are connected with the first power supply voltage end, and a second pole of the fifth transistor is connected with the pull-down node.
9. The shift register of claim 1, wherein the pull-down sub-circuit comprises a sixth transistor and a seventh transistor, wherein:
a first pole of the seventh transistor is connected with the pull-down node, a second pole of the seventh transistor is connected with the second non-working level end, and a control pole of the seventh transistor is connected with the pull-up node;
and a first pole of the sixth transistor is connected with the pull-down node, a second pole of the sixth transistor is connected with the second non-working level end, and a control pole of the sixth transistor is connected with the pull-up node.
10. The shift register of claim 1, wherein the first noise reduction sub-circuit comprises an eighth transistor, wherein:
and a first pole of the eighth transistor is connected with the pull-up node, a second pole of the eighth transistor is connected with the control node, and a control pole of the eighth transistor is connected with the pull-down node.
11. The shift register of claim 1, wherein the first auxiliary control sub-circuit comprises a tenth transistor, wherein:
the tenth transistor has a first electrode connected to the control node, a second electrode connected to the second non-operating level terminal, and a control electrode connected to the pull-up node.
12. The shift register of claim 1, wherein the second auxiliary control sub-circuit comprises a ninth transistor, wherein:
and a first pole of the ninth transistor is connected with the control node, a second pole of the ninth transistor is connected with the first non-working level end, and a control pole of the ninth transistor is connected with the pull-down node.
13. A gate drive circuit comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 12.
14. A display device comprising the gate driver circuit according to claim 13.
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