CN113326140B - Process migration method, device, computing device and storage medium - Google Patents
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Abstract
The invention discloses a process migration method, a device, a computing device and a storage medium, wherein the process migration method is executed in the computing device and comprises the following steps: dividing each process into an active process or an inactive process based on the real load of each process in the processor; judging whether the active process is the only active process in the processor; if the process is not the only active process, sequentially determining task layering loads of the processes; and when the task layering load of the process meets the preset condition, migrating the process to other processors.
Description
Technical Field
The present invention relates to the field of the internet, and in particular, to a process migration method, a device, a computing device, and a storage medium.
Background
In a multi-core SMP (symmetric multiprocessor) system, reasonable task scheduling is an important premise for exploiting the potential of the multi-core system. Based on multi-core scheduling, a process queue is currently running on each processor. And one executable process can be added to other running queues to realize load balancing among the processors, so that the situation that one part of the processors are busy and the other part of the processors are idle is avoided.
The current load balancing implementation uses task layering load (task_h_load), namely considering the load contribution of the current process to the current processor, and judging whether a task can meet the migration condition according to the size of the task layering load. However, the existing process migration method has the following problems that in a full-load scene, the phenomenon that a high-load process is migrated across a processor or even across a memory node due to the influence of a background low-load process occurs, so that serious cache failure is caused, and the normal performance of the high-load process is further influenced.
Disclosure of Invention
The present invention has been made in view of the above problems, and provides a process migration method, apparatus, computing device, and storage medium that overcome or at least partially solve the above problems.
According to one aspect of the present invention, there is provided a process migration method, executed in a computing device, the method comprising: dividing each process into an active process or an inactive process based on the real load of each process in the processor; judging whether the active process is the only active process in the processor; if the process is not the only active process, sequentially determining task layering loads of the processes; and when the task layering load of the process meets the preset condition, migrating the process to other processors.
Optionally, in the process migration method according to the present invention, if the process is not the only active process, the step of sequentially determining task layering loads of the process includes: polling a linked list of each process stored in the processor to obtain the joining sequence of each process; and sequentially determining task layering loads of the processes according to the adding sequence of the processes from back to front.
Optionally, in the process migration method according to the present invention, after the step of dividing each process into an active process or an inactive process based on a real load of each process in the processor, the method further includes the step of: and counting the number of active processes in the processor.
Optionally, in the process migration method according to the present invention, the step of calculating the real load includes: respectively acquiring time information of each process in a working state and a non-working state; based on the time information, the real load of each process is calculated.
Optionally, in the process migration method according to the present invention, the step of calculating the task layering load includes: acquiring the number of processors of the process in the corresponding group; acquiring a process load of a process in a corresponding group; and taking the ratio of the load of the process to the number of the processors as the task layering load of the process.
Optionally, in the process migration method according to the present invention, the step of dividing each process into an active process or an inactive process based on a real load of each process in the processor includes: if the real load of the process is greater than a preset load threshold, determining that the process is an active process; otherwise, the process is determined to be an inactive process.
Optionally, in the process migration method according to the present invention, when the task layering load of the process meets a preset condition, the step of migrating the process to the other processor includes: judging whether the task layering load of the process is less than half of the load imbalance value or not; if yes, the process is migrated to other processors.
According to still another aspect of the present invention, there is provided a process migration apparatus including: the process state determining module is suitable for dividing each process into an active process or an inactive process based on the real load of each process in the processor; the judging module is suitable for judging whether the active process is the only active process in the processor; the process task layering load determining module is suitable for sequentially determining task layering loads of the processes; and a process migration module adapted to migrate the process to other processors.
According to yet another aspect of the present invention, there is provided a computing device comprising: at least one processor; and a memory storing program instructions, wherein the program instructions are configured to be adapted to be executed by the at least one processor, the program instructions comprising instructions for performing the above-described method.
According to yet another aspect of the present invention, there is provided a readable storage medium storing program instructions that, when read and executed by a computing device, cause the computing device to perform the above-described method.
According to the scheme of the invention, the dual effects of the real load of the task and the layered load of the task of the process are comprehensively considered, when only one process with high real load is arranged on the processor, the low-load process newly added to the processor is preferentially migrated, the migration of the process with high real load is avoided, and the normal performance of the process with high load is further ensured.
According to the scheme of the invention, under the full thread use case scene, the influence of the background process on the main process is reduced, the main process is not influenced by the background to cause process migration across processors and even across memory nodes, and at the moment, the utilization rate of the cache memory is highest, and the running performance of the program is also best.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
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Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 illustrates a schematic diagram of a principle 100 of process migration;
FIG. 2 illustrates a flow chart of a prior art process migration method 200;
FIG. 3 shows a schematic diagram of a computing device 300 according to one embodiment of the invention;
FIG. 4 illustrates a flow diagram of a process migration method 400 according to one embodiment of the invention.
Fig. 5 illustrates a block diagram of a process migration apparatus 500 according to one embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
An important part of load balancing is how to select the appropriate process in the processor process queue for migration. Specifically, the load of the processor process queue is the sum of the loads of all the processes on the process queue, the load of one process is related to the actual running time of the process, and the longer the substantially continuous running time is, the higher the load is. The goal of load balancing is therefore to utilize the processor power resources as much as possible, allowing each process to get sufficient processor time. To achieve this goal, it is necessary to select an appropriate process (typically, a process with a smaller load is likely to satisfy the migration condition) to migrate to a relatively idle processor from a busy processor with a relatively large number of processes in the run queue and a relatively large total load.
As shown in fig. 1, fig. 1 shows a schematic diagram of a principle 100 of process migration, where a process running in a processor 0 has a process 1, a process 2 and a process 3, and a process running in the processor 1 has a process 4. Processor 0 is a busy processor as compared to processor 1, and at this time, for example, process 3 in processor 0 may be migrated to processor 1 to implement load balancing of the system.
FIG. 2 illustrates a flow chart of one prior art implementation of a process migration method 200 that begins by sequentially polling each process on a busy processor after a process migration flow is initiated. And then judging whether the task layering load of the process meets the migration requirement. And finally, migrating the process meeting the migration requirement from the busy processor to the idle processor. The process migration method uses task layering load, namely considering load contribution of the current process to the current processor, and judging whether a task can meet migration conditions according to the size of the task layering load.
Under the condition that the task layering load starts group scheduling, the more tasks run in the same group, because the weight of one task group is a default value when not actively adjusted, the task weight averaged to one processor is smaller than a standard value, so that the task layering load (task_h_load) =task load/cpu number is caused, and at the moment, the background process load > =work process load is possible.
In one specific example, after the group dispatch is turned on, the full thread runs the specified program.
Process 1 (user process running continuously):
The system is positioned in a task group A, and 10 processes in the group are distributed on 10 processors;
process load task_load=1000;
The hierarchical load task_h_load=1000/10=100 of the process.
Process 2 (background process running periodically):
The system is positioned in a task group B, and 1 process in the group is distributed on 1 processor;
Process load task_load=120;
the hierarchical load task_h_load=120/1=120 of the process.
In this case, the hierarchical load of the background process > =the hierarchical load of the working process, and the above-mentioned process with smaller load is easy to satisfy the migration condition, and when the plurality of tasks on one processor all satisfy the migration condition, the migration is performed according to the order of adding the tasks into the running queue, and the process added into the running queue is preferentially migrated, so that the user process that normally runs continuously is migrated. In a full load scenario, a phenomenon that a high-load process is migrated across processors and even across memory nodes due to the influence of a background low-load process can occur, which can cause serious cache failure, thereby affecting the normal performance of the high-load process.
The technical scheme of the invention is provided for solving the problems in the prior art. One embodiment of the present invention provides a process migration method that may be performed in a computing device. In particular, FIG. 3 illustrates a block diagram of a computing device 300 according to one embodiment of the invention. As shown in FIG. 3, in a basic configuration 302, computing device 300 typically includes a system memory 306 and one or more processors 304. A memory bus 308 may be used for communication between the processor 304 and the system memory 306.
Depending on the desired configuration, processor 304 may be any type of processing, including, but not limited to: a microprocessor (μp), a microcontroller (μc), a digital information processor (DSP), or any combination thereof. Processor 304 may include one or more levels of cache, such as a first level cache 310 and a second level cache 312, a processor core 314, and registers 316. The example processor core 314 may include an Arithmetic Logic Unit (ALU), a Floating Point Unit (FPU), a digital signal processing core (DSP core), or any combination thereof. The example memory controller 318 may be used with the processor 304 or, in some implementations, the memory controller 318 may be an internal part of the processor 304.
Depending on the desired configuration, system memory 306 may be any type of memory including, but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. Physical memory in a computing device is often referred to as volatile memory RAM, and data in disk needs to be loaded into the physical memory in order to be read by processor 304. The system memory 306 may include an operating system 320, one or more applications 322, and program data 324. The application 322 is in effect a plurality of program instructions for instructing the processor 304 to perform a corresponding operation. In some implementations, the application 322 may be arranged to execute instructions on an operating system by the one or more processors 304 using the program data 324 in some implementations. Operating system 320 may be, for example, linux, windows or the like, which includes program instructions for handling basic system services and performing hardware-dependent tasks. The application 322 includes program instructions for implementing various functions desired by the user, and the application 322 may be, for example, a browser, instant messaging software, a software development tool (e.g., integrated development environment IDE, compiler, etc.), or the like, but is not limited thereto. When an application 322 is installed into computing device 300, a driver module may be added to operating system 320.
When the computing device 300 starts up running, the processor 304 reads the program instructions of the operating system 320 from the memory 306 and executes them. Applications 322 run on top of operating system 320, utilizing the interfaces provided by operating system 320 and the underlying hardware to implement various user-desired functions. When a user launches the application 322, the application 322 is loaded into the memory 306, and the processor 304 reads and executes the program instructions of the application 322 from the memory 306.
Computing device 300 also includes storage device 332, storage device 332 includes removable storage 336 and non-removable storage 338, both removable storage 336 and non-removable storage 338 being connected to storage interface bus 334.
Computing device 300 may also include an interface bus 340 that facilitates communication from various interface devices (e.g., output devices 342, peripheral interfaces 344, and communication devices 346) to basic configuration 302 via bus/interface controller 330. The example output device 342 includes a graphics processing unit 348 and an audio processing unit 350. They may be configured to facilitate communication with various external devices such as a display or speakers via one or more a/V ports 352. Example peripheral interfaces 344 may include a serial interface controller 354 and a parallel interface controller 356, which may be configured to facilitate communication via one or more I/O ports 358 and external devices, such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripheral devices (e.g., printer, scanner, etc.). The example communication device 346 may include a network controller 360, which may be arranged to facilitate communication with one or more other computing devices 362 via one or more communication ports 364 over a network communication link.
The network communication link may be one example of a communication medium. Communication media may typically be embodied by computer readable instructions, data structures, program modules, and may include any information delivery media in a modulated data signal, such as a carrier wave or other transport mechanism. A "modulated data signal" may be a signal that has one or more of its data set or changed in such a manner as to encode information in the signal. By way of non-limiting example, communication media may include wired media such as a wired network or special purpose network, and wireless media such as acoustic, radio Frequency (RF), microwave, infrared (IR) or other wireless media. The term computer readable media as used herein may include both storage media and communication media.
Computing device 300 also includes a storage interface bus 334 that is coupled to bus/interface controller 330. The storage interface bus 334 is connected to the storage device 332, and the storage device 332 is adapted to store data. Example storage devices 332 may include removable storage 336 (e.g., CD, DVD, U-disk, removable hard disk, etc.) and non-removable storage 338 (e.g., hard disk drive HDD, etc.).
In computing device 300 according to the present invention, application 322 includes a plurality of program instructions that perform method 400.
FIG. 4 illustrates a flow diagram of a process migration method 400 according to one embodiment of the invention. The method 400 is suitable for execution in a computing device (e.g., the computing device 300 described previously).
As shown in fig. 4, the purpose of the method 400 is to implement a process migration method, beginning with step S402, in which each process is divided into an active process or an inactive process based on the actual load of each process in the processor.
It should be noted that, according to the embodiment of the present invention, before the step S402 is executed, it is already determined that there is a load imbalance in the computing device at this time, and the process on the processor needs to be migrated, and the determination of the load imbalance may be known based on the foregoing or the existing load balancing policy, which is not described herein.
It should be further noted that, the process migration method provided in this embodiment is applicable to a scenario where each process runs at or near the full load in the processor, that is, the occupancy rate of the processor is near 100%.
Preferably, the actual load of the process can be calculated by the following steps.
Step S422, respectively obtaining time information of each process in the working state and the non-working state.
The process is intermittently executed, and after a period of time, the processor stops running the process for a period of time, and changes to running other processes, and when other processes are stopped running, the processor re-runs the process, and the time when the process is in a working state is the running time of the process.
In step S424, the actual load of each process is calculated based on the time information.
The load of a process is the accumulation of a plurality of runtimes, while the load in the previous runtime is required to decay, the decay factor is related to the time that the process is in a non-working state.
The real load is calculated according to the time of the process in each operation interval and the attenuation coefficient of each operation interval, for example, the process runs for 3 time intervals before the current time, and then the real load of the process= (first time interval x first attenuation coefficient) + (second time interval x second attenuation coefficient) + (third time interval x third attenuation coefficient).
And comparing the real load of the process with a preset load threshold value after obtaining the real load of the process, and judging that the process is an active process when the real load of the process is larger than the load threshold value, or else, judging that the process is an inactive process. The setting of the load threshold may be performed by a person skilled in the art or according to the attribute of the computing device, which is not limited in this embodiment.
In step S404, it is determined whether the active process is the only active process in the processor. In step S402, the state of each process (active process or inactive process) in the processor is already determined by the real load of each process, and it may be directly determined whether the target process is the only active process in the processor.
It should be noted that when the process is the only active process in the processor, the process is skipped directly, in other words, when the process is the only process in the processor, the migration of the process is abandoned.
Of course, to facilitate determining the number of active processes in the processor, the number of active processes in the processor may be counted before executing step S404.
In step S406, if it is not the only active process, the task layering loads of the processes are sequentially determined. Polling determines the task layering load of each process on the processor, starting with the process that later joins the run queue.
Specifically, polling a linked list of each process stored in a processor to obtain the joining sequence of each process; and sequentially determining task layering loads of the processes according to the adding sequence of the processes from back to front.
The process can be put into the table head position of the appointed linked list after being added into the process queue, so that the process can be polled according to the time of adding the process queue from the head of the linked list, that is to say, the adding sequence of the process can be known through polling the linked list.
In some embodiments, the task load for each process is calculated as follows: acquiring the number of processors of the process in the corresponding group; acquiring a process load of a process in a corresponding group; and taking the ratio of the load of the process to the number of the processors as the task layering load of the process.
The task load calculating step is applicable to a scenario that each process in the group runs at or near the full load on the processor.
In one specific example, the conventional task layering load is calculated as follows:
task layered load = real load of process. Upper queue relative top layer load/upper queue load;
Thus, task hierarchical load/task real load = upper queue relative top layer load/upper queue load = current cpu group entity weight/1024 = current process load/total load of all processes within the group;
so when each process runs at full load, the load is the same and the total load of all processes in the current process load/group is approximately 1/total number of processors.
In other words, when each process in the packet runs at or near full load on the processor, the task hierarchical load of each process=process load/number of processors of that process in the corresponding packet.
In one particular example, processes are located within task group 0, a total of 5 processors are distributed within the group, and each process within task group 0 is running at full load. Load of the process=10; the task layering load of the process=10/5=2.
In step S408, when the task layering load of the process satisfies a preset condition, the process is migrated to the other processor.
Specifically, a load imbalance value is calculated based on a current load value of the computing device. And judging whether the task layering load of the process is less than half of the load imbalance value. If yes, the process is migrated to other processors.
It should be noted that, the load value of the computing device is not a fixed value, and changes with the running of each process, and thus, the load imbalance value also changes from time to time. In summary, the smaller the task layering load, the easier the migration condition is satisfied.
Fig. 5 illustrates a block diagram of a process migration apparatus 500 according to one embodiment of the present invention.
As shown in fig. 5, the apparatus 500 includes a state determination module adapted to divide each process into an active process or an inactive process based on a real load of each process in the processor; the judging module is suitable for judging whether the active process is the only active process in the processor; the task layering load determining module is suitable for sequentially determining task layering loads of the processes; and a migration module adapted to migrate the process to the other processor.
It should be noted that, the principle and workflow of the process migration apparatus provided in this embodiment are similar to those of the foregoing process migration method, and the relevant points may be described with reference to the foregoing process migration method, which is not repeated herein.
In the embodiment, on the task migration standard of load balancing, the dual effects of the real load of the task and the layered load of the task are comprehensively considered, and when only one process with high real load is arranged on the processor, the low-load process newly added to the processor is preferentially migrated. Under the full thread use case scene, the influence of a background process on a main process is reduced, the main process is not influenced by the background to cause process migration across processors and even across memory nodes, at the moment, the cache memory utilization rate is highest, and the program running performance is also best.
The various techniques described herein may be implemented in connection with hardware or software or, alternatively, with a combination of both. Thus, the methods and apparatus of the present invention, or certain aspects or portions of the methods and apparatus of the present invention, may take the form of program code (i.e., instructions) embodied in tangible media, such as removable hard drives, U-drives, floppy diskettes, CD-ROMs, or any other machine-readable storage medium, wherein, when the program is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
In the case of program code execution on programmable computers, the computing device will generally include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. Wherein the memory is configured to store program code; the processor is configured to perform the method of the invention in accordance with instructions in said program code stored in the memory.
By way of example, and not limitation, readable media comprise readable storage media and communication media. The readable storage medium stores information such as computer readable instructions, data structures, program modules, or other data. Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Combinations of any of the above are also included within the scope of readable media.
In the description provided herein, algorithms and displays are not inherently related to any particular computer, virtual system, or other apparatus. Various general-purpose systems may also be used with examples of the invention. The required structure for a construction of such a system is apparent from the description above. In addition, the present invention is not directed to any particular programming language. It should be appreciated that the teachings of the present invention as described herein may be implemented in a variety of programming languages and that the foregoing description of specific languages is provided for disclosure of preferred embodiments of the present invention.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed as reflecting the intention that: i.e., the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in a device as described in this embodiment, or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may be further divided into a plurality of sub-modules.
Those skilled in the art will appreciate that the modules in the apparatus of the embodiments may be adaptively changed and disposed in one or more apparatuses different from the embodiments. The modules or units or components of the embodiments may be combined into one module or unit or component and, furthermore, they may be divided into a plurality of sub-modules or sub-units or sub-components. Any combination of all features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or units of any method or apparatus so disclosed, may be used in combination, except insofar as at least some of such features and/or processes or units are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.
Furthermore, some of the embodiments are described herein as methods or combinations of method elements that may be implemented by a processor of a computer system or by other means of performing the functions. Thus, a processor with the necessary instructions for implementing the described method or method element forms a means for implementing the method or method element. Furthermore, the elements of the apparatus embodiments described herein are examples of the following apparatus: the apparatus is for carrying out the functions performed by the elements for carrying out the objects of the invention.
As used herein, unless otherwise specified the use of the ordinal terms "first," "second," "third," etc., to describe a general object merely denote different instances of like objects, and are not intended to imply that the objects so described must have a given order, either temporally, spatially, in ranking, or in any other manner.
While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of the above description, will appreciate that other embodiments are contemplated within the scope of the invention as described herein. Furthermore, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is defined by the appended claims.
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| CN113326140B (en) * | 2021-06-30 | 2024-11-26 | 统信软件技术有限公司 | Process migration method, device, computing device and storage medium |
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| CN114942791A (en) * | 2022-05-26 | 2022-08-26 | 统信软件技术有限公司 | Process awakening method and device, computing device and readable storage medium |
| CN115857418B (en) * | 2023-02-28 | 2023-05-02 | 深圳华龙讯达信息技术股份有限公司 | Programmable logic control system based on coupling design |
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| CN113326140B (en) * | 2021-06-30 | 2024-11-26 | 统信软件技术有限公司 | Process migration method, device, computing device and storage medium |
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| CN109766180A (en) * | 2017-11-09 | 2019-05-17 | 阿里巴巴集团控股有限公司 | Load-balancing method and device, calculate equipment and computing system at storage medium |
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