CN113314529A

CN113314529A - Integrated circuit device

Info

Publication number: CN113314529A
Application number: CN202011313663.0A
Authority: CN
Inventors: 黄乾燿; 林文傑; 陈国基
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-02-27
Filing date: 2020-11-20
Publication date: 2021-08-27

Abstract

An integrated circuit device includes a plurality of first well tap cells of a first semiconductor type, and a plurality of second well tap cells of a second semiconductor type different from the first semiconductor type. The plurality of first well tap cells are arranged in at least two columns adjacent to each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first well tap cells has a first length in a first direction. The plurality of second well tap units includes at least one second well tap unit that is greater than the first length of each of the plurality of first well tap units in the first direction The second length, between at least two columns, extends in the first direction.

Description

Integrated circuit device

Technical Field

The present disclosure relates to integrated circuit devices, and more particularly, to integrated circuit devices having well tap cells of different semiconductor types.

Background

An Integrated Circuit (IC) typically includes many semiconductor devices represented in an IC layout. The IC layout is hierarchical and includes modules that perform higher-order functions according to the design specifications of the semiconductor device. A module is typically constructed from a combination of cells, each of which represents one or more semiconductor structures designed to perform a particular function. Units having a preset layout are sometimes referred to as standard cells, which are stored in a standard cell library (hereinafter "library" or "cell library" for simplicity) and are accessible by various tools, such as Electronic Design Automation (EDA) tools, to generate, optimize, and verify designs for ICs.

Disclosure of Invention

According to an embodiment of the present disclosure, an integrated circuit device is disclosed that includes a plurality of first well tap units of a first semiconductor type and a plurality of second well tap units of a second semiconductor type different from the first semiconductor type. The plurality of first well tap units are arranged in at least two columns, the at least two columns being adjacent to each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first well tap cells has a first length in a first direction. The plurality of second well tap units includes at least one second well tap unit extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first well tap units in the first direction.

Drawings

Aspects of one embodiment of the disclosure are better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A is a schematic diagram of an IC layout according to some embodiments;

fig. 1B is a schematic enlarged view of a portion of an IC layout according to some embodiments;

fig. 1C is a schematic cross-sectional view in combination with a schematic circuit diagram of an IC device according to some embodiments;

FIG. 2 is a schematic diagram of an IC layout according to some embodiments;

FIG. 3A is a schematic diagram of an IC layout according to some embodiments;

FIG. 3B is a schematic diagram of an IC layout according to some embodiments;

FIG. 4A is a schematic diagram of an IC layout according to some embodiments;

fig. 4B is a schematic cross-sectional view in combination with a schematic circuit diagram of an IC device according to some embodiments;

FIG. 5 is a flow diagram of a method of generating an IC layout according to some embodiments;

fig. 6 is a perspective view of an exemplary transistor having fin features according to some embodiments;

FIG. 7 is a block diagram of an EDA system according to some embodiments;

FIG. 8 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated with the IC manufacturing system, in accordance with some embodiments.

[ notation ] to show

A is unit height

A1 height

A2 height

Pitch of CPP

d is interval

DX (first distance)

2 DY is the second distance

L', L is length

L_ODLength of

m is length

Q1(PNP), Q2(NPN), Q2 '(PNP), Q1' (NPN): (parasitic) transistors

W is height

R_NW,R_PWResistor

R_Psub,R_NsubResistor

Y → Y1, Y '→ Y1': arrow

100 IC layout

110-

115 NTAP unit

115' PTAP unit

118,119 column (b)

120 second TAP unit

121 second TAP Unit, PTAP Unit

121' NTAP unit

122 first end

123 second end

124 middle part

130,132,134,136 first well region, N-well

134 ', 136' P well

130' well region

131,133,135,137,139 second well region, P-well

137 ', 139' N trap

140 part (C)

141 well region

142 OD region

143,144 gate region

150, 150' IC device

151, 151' substrate

151P-type substrate

151' N type substrate

152, 153P type active region

152 ', 153' N type active region

155, 156N type active region

155 ', 156' P type active region

154,154 ', 157,157' gate region

158, 158' isolation region

VDD first supply voltage

VSS second supply voltage

PMOS-P channel MOS

NmOS-N channel MOS

200 IC layout

201-20n part

300A,300B IC layout

310 first TAP unit

320,321 second TAP unit

318,319,328,329 column (B)

330,331: series

332,333,334,335 second TAP unit

400 IC layout

500 method

505,515 operation

600 circuit element

602 substrate

604 Fin characteristics (Or Fin)

606 Gate dielectric

608 Gate electrode

610 source region

612 drain region

EDA System 700

702 hardware processor, processor

704 (non-transitory) computer readable storage medium, memory

706 computer program code (Instructions)

707 library, Standard cell library (including Standard cells)

708 bus line

710I/O interface

712 network interface

714 network

742 user interface/UI

800 Integrated Circuit (IC) manufacturing System

820 design factory

822 IC design layout diagram

830 mask factory

832 data preparation

844 mask making

845 shade

850 IC manufacturer/manufacturer, (IC) manufacture

852 wafer fabrication

853 semiconductor wafer

860 IC device

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, configurations, etc., are described below to simplify one embodiment of the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, values, operations, materials, configurations, etc. are contemplated. For example, formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below … …," "below … …," "below," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

A well TAP cell (well TAP cell), referred to herein as a "TAP cell," is a standard cell that defines a region in a doped well, where the doped well is coupled to a bias voltage, such as a supply voltage. The TAP unit is included in the IC layout to improve latch-up immunity of ICs manufactured according to the IC layout.

With the current trend of scaling down semiconductor devices, the placement of TAP cells in IC layouts for manufacturing ICs raises one or more considerations, including but not limited to process bottlenecks due to reduced lithographic Critical Dimensions (CDs), and mixed channel effects. To address one or more of these considerations, in an IC layout according to some embodiments, first TAP units of a first semiconductor type (e.g., N-type or P-type) are disposed in rows and columns, and second TAP units of a different second semiconductor type (e.g., P-type or N-type) are disposed in an elongated configuration or strip shape across multiple columns of first TAP units. Thus, in at least one embodiment, it is possible to achieve one or more effects, including, but not limited to, relaxation of process constraints, an increase in latch immunity, a decrease in the area occupied or blocked by the TAP unit, and an increase in the area in which standard cells other than the TAP unit can be disposed.

Fig. 1A is a schematic diagram of an IC layout 100 of an IC device according to some embodiments. The IC layout 100 includes a plurality of

first TAP units

110 and 117 of a first semiconductor type and a plurality of

second TAP units

120 and 121 of a second semiconductor type different from the first semiconductor type. The

first TAP unit

110 and 117 are arranged in at least two

columns

118, 119. For example,

first TAP units

110, 112, 114, 116 are arranged in column 118, and

first TAP units

111, 113, 115, 117 are arranged in column 119. The columns 118,119 are adjacent to each other in a first direction, e.g., the X-direction, and extend in a second direction, e.g., the Y-direction, transverse to the first direction. At least one of the

second TAP units

120, 121 extends in the X direction between the columns 118,119 over a length L that is greater than the length L' of each of the

first TAP units

110 and 117 in the X direction. At least one of the

second TAP units

120, 121 overlaps at least one of the first TAP units in at least one of the columns 118,119 in the Y-direction along the page.

In the exemplary configuration in fig. 1A, the second TAP unit 120 is elongated in the X-direction and has a length L in the X-direction that is greater than its height in the Y-direction. The second TAP unit 120 overlaps the first TAP unit 110-117 in the Y-direction. For example, the second TAP unit 120 extends continuously in the X-direction from its first end 122 to its second end 123. The first ends 122 of the second TAP units 120 overlap the

first TAP units

110, 112, 114, 116 in the column 118 in the Y-direction. The second end 123 of the second TAP unit 120 overlaps the

first TAP units

111, 113, 115, 117 in column 119 in the Y-direction. The intermediate portion 124 of the second TAP unit 120 is between the first end 122 and the second end 123 and does not overlap any of the

first TAP units

110 and 117 in the Y-direction. The second TAP unit 121 has an elongated configuration similar to that described above with respect to the second TAP unit 120. The

second TAP units

120, 121 are adjacent to each other in the Y-direction, and no other TAP unit of the second semiconductor type is present between the

second TAP units

120, 121. The

second TAP units

120, 121 sandwich a plurality of rows and columns of the first TAP units, i.e., two columns 118,119, and four rows formed by the

first TAP units

110 and 111, the

first TAP units

112 and 113, the

first TAP units

114 and 115, and the

first TAP units

116 and 117, respectively.

The configuration described above with respect to fig. 1A is an example, and other configurations are within the scope of various embodiments. For example, some embodiments include a different number of first TAP units in each of columns 118,119 and/or a different number of rows of first TAP units sandwiched between each pair of adjacent

second TAP units

120, 121. In at least one embodiment, at least one of the

second TAP units

120, 121 has a configuration that is different from that described above with respect to fig. 1A. For example, at least one of the first end 122 or the second end 123 of the second TAP unit 120 does not overlap the

corresponding column

118 or 119 in the Y-direction. For another example, the

second TAP units

120, 121 have different lengths in the X direction. In another example, at least one of the

second TAP units

120, 121 is not a single second TAP unit that extends continuously in the X-direction as described with respect to fig. 1A, but instead includes a series of discrete second TAP units as described herein with respect to fig. 3B.

The IC layout 100 further includes a first well region 130,132,134,136 of the first semiconductor type and a plurality of second well regions 131,133,135,137,139 of the second semiconductor type. The first well regions 130,132,134,136 and the second well regions 131,133,135,137,139 extend in the X direction and are alternately arranged in the Y direction. Each of the

first TAP units

110 and 117 is in a corresponding one of the first well regions 130,132,134,136, and each of the

second TAP units

120, 121 is in a corresponding one of the second well regions 131,133,135,137, 139. For example,

first TAP units

110 and 111 are in first TAP unit 130,

first TAP units

112 and 113 are in first TAP unit 132,

first TAP units

114 and 115 are in first TAP unit 134, and

first TAP units

116 and 117 are in first TAP unit 136, while second TAP unit 120 is in second well region 131, and second TAP unit 121 is in second well region 139.

In the exemplary configuration in fig. 1A, the first semiconductor type is N-type and the second semiconductor type is P-type. In other words, the first well regions 130,132,134,136 are N-type well regions (hereinafter "N-well", the second well regions 131,133,135,137,139 are P-type well regions (hereinafter "P-well"), the first TAP unit 110-117 is an N-type TAP unit (hereinafter "NTAP unit"), and the

second TAP units

120, 121 are P-type TAP units (hereinafter "PTAP unit"). N-well is a region including an N-type dopant, and P-well is a region including a P-type dopant.

The NTAP cell is a region in the N-well but has a higher concentration of N-type dopant than the N-well itself. For example, the NTAP cell 110 has a higher concentration of N-type dopant than the N-well 130 in which the NTAP cell 110 is formed. The PTAP cell is a region in the P-well, but with a higher concentration of P-type dopants compared to the P-well itself. For example, the PTAP cell 120 has a higher concentration of P-type dopants compared to the P-well 131 of the PTAP cell 120.

In the N-well, a P-type active region with P-type dopants is disposed in an area not occupied or blocked by the NTAP cell to form one or more circuit elements. In the P-well, an N-type active region with N-type dopants is disposed in the region not occupied or blocked by the PTAP cell to form one or more circuit elements. Examples of circuit elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, Bipolar Junction Transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and/or N-channel field effect transistors (PFETs), etc.), FinFETs, planar MOS transistors with raised sources/drains, and the like. For example, in the N-wells 130,132,134,136, P-type active regions (not shown in fig. 1A, but described herein with respect to fig. 1C) are disposed in regions not occupied or blocked by the

NTAP cells

110 and 117 to define P-channel metal oxide semiconductor (PMOS) regions for forming PMOS transistors. In P-wells 133,135,137, N-type active regions (not shown in fig. 1A, but described herein with respect to fig. 1C) are disposed in regions not occupied or blocked by

PTAP cells

120, 121 to define N-channel metal oxide semiconductor (NMOS) regions for forming NMOS transistors. Cells having a preset layout are read from a cell library and disposed in the IC layout 100 such that the NMOS transistors of the cells are configured in the NMOS region and the PMOS transistors of the cells are configured in the PMOS region. The NTAP unit, the PTAP unit, the N-type active region and the P-type active region are sometimes collectively referred to as an oxide-definition (OD) region, and are schematically illustrated in FIG. 1B by the label "OD".

The IC layout 100 further includes gate regions (not shown in fig. 1A, but described herein with respect to fig. 1B) that include a conductive material, such as polysilicon, and are schematically illustrated in fig. 1B with the label "Poly (Poly)". Other conductive materials for the gate region, such as a metal, are within the scope of various embodiments. The gate region extends, or elongates, in the Y direction across the OD region. The Y direction is also referred to herein as multidirectional. In some embodiments, each OD region has one or more fin features disposed therein. Such fin features extend, or are elongated, in the X-direction and are spaced apart from each other in the Y-direction. The X direction is also referred to herein as the fin direction. Examples of fin features are described with respect to fig. 6.

In at least one embodiment, the number of fin features in each of the

first TAP units

110 and 117 and the number of fin features in each of the

second TAP units

120, 121 satisfy the following relationship:

F2/F1 ≥ (DY/DX)*(L/A) (1)

where F1 is the number of fin features in each of first TAP units 110-117, F2 is the number of fin features in each of

second TAP units

120, 121 elongated in the X direction, DX is half of a first distance 2X DX in the X direction between facing sides of the first TAP units in adjacent columns 118,119, DY is half of a second distance 2X DY in the Y direction between facing sides of the

second TAP units

120, 121, L is the length of the

second TAP unit

120 or 121 in the X direction, and a is the cell height in the Y direction and is the sum of the height a1 of the first well region (e.g., 132) and the height a2 of the adjacent second well region (e.g., 135).

In the exemplary configuration of fig. 1A, F1 is the number F of fin features in each NTAP cell_NTAPAnd F2 is the number of fin features F in each PTAP cell_PTAPAnd the relation (1) becomes

F_PTAP/F_NTAP≥(DY/DX)*(L/A) (1’)

By configuring the NTAP and PTAP cells to have different configurations and satisfy the relationship (1) or (1'), it is possible in some embodiments to match or improve latch-up (LUP) immunity indicators, as compared to another approach. Specifically, the LUP interference rejection index of the IC device corresponding to the IC layout 100 is determined by the following relationship

V＝Jbody*L*(A/2)*(2DY/A)*(Rc/F_PTAP) (2)

Where V is an index of the LUP immunity represented by a voltage drop caused by a leakage current Jbody in the IC device, and Rc is a unit resistance. The lower the voltage drop V, the better the LUP immunity of the IC device.

In another method in which the NTAP unit and the PTAP unit are configured similarly to each other and to the NTAP unit 110-

V’＝Jbody*2DX*(A/2)*(Rc/F_NTAP) (3)

In comparison to another approach, to match or improve the LUP immunity index, the following relationship will be satisfied:

V≤V’ (4)

based on the relationships (2), (3), and (4), the relationships (1') and (1) are obtained.

In some embodiments, the IC layout 100 satisfies at least one of: DY is from 0.5 μm to 1000 μm, DX is from 0.05 μm to 100 μm, L is from 0.1 μm to 5000 μm, or A is from 0.025 μm to 0.300. mu.m. The range of 0.025 μm to 0.300 μm of the cell height a corresponds to one or more considerations and/or constraints in an exemplary semiconductor manufacturing process. At a range of 0.025 μm to 0.300 μm of the cell height A, an excessive increase in the wafer area where the TAP unit is present is associated with a decrease in the remaining wafer area for the other functional units of the IC layout 100 if DX is below the range of 0.05 μm to 100 μm and/or if DY is below the range of 0.5 μm to 1000 μm. At a range of 0.025 μm to 0.300 μm of the cell height A, there is an increased risk of latch-up if DX exceeds a range of 0.05 μm to 100 μm and/or if DY exceeds a range of 0.5 μm to 1000 μm. The range of 0.1 μm to 5000 μm for the length L of the elongated TAP unit (e.g., 120 or 121) is derived from the respective range(s) for A, DX and/or DY based on the relationship (1) or (1').

Fig. 1B is a schematic enlarged view of a portion 140 of an IC layout 100 according to some embodiments to describe an example to determine the number of fin features in a TAP unit. Portion 140 includes well region 141, OD region 142, and a plurality of

gate regions

143, 144. Well region 141 extends in the X-direction and surrounds or encloses OD region 142 therein. OD region 142 includes one or more fin features (not shown) extending in the X-direction. OD region 142 has a length L in the X direction_ODAnd a height W in the Y direction. The gate regions 143,144 extend in the Y-direction across the OD region 142 and are arranged at a pitch CPP in the X-direction.

The number of fin features F in the OD region 142 is determined by the following relationship

F＝(L_OD/CPP)*W*Fn (5)

Where Fn is the number of fin features per unit height in the Y direction. In at least one embodiment, the CPP and W are the same for all TAP units.

In an example, portion 140 corresponds to a region containing a first TAP unit, such as first TAP unit 110 in fig. 1A. In particular, well region 141 corresponds to first well region 130, OD region 142 corresponds to first TAP unit 110, and L_ODCorrespond toAt lengths L', W of the first TAP unit 110 corresponds to the height of the first TAP unit 110 in the Y-direction, and F corresponds to F1 or F, which is the number of fin features in the first TAP unit 110_NTAP. Thus, the number of fin features in each first TAP unit may be determined from relationship (5).

In another example, portion 140 corresponds to a region containing a second TAP unit, such as second TAP unit 120 in fig. 1A. In particular, well region 141 corresponds to second well region 131, and OD region 142 corresponds to second TAP unit 120, L_ODCorresponds to the length L of the second TAP unit 120, W corresponds to the height of the second TAP unit 120 in the Y-direction, and F corresponds to F2 or F, which is the number of fin features in the second TAP unit 120_PTAP. Thus, the number of fin features in each second TAP unit may also be determined from relationship (5).

Fig. 1C is a schematic cross-sectional view of an IC device 150 according to some embodiments. The IC device 150 corresponds to a part of the IC arrangement diagram 100 indicated by an arrow Y → Y1 in fig. 1A. The cross-sectional view in fig. 1C is also combined with the schematic circuit diagram of the IC device 150.

IC device 150 includes a substrate 151 on which TAP units, well regions, active regions, gate regions, and fin features described with respect to fig. 1A and 1B are formed. For example, IC device 150 includes N-well 134, P-well 137, N-well 136, and P-well 139 on substrate 151. P-type

active regions

152 and 153, and NTAP cell 115 are formed in N-well 134. The gate regions 154 are formed over the P-type active regions 152,153 and define a PMOS with the P-type

active regions

152, 153. N-type active regions 155,156 are formed in P-well 137. The gate regions 157 are formed over the N-type active regions 155,156 and define, together with the N-type active regions 155,156, an NMOS. The PTAP cell 121 is formed in the P-well 139. The IC device 150 further includes a plurality of isolation regions 158 between adjacent P-wells and N-wells. The PMOS P-type active region 152 is coupled to a first power voltage, e.g., VDD. The N-type active region 156 of the NMOS is coupled to a second power supply voltage, e.g., VSS, which in at least one embodiment is ground. The substrate 151 is a P-type substrate.

The schematic circuit diagram of the IC device 150 in fig. 1C shows parasitic transistors Q1 and Q2. Parasitic transistor Q1 is a PNP transistor formed by P-type active region 152, N-well 134, and P-type substrate 151. Parasitic transistor Q2 is an NPN transistor formed through N-well 134, P-well 137, and N-type active region 156. In the absence of the NTAP cell 115 and/or PTAP cell 121, there is a problem with leakage current in one or more of the P-type substrate 151, P-well, and N-well of the IC device 150 being sufficient to turn on both parasitic transistors Q1 and Q2, and create a current path from VDD, through the turned-on parasitic transistors Q1 and Q2, to VSS. This current path between VDD and VSS is a latch-up condition that adversely affects the performance of the IC device 150.

The provision of NTAP cell 115 coupled to VDD and PTAP cell 121 coupled to VSS reduces the likelihood of latch-up conditions and improves LUP immunity of IC device 150. In the schematic circuit diagram of the IC device 150 in fig. 1A, the resistor R_NWRepresenting the TAP cell resistance between the NTAP cell represented by NTAP cell 115 and the substrate of parasitic transistor Q1, and resistor R_PsubRepresenting the TAP cell resistance between the PTAP cell represented by PTAP cell 121 and the substrate of parasitic transistor Q2. Resistor R_NWAnd R_PsubThe lower the resistance of (a), the lower the likelihood that the parasitic transistors Q1 and Q2, respectively, will turn on, the better the LUP immunity of the IC device 150. Resistor R_NWThe resistance of (a) depends on the configuration and/or arrangement of the NTAP cell. Resistor R_PsubDepending on the configuration and/or arrangement of the PTAP cell. For example, referring to fig. 1A, as the distance 2 DY between adjacent elongated

second TAP units

120, 121 increases, the resistor R_PsubThe resistance of (2) increases; however, as the length L or number of fin features of the elongated

second TAP unit

120, 121 increases, the resistor R_PsubThe resistance of (2) is reduced. By configuring and/or configuring NTAP units and/or PTAP units as described herein, it is possible to improve the LUP immunity of the IC device 150 in at least one embodiment.

As described herein, some other methods for TAP unit placement suffer from some potential problems. For example, in a first approach, the TAP unit is disposed in a half-cell height configuration across the boundary between the P-well and the N-well. This half-cell height configuration faces manufacturing difficulties, especially at CDs below 100 nm. In contrast, as described with respect to fig. 1A-1B, the TAP cells in some embodiments are completely enclosed within respective well regions, thus avoiding the manufacturing difficulties associated with half-cell height configurations. For another example, in the described first approach and in a second, different approach, there is a problem with mixed channel effects due to implant discontinuities between tightly configured NTAP cells and PTAP cells. Such problems of mixed channel effects are precluded by one or more embodiments described herein. In some embodiments, it is possible to achieve one or more effects, including but not limited to relaxing process constraints, improving latch-up immunity, reducing the area occupied or blocked by a TAP unit, and increasing the area in which standard cells other than TAP units may be disposed, particularly at advanced manufacturing process nodes. In some further embodiments, it is possible to improve latch immunity and/or reduce the area occupied or blocked by the TAP unit without process constraints at advanced manufacturing process nodes. In one example, the area occupied or blocked by a TAP unit is reduced in at least one embodiment to about 85% of that observed in other methods without sacrificing LUP immunity.

Fig. 2 is a schematic diagram of an IC layout 200 according to some embodiments. The IC layout 200 includes a plurality of portions 201, … 20n arranged at regular intervals in the X direction and the Y direction. The TAP units are similarly disposed in each of the portions 201, … 20 n. For example, in each of the portions 201, … 20n, the TAP units are disposed as described with respect to fig. 1A in at least one embodiment. Other arrangements of TAP units as described with respect to fig. 3A, 3B, and 4A are within the scope of the various embodiments. Thus, the TAP units are disposed on the IC layout 200 at regular intervals and in a repeating pattern to ensure a predetermined LUP immunity on the IC layout 200. In some embodiments, one or more advantages or effects described with respect to fig. 1A may be achieved in the IC layout 200.

Fig. 3A is a schematic diagram of an IC layout 300A according to some embodiments. In at least one embodiment, IC layout 300A corresponds to any of portions 201, … 20n in fig. 2. Similar to the IC layout 100, the IC layout 300A includes a plurality of first TAP units, representatively indicated at 310, and a plurality of

second TAP units

320, 321. The first TAP unit 310 corresponds to the

first TAP unit

110 and 117 of the IC arrangement 100, but is configured in more than two columns, e.g., in four columns 318,319,328, 329. The second TAP units 320,321 correspond to the

second TAP units

120, 121 and extend in the X direction across the four columns 318,319,328,329 of the first TAP unit 310. In some embodiments, the configurations, modifications, advantages or effects described with respect to fig. 1A may be achieved in the IC layout 300A.

Fig. 3B is a schematic diagram of an IC layout 300B according to some embodiments. In at least one embodiment, IC layout 300B corresponds to any of portions 201, … 20n in fig. 2. Similar to the IC layout diagram 300A, the IC layout diagram 300B includes a plurality of first TAP units 310 configured in four columns 318,319,328, 329. However, instead of each of the successive second TAP units 320,321 in the IC arrangement 300A, the IC arrangement 300B includes a series 330,331 of discrete second TAP units, representatively indicated at 332,333,334, 335. The second TAP units 332,333,334,335 are arranged in a row along the X direction at an interval d. The length L of each of the series 330,331, which determines the number of fin features in the series, is the total number of lengths m of each second TAP unit 332,333,334,335 in the series. In each of the series, e.g., series 331, a first end TAP unit 332 at a first end of series 331 overlaps in the Y-direction the first TAP unit in one of the columns, e.g., column 318. A second end TAP unit 335 at a second end of the series 331 overlaps the first TAP unit in another column 329 in the Y-direction. Series 331 further includes at least one intermediate TAP unit 334 between the first and second ends of series 331 and does not overlap first TAP units among the first TAP units in columns 318,319,328, 329. In some embodiments, the configurations, modifications, advantages or effects described with respect to fig. 1A may be achieved in the IC layout 300B.

Fig. 4A is a schematic diagram of an IC layout 400 according to some embodiments. The IC arrangement 400 in fig. 4A is similar to the IC arrangement 100 in fig. 1A, except that the P-type regions, wells, or TAP units in the IC arrangement 400 correspond to the N-type regions, wells, or TAP units in the IC arrangement 100, and vice versa. Elements in fig. 4A are indicated by the same reference numerals as the corresponding elements in fig. 1A, but with a single prime added to fig. 4A. For example, the well region 130' in fig. 4A corresponds to the well region 130 in fig. 1A. In at least one embodiment, the IC device corresponding to IC layout 400 is formed on an N-type substrate, as described with respect to fig. 4B.

Fig. 4B is a schematic cross-sectional view of an IC device 150' according to some embodiments. IC device 150 ' corresponds to a portion of IC layout 400 indicated by arrow Y ' Y1 ' in fig. 4A. The cross-sectional view in fig. 4B is also combined with the schematic circuit diagram of the IC device 150'. The IC device 150 'in fig. 4B is similar to the IC device 150 in fig. 1C, except that the P-type substrate, region, well, TAP unit in the IC device 150' corresponds to the N-type substrate, region, well, TAP unit in the IC device 150, and vice versa. Elements in fig. 4B are indicated by the same reference numerals as the corresponding elements in fig. 1C, but with a single prime added to fig. 4B. For example, the substrate 151' in fig. 4B corresponds to the substrate 151 in fig. 1C. In addition, NMOS, PMOS, Q1 '(NPN), Q2' (PNP), R in FIG. 4B_PWAnd R_NsubCorresponding to PMOS, NMOS, Q1(PNP), Q2(NPN), R in FIG. 1C, respectively_NWAnd R_Psub。

In some embodiments, the configurations, operations, modifications, advantages or effects described with respect to the IC arrangement 100 in fig. 1A and/or the IC device 150 in fig. 1C may be achieved in the IC arrangement 400 in fig. 4A and/or the IC device 150' in fig. 4B. Some embodiments include an IC layout similar to

IC layout

300A or 300B, but with similar changes from P-type substrates, wells, regions, or TAP units to N-type substrates, wells, regions, or TAP units, respectively, and vice versa.

Fig. 5 is a flow diagram of a method 500 for TAP unit placement in an IC layout, according to some embodiments. In at least one embodiment, method 500 is performed, in whole or in part, by a processor as described herein to generate an IC layout corresponding to at least one of

IC layouts

100, 200, 300A,300B, and 400.

At operation 505, a plurality of first TAP units are disposed in an IC layout such that the first TAP units are configured in two adjacent columns. For example, as described with respect to fig. 1A, the plurality of first TAP units 110-. Two adjacent columns 118,119 are adjacent to each other in a first direction, e.g. the X-direction, and extend in a second direction, e.g. the Y-direction, transverse to the first direction. The first TAP unit 110-117 has a first semiconductor type, e.g., N-type as in fig. 1A, or P-type as in fig. 4A.

At operation 515, two second TAP units of a second semiconductor type different from the first semiconductor type are disposed in the IC layout. Each of the two second TAP units extends continuously between two adjacent columns of the first TAP units over a second length greater than the first length of each of the first TAP units. For example, as described with respect to fig. 1A, two

second TAP units

120, 121 are disposed in the IC layout 100. Each of the two

second TAP units

120, 121 extends continuously between two adjacent columns 118,119 of the first TAP unit 110-. Two adjacent columns 118,119 of

first TAP units

110 and 117 are located between two

second TAP units

120, 121 in the Y-direction. The

second TAP units

120, 121 are of a second semiconductor type, e.g., P-type as in fig. 1A, or N-type as in fig. 4A.

In at least one embodiment,

operations

505 and 515 occur in parallel, for example, at one place, and route the operations of an IC manufacturing flow. In one or more embodiments, the first TAP unit and/or the second TAP unit are standard units stored in and read from one or more unit libraries. In some embodiments,

operations

505 and 515 are performed to dispose TAP units on an IC layout at regular intervals and in a repeating pattern, as described with respect to fig. 2.

The described method includes exemplary operations, but these exemplary operations do not necessarily need to be performed in the order shown. Operations may be added, substituted, changed in order, and/or eliminated as appropriate according to the spirit and scope of embodiments of the present disclosure. Embodiments that combine different features and/or different embodiments are within the scope of the present disclosure and will be apparent to one of ordinary skill in the art upon review of one embodiment of the present disclosure.

Fig. 6 is a perspective view of an exemplary circuit element 600 having fin features according to some embodiments. In the exemplary configuration in fig. 6, circuit element 600 is a fin-field-effect transistor (FINFET). The FINFET 600 includes a substrate 602, at least one fin feature (or fin) 604 extending from the substrate 602 in the Z-direction, a gate dielectric 606 along a surface of the fin 604, and a gate electrode 608 over the gate dielectric 606. Source and

drain regions

610 and 612 are disposed over the substrate 602 on opposite sides of the fin 604. The fin 604, source region 610, and drain region 612 are active regions (or OD regions) that correspond in one or more embodiments to any of the active regions described with respect to fig. 1A-4B. In at least one embodiment, gate electrode 608 corresponds to any of the gate regions described with respect to fig. 1A-4B. The described configuration of fin features in the active region is an example. Other configurations are within the scope of various embodiments.

In some embodiments, some or all of the methods discussed above are performed by an IC layout generation system. In some embodiments, the IC layout generation system may be used as part of a design factory for an IC manufacturing system as discussed below.

Fig. 7 is a block diagram of an EDA system 700 according to some embodiments.

In some embodiments, EDA system 700 includes an Automated Placement and Routing (APR) system. According to one or more embodiments, the methods described herein of designing a layout and representing a wire routing configuration are performable, for example, using an EDA system 700 according to some embodiments.

In some embodiments, the EDA system 700 is a general purpose computing device that includes a hardware processor 702 and a non-transitory computer readable storage medium 704. Among other things, the storage medium 704 is encoded with computer program code 706, i.e., stores computer program code 706, i.e., a set of executable instructions. Execution of the instructions 706 by the hardware processor 702 represents (at least in part) an EDA tool that implements some or all of, for example, the methods described herein in accordance with one or more embodiments (hereinafter, the processes and/or methods described).

The processor 702 is electrically coupled to the computer-readable storage medium 704 by a bus 708. The processor 702 is also electrically coupled to an I/O interface 710 via bus 708. A network interface 712 also electrically couples the processor 702 via the bus 708. The network interface 712 connects to a network 714, so that the processor 702 and the computer-readable storage medium 704 can connect to external elements through the network 714. The processor 702 is configured to execute computer program code 706 encoded in a computer readable storage medium 704 to cause the EDA system 700 to perform a portion or all of the processes and/or methods. In one or more embodiments, the processor 702 is a Central Processing Unit (CPU), a multiprocessor, a distributed processing system, an Application Specific Integrated Circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). The computer-readable storage medium 704 includes, for example, a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 704 may include a compact disk-read-only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a Digital Video Disk (DVD).

In one or more embodiments, the storage medium 704 stores computer program code 706 for causing the EDA system 700 (where such execution represents, at least in part, an EDA tool) to perform a portion or all of the processes and/or methods. In one or more embodiments, the storage medium 704 also stores information that facilitates performing a portion or all of the processes and/or methods. In one or more embodiments, the storage medium 704 stores a library 707 of standard cells including HPC cells as disclosed herein.

The EDA system 700 includes an I/O interface 710. The I/O interface 710 is coupled to external circuitry. In one or more embodiments, I/O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for communicating information and commands to processor 702.

EDA system 700 also includes a network interface 712 coupled to processor 702. Network interface 712 allows EDA system 700 to communicate with a network 714 to which one or more other computer systems are connected. Network interface 712 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and/or methods are performed in two or more EDA systems 700.

The EDA system 700 is configured to receive information via the I/O interface 710. Information received via I/O interface 710 may include one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor 702. Information is communicated to the processor 702 via the bus 708. The EDA system 700 is configured to receive information related to a UI through the I/O interface 710. Information is stored on the computer-readable medium 704 as a User Interface (UI) 742.

In some embodiments, some or all of the processes and/or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, some or all of the processes and/or methods are implemented as software applications that are part of additional software applications. In some embodiments, some or all of the processes and/or methods are performed as a plug-in to a software application. In some embodiments, at least one of the processes and/or methods is performedImplemented as a software application that is part of the EDA tool. In some embodiments, some or all of the processes and/or methods are implemented as software applications used by the EDA system 700. In some embodiments, a layout comprising standard cells is made using a standard cell such as that available from CADENCE DESIGN SYSTEMS, Inc

Or another suitable arrangement.

In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/removable and/or internal/built-in memory or memory units, for example, one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM, a RAM, a memory card, and the like.

Fig. 8 is a block diagram of an Integrated Circuit (IC) manufacturing system 800 and an IC manufacturing flow associated with the IC manufacturing system, in accordance with some embodiments. In some embodiments, based on the layout, at least one of (a) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using the fabrication system 800.

In fig. 8, IC manufacturing system 800 includes entities such as design factory 820, mask factory 830, and IC manufacturer/manufacturer ("fabricator") 850 that interact with each other in the design, development, and manufacturing cycle and/or service associated with fabricating IC device 860. The entities in system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design factory 820, mask factory 830, and IC fabrication 850 are owned by a single larger company. In some embodiments, two or more of the design factory 820, the mask factory 830, and the IC manufacturing 850 coexist in a common facility and use common resources.

Design factory (or design team) 820 generates IC design layout 822. IC design layout 822 includes various geometric patterns designed for IC device 860. The geometric pattern corresponds to the pattern of the metal, oxide, or semiconductor layers that make up the various components of the IC device 860 to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout 822 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal wires or vias interconnecting intervening layers, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design factory 820 performs the appropriate design procedures to form an IC design layout 822. The design procedure includes one or more of a logic design, a physical design or placement, and routing. The IC design layout 822 is presented in one or more data files with information of the geometric pattern. For example, the IC design layout 822 is expressed in a GDSII file format or a DFII file format.

The mask factory 830 includes data preparation 832 and mask manufacturing 844. Mask factory 830 uses IC design layout 822 to fabricate one or more masks 845 for various layers that will be used in fabricating IC device 860 according to IC design layout 822. The mask factory 830 performs mask data preparation 832 in which the IC design layout 822 is converted into a representative data file ("RDF"). The mask data preparation 832 provides the RDF to the mask manufacture 844. Mask manufacture 844 includes mask writers. The mask writer converts the RDF into an image on a substrate such as mask (reticle) 845 or semiconductor wafer 853. The design layout 822 is manipulated by the mask data preparation 832 to conform to the characteristics of the mask writer and/or the requirements of the IC fabrication 850. In FIG. 8, mask data preparation 832 and mask manufacturing 844 are illustrated as separate elements. In some embodiments, the mask data preparation 832 and the mask manufacturing 844 may be collectively referred to as mask data preparation.

In some embodiments, mask data preparation 832 includes Optical Proximity Correction (OPC) that uses lithography enhancement techniques to compensate for image errors such as those that may result from diffraction, interference, other process effects, and the like. The OPC adjusts the IC design layout 822. In some embodiments, mask data preparation 832 includes further Resolution Enhancement Techniques (RET), such as off-axis illumination, secondary resolution assist features, phase shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, Inverse Lithography (ILT) techniques are also used, which treat OPC as an inverse imaging problem.

In some embodiments, mask data preparation 832 includes a Mask Rule Checker (MRC) that checks IC design layout 822 that has undergone processing in OPC with a set of mask creation rules that contain certain geometric and/or connectivity constraints to ensure adequate margins to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout 822 to compensate for limitations during mask manufacturing 844, which may cancel portions of the modifications performed by the OPC in order to satisfy mask creation rules.

In some embodiments, mask data preparation 832 includes Lithography Process Checking (LPC) that verifies processing to simulate the fabrication of IC devices 860 to be performed by IC fabricator 850. The LPC simulates this process based on IC design layout 822 to create a device that simulates fabrication, such as IC device 860. The processing parameters in the LPC simulation may include parameters associated with various processes of an IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and/or other aspects of the manufacturing process. The LPC considers various factors such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like or combinations thereof. In some embodiments, after the simulated fabricated devices have been created by LPC, if the simulated devices are not close enough in shape to satisfy design rules, OPC and/or MRC are repeated to further refine the IC design layout 822.

It should be understood that the above description of mask data preparation 832 has been simplified for purposes of clarity. In some embodiments, data preparation 832 includes additional features such as Logic Operations (LOPs) to modify IC design layout 822 according to manufacturing rules. Additionally, the processes applied to the IC design layout 822 during data preparation 832 may be performed in a variety of different orders.

After mask data preparation 832 and during mask manufacture 844, a mask 845 or a set of masks 845 are manufactured based on the modified IC design layout 822. In some embodiments, the mask fabrication 844 includes performing one or more lithography exposures based on the IC design layout 822. In some embodiments, an electron beam (e-beam) or electron beam mechanisms are used to form a pattern on a mask (reticle) 845 based on the modified IC design layout 822. The mask 845 may be formed by various techniques. In some embodiments, the mask 845 is formed using a binary technique. In some embodiments, the masking pattern includes opaque and transparent regions. A radiation beam, such as an Ultraviolet (UV) beam, used to expose a layer of image sensitive material (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of mask 845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in an opaque region of the binary mask. In another example, mask 845 is formed using a phase-shifting technique. In a Phase Shift Mask (PSM) version of mask 845, various features in the pattern formed on the phase shift mask are used to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask may be a mute PSM or an alternating PSM. The mask(s) resulting from the mask fabrication 844 are used in various processes. For example, the mask(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 853, in etching processes to form various etched regions in semiconductor wafer 853, and/or in other suitable processes.

IC fabrication 850 includes wafer fabrication 852. IC manufacturing 850 is an IC manufacturing business that includes one or more manufacturing facilities for the manufacture of various IC products. In some embodiments, IC fabrication 850 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple IC products, while a second manufacturing facility may provide back-end-of-line (BEOL) manufacturing for interconnection and packaging of the IC products, and a third manufacturing facility may provide other services for foundry business.

IC fabrication 850 uses mask(s) 845 fabricated by mask factory 830 to fabricate IC device 860. Thus, IC fabrication 850 uses IC design layout 822, at least indirectly, to fabricate IC device 860. In some embodiments, semiconductor wafer 853 is fabricated by IC fabrication 850 using mask(s) 845 to form IC device 860. In some embodiments, IC fabrication includes performing one or more lithography exposures based at least indirectly on the IC design layout 822. Semiconductor wafer 853 comprises a silicon substrate or other suitable substrate having a material layer formed thereon. The semiconductor wafer 853 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent fabrication steps).

Details regarding Integrated Circuit (IC) manufacturing systems (e.g., system 800 of fig. 8) and IC manufacturing flows associated with the manufacturing systems are found, for example, in U.S. patent No. 9,256,709 issued on day 9/2/2016, U.S. pre-granted publication No. 20150278429 issued on day 1/10/2015, U.S. pre-granted publication No. 20140040838 issued on day 6/2/2014, and U.S. patent No. 7,260,442 issued on day 21/8/2007, each of which is hereby incorporated by reference in its entirety.

In some embodiments, an Integrated Circuit (IC) device includes a plurality of first tap cells of a first semiconductor type, and a plurality of second tap cells of a second semiconductor type different from the first semiconductor type. The plurality of first tap units are arranged in at least two columns, the at least two columns being adjacent to each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first tap units has a first length in a first direction. The plurality of second tap units comprises at least one second tap unit extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first tap units in the first direction.

In some embodiments, the integrated circuit device further comprises a substrate. The first well tap unit and the second well tap unit are disposed on the substrate. Wherein the substrate is of the second semiconductor type.

In some embodiments, wherein the second well tap unit further includes at least another second well tap unit extending in the first direction between the at least two columns over a second length greater than the first length of each of the first well tap units in the first direction, and the first well tap unit is arranged between the at least one second well tap unit and the at least another second well tap unit in the second direction.

In some embodiments, the integrated circuit device further includes a plurality of first well regions of the first semiconductor type, each of the first well tap cells being in a corresponding one of the first well regions. The IC device further includes a plurality of second well regions of the second semiconductor type, each of the second well tap units being in a corresponding one of the second well regions, the first well regions and the second well regions extending in the first direction and being alternately arranged in the second direction; and a plurality of fin features extending in a first direction. Wherein F2/F1 ≧ (DY/DX) × (L/A). F1 is a number of fin features in each of the first well tap cells. F2 is a number of fin features in each of the at least one second well tap cell and the at least another second well tap cell. DX is half of a first distance in the first direction between facing sides of the at least two columns. DY is half of a second distance in the second direction between facing sides of the at least one second well tap cell and the at least another second well tap cell. L is a second length of the at least one second well tap cell or the at least another second well tap cell in the first direction. A is a cell height in the second direction and is a sum of a height of a first well region in the first well region and a height of an adjacent second well region in the second well region.

In some embodiments, the IC device satisfies at least one of: DY is from 0.5 μm to 1000 μm, DX is from 0.05 μm to 100 μm, L is from 0.1 μm to 5000 μm or A is from 0.025 μm to 0.300. mu.m.

In some embodiments, the IC device further comprises a plurality of gate regions, the gate regions extending in the second direction. Wherein each of F1 and F2 is defined by the formula (L)_OD/CPP)*W*Fn。L_ODIs a first length corresponding to the first well tap cell or a second length of at least one second well tap cell or at least another second well tap cell. CPP is a pitch between adjacent gate regions in the first direction. W is a height of the corresponding first well tap unit, the at least one second well tap unit, or the at least another second well tap unit in the second direction. Fn is a number of fin features per unit height in the second direction.

In some embodiments, the IC device further includes a plurality of first well regions of the first semiconductor type, each of the first well tap cells being in a corresponding one of the first well regions. Also included are a plurality of second well regions of the second semiconductor type, each of the second well tap cells being in a corresponding one of the second well regions; and the first well region, the second well region, the first well tap unit and the second well tap unit are arranged on the substrate. Wherein the first semiconductor type is N-type, the second semiconductor type is P-type, and the substrate is a P-type substrate, or the first semiconductor type is P-type, the second semiconductor type is N-type, and the substrate is an N-type substrate.

In some embodiments, wherein the at least one second well tap cell overlaps the at least one first well tap cell in at least one of the at least two columns in the second direction.

In some embodiments, wherein the at least one second well tap cell overlaps all of the first well tap cells in all of the at least two columns in the second direction.

In some embodiments, the at least one second well tap cell comprises a single second well tap cell extending continuously in the first direction between the first and second ends thereof. The first end of the single second well tap cell overlaps the first well tap cell in one of the at least two columns in the second direction, and the second end of the single second well tap cell overlaps the first well tap cell in another of the at least two columns in the second direction.

In some embodiments, the at least one second well tap cell comprises a second series of well tap cells arranged along the first direction. The second series of well tap units includes a first end well tap unit overlapping the first well tap unit in one of the at least two columns at a first end of the series of second well tap units and in the second direction, a second end well tap unit overlapping the first well tap unit in the other of the at least two columns at a second end of the series of second well tap units and in the second direction, and an intermediate well tap unit between the first end and the second end of the series of second well tap units and not overlapping the first well tap unit among the first well tap units in the at least two columns.

In some embodiments, wherein the at least two columns include more than two columns, and the first well tap cells in the more than two columns overlap the at least one second well tap cell in the second direction.

In some embodiments, a method comprises: a plurality of first well tap cells of a first semiconductor type are disposed in two adjacent columns in an Integrated Circuit (IC) layout. The method further comprises: in the IC layout, two second well tap units of a second semiconductor type different from the first semiconductor type are disposed. Two adjacent columns are adjacent to each other in the first direction, extend in a second direction transverse to the first direction, and are located between two second well tap units in the second direction. Each of the plurality of first well tap cells has a first length in a first direction. Each of the two second well tap units extends continuously in the first direction between two adjacent columns over a second length greater than the first length of each of the plurality of first well tap units in the first direction. At least one of the disposing of the plurality of first well tap units or the disposing of the two second well tap units is performed by a processor.

In some embodiments, no other well tap cell of the second semiconductor type is disposed between two second well tap cells in the IC layout.

In some embodiments, each of the two second well tap cells has a first end overlapping the first well tap cell in one of the two adjacent columns in the second direction, and a second end overlapping the first well tap cell in the other of the at least two columns in the second direction.

In some embodiments, the IC layout includes a plurality of first well regions of a first semiconductor type and a plurality of second well regions of a second semiconductor type, the first well regions and the second well regions extending in a first direction and being alternately arranged in a second direction. In disposing the first well tap units, each of the first well tap units is disposed in a corresponding one of the first well regions. In disposing the second well tap units, each of the two second well tap units is disposed in a corresponding one of the second well regions.

In some embodiments, wherein the IC layout further comprises a plurality of fin features, the fin features extending in a first direction, and F2/F1 ≧ (DY/DX) × (L/A). Where F1 is a number of fin features in each of the first well tap cells and F2 is a number of fin features in each of the two second well tap cells. DX is half of a first distance in the first direction between facing sides of two adjacent columns. DY is half of a second distance in the second direction between facing sides of the two second well tap cells. L is a second length of each of the two second well tap units in the first direction. A is a cell height in the second direction and is a sum of a height of a first well region in the first well region and a height of an adjacent second well region in the second well region.

In some embodiments, the disposing of the first well tap unit and the disposing of the two second well tap units are performed at regular intervals in the first direction and the second direction on a region of the IC layout.

In some embodiments, a system includes a processor to perform well tap cell placement in an Integrated Circuit (IC) layout by placing a plurality of first well tap cells of a first semiconductor type in rows and columns, and a plurality of second well tap cells of a second semiconductor type different from the first semiconductor type. The rows extend in a first direction and the columns extend in a second direction transverse to the first direction. Each of the plurality of second well tap units is elongated in the first direction and overlaps a plurality of first well tap units among the plurality of first well tap units in the second direction.

In some embodiments, wherein the processor is to perform disposing the second well tap units such that, among the second well tap units, each pair of second well tap units adjacent to each other in the second direction sandwich therebetween the plurality of rows and columns of the first well tap units.

The foregoing summary, as well as the following detailed description of the embodiments, is provided to enable those skilled in the art to better understand the aspects of an embodiment of the present disclosure. Those skilled in the art should appreciate that they may readily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of an embodiment of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, characterized in that, comprising:

a plurality of first well tap cells of a first semiconductor type; and

a plurality of second well tap cells of a second semiconductor type different from the first semiconductor type,

wherein the plurality of first well tap cells are arranged in at least two rows adjacent to each other in a first direction and extending in a second direction transverse to the first direction,

each of the plurality of first well tap cells has a first length in the first direction, and

The plurality of second well tap cells includes at least one second well tap cell that is greater than each of the plurality of first well tap cells in the first direction. A second length of the first length, between the at least two columns, extends in the first direction.