[go: up one dir, main page]

CN113314480A - Panel-level fan-out type packaging structure and method for silicon-based GaN HEMT device - Google Patents

Panel-level fan-out type packaging structure and method for silicon-based GaN HEMT device Download PDF

Info

Publication number
CN113314480A
CN113314480A CN202110726218.5A CN202110726218A CN113314480A CN 113314480 A CN113314480 A CN 113314480A CN 202110726218 A CN202110726218 A CN 202110726218A CN 113314480 A CN113314480 A CN 113314480A
Authority
CN
China
Prior art keywords
silicon
chip
gan hemt
based gan
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110726218.5A
Other languages
Chinese (zh)
Inventor
刘家才
霍炎
谢雷
罗鹏
熊元庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Nitrosil Technology Co ltd
SIPLP Microelectronics Chongqing Ltd
Original Assignee
Chengdu Nitrosil Technology Co ltd
SIPLP Microelectronics Chongqing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Nitrosil Technology Co ltd, SIPLP Microelectronics Chongqing Ltd filed Critical Chengdu Nitrosil Technology Co ltd
Priority to CN202110726218.5A priority Critical patent/CN113314480A/en
Publication of CN113314480A publication Critical patent/CN113314480A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明提供一种硅基氮化镓(GaN)HEMT器件面板级扇出型封装结构及封装方法，包括硅基GaN HEMT芯片，芯片的四周和正面被第一塑封料包裹，底部金属层为第一散热通道，硅基GaN HEMT芯片正面输入输出口上方的铜线路为第二散热通道。本发明用铜线路将芯片的输入输出口引出，与传统焊线封装工艺中用金线或铜线引出输入输出口相比，大大减小了封装带来的寄生电阻和电感，使得产品应用频率的上限进一步提升。芯片背面与金属散热片直接相连，提供除芯片底部以外的另外一个散热通道，大大降低了封装热阻，解决了硅基GaNHEMT器件正面散热困难的问题。

Figure 202110726218

The invention provides a panel-level fan-out packaging structure and packaging method of a silicon-based gallium nitride (GaN) HEMT device, including a silicon-based GaN HEMT chip, the periphery and front of the chip are wrapped by a first plastic sealing compound, and the bottom metal layer is the first plastic sealing compound. A heat dissipation channel, the copper circuit above the input and output ports on the front of the silicon-based GaN HEMT chip is the second heat dissipation channel. The invention uses copper lines to lead out the input and output ports of the chip. Compared with the traditional bonding wire packaging process using gold wires or copper wires to lead out the input and output ports, the parasitic resistance and inductance brought by the packaging are greatly reduced, and the frequency of product application is greatly reduced. The upper limit is further increased. The back of the chip is directly connected to the metal heat sink, providing another heat dissipation channel other than the bottom of the chip, which greatly reduces the thermal resistance of the package and solves the problem of difficult heat dissipation on the front of the silicon-based GaN HEMT device.

Figure 202110726218

Description

Panel-level fan-out type packaging structure and method for silicon-based GaN HEMT device
Technical Field
The invention relates to the technical field of wafer-level packaging, in particular to a panel-level fan-out type packaging structure and a packaging method of a silicon-based GaN HEMT device.
Background
The electronic product can convert electric energy into heat energy when working due to the internal resistance of the electronic product, so that the temperature of the whole machine is increased, and when the heat generation speed is equal to the dissipation speed, the heat balance state is achieved, and the temperature is stabilized at a determined value. The resistance is generally in positive correlation with the temperature, the internal resistance of the device is increased along with the increase of the temperature, so that the consumed electric energy is also increased, the efficiency of the whole machine is reduced, and the energy is wasted. For this reason, it is expected that the lower the temperature at which the device operates stably, the better, and the higher the dissipation rate of heating becomes.
In power supply products, for example charger, adapter, fill electric pile, data center power etc. inside switching device is the main source of thermogenesis, so solve the heat dissipation that switching device is favorable to improving power supply product's efficiency. The traditional switch device mainly uses a silicon (Si) -based MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and the Si-based MOSFET cannot meet the application of high frequency and high power due to the limitation of materials and structures. The third generation semiconductor material device GaN High Electron Mobility Transistor (GaN HEMT) has the characteristics of High breakdown field strength, High Electron Mobility, High junction temperature and the like, and is an ideal device for replacing a Si MOSFET.
The difference between the thermal conductivity of the GaN material and the thermal conductivity of Si is not large, and the packaging thermal resistance is required to be small enough for exerting the excellent performance of the GaN HEMT.
When the MOSFET is in operation, when the Gate (Gate) voltage is greater than the threshold voltage Vth, carriers flow from the Source (Source) to the Drain (Drain) through the Gate to form a path, and the on and off of the device are controlled by controlling the Gate voltage, and meanwhile, the switching loss and the conduction loss are accompanied in a channel. The Source and Drain of the GaN HEMT device are both on the surface of the device, heat is mainly concentrated on the surface of the device, the Source and Drain of the traditional Si MOSFET are respectively located on the surface and the bottom of the device and belong to a vertical structure, and heat generated during working penetrates through the whole device. This results in GaN HEMTs with package heat treatment requirements that are different from those of conventional Si devices.
The traditional packaging of the Si-based power device adopts a Wire Bonding process, the chip mainly depends on a Frame (Lead Frame) at the bottom of the chip for heat dissipation when working, the heat dissipation mode is single, and the slender Wire brings larger parasitic inductance, so that the high-frequency application of the product is limited.
Wafer Level Packaging (WLP) was introduced in about 2000. Until now, most packaging processes have been mechanical processes such as grinding, sawing, wire bonding, and the like.
Fanout technology can be divided into three main types: chip-first/face-down, chip-first/face-up, and chip-last. These basic structures have expanded to include many variations, with variations appearing, it is increasingly difficult for end users to understand the differences between them, as well as their respective advantages and disadvantages. Each supplier of the fan-out has its own set of architecture, with different material combinations and process flows, and terminology to distinguish itself. This makes it a significant challenge for the end user to not only select the packaging architecture, but also to be able to provide a second source for any defined architecture. This may negatively impact the high volume implementation.
There are several challenges in the near future for Wafer level packaging technologies such as Wafer level CSP. With the development of silicon technology nodes, reliability and Chip Package Interaction (CPI) face greater challenges as the WLCSP size increases. This is not only the reliability performance, but also an adverse effect that may occur in subsequent processes after fabrication of the WLCSP. This includes transportation and handling, and final assembly onto a circuit board. There is increasing interest in adding five-sided or six-sided protection in the form of mold type compounds around WLCSP to provide additional protection for the post-fabrication process. At present, 5 surfaces of a Wafer of Wafer level CSP are exposed in the air, and the Wafer cannot meet high-voltage and complex application environments in various aspects of structural strength, safety specification, reliability and the like of products.
Disclosure of Invention
The invention aims to provide a panel-level fan-out packaging structure of a silicon-based GaNHEMT device, which is designed by utilizing a plate electrode fan-out packaging technology and combining a wide bandgap semiconductor device and has the advantages of high heat dissipation capacity, high reliability and low parasitic inductance.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a panel-level fan-out type packaging structure of a silicon-based GaN HEMT device comprises a silicon-based GaN HEMT chip 1, wherein the periphery and the front of the silicon-based GaN HEMT chip are wrapped by a first plastic packaging material 41, the front of the silicon-based GaN HEMT chip is the upper surface of a GaN device layer 12 on a silicon substrate 11, the bottom of the silicon substrate 11 is the back of the chip, the bottom of the silicon-based GaN HEMT chip is directly connected with a bottom metal layer 7, the upper surface of the silicon-based GaN HEMT chip 1 is an insulating layer 6, an input and output port 5 is arranged on the insulating layer 6 through punching, the upper surface of the insulating layer 6 is a copper circuit 3, pins are arranged above the copper circuit 3, the copper circuit 3 leads out the input and output ports of the chip, and adjacent copper circuits 3 are isolated through a second plastic packaging material 42; the bottom metal layer 7 below the silicon-based GaN HEMT chip 1 is a first heat dissipation channel, and the copper circuit 3 above the input/output port 5 on the front surface of the silicon-based GaN HEMT chip 1 is a second heat dissipation channel.
As a preferred mode, the silicon-based gan hemt device panel-level fan-out package structure is obtained by the following packaging method:
(1) the insulating layer 6 is adhered to the surface of the GaN wafer 8; (ii) a
(2) Exposing the input/output port 5 by laser drilling on the insulating layer 6;
(3) cutting the GaN wafer 8 into single silicon-based GaN HEMT chips 1 and then inversely installing the single silicon-based GaN HEMT chips on a carrier plate;
(4) the periphery of the silicon-based GaN HEMT chip 1 and the back surface of the chip are plastically packaged by a first plastic package material 41,
(5) grinding and thinning the first plastic packaging material 41 on the back surface of the chip until the Si substrate 11 on the back surface is exposed, and stripping;
(6) a copper circuit 3 is wired on the front surface of a silicon-based GaN HEMT chip 1 by an exposure and development method, an input/output port 5 of the GaN chip is led out to the surface of a product by electroplating, and a pin 2 is formed;
(7) forming a bottom metal layer 7 on the back of the silicon-based GaN HEMT chip in an electroplating and sputtering mode, and enhancing heat dissipation through the bottom metal layer 7;
(8) and the front surface of the silicon-based GaN HEMT chip is plastically packaged by using a second plastic packaging material 42.
In order to achieve the above object, the present invention further provides a method for packaging a panel-level fan-out package structure of a silicon-based GaN HEMT device, comprising the following steps:
(1) the insulating layer 6 is adhered to the surface of the GaN wafer 8; (ii) a
(2) Exposing the input/output port 5 by laser drilling on the insulating layer 6;
(3) cutting the GaN wafer 8 into single silicon-based GaN HEMT chips 1 and then inversely installing the single silicon-based GaN HEMT chips on a carrier plate;
(4) the periphery of the silicon-based GaN HEMT chip 1 and the back surface of the chip are plastically packaged by a first plastic package material 41,
(5) grinding and thinning the first plastic packaging material 41 on the back surface of the chip until the Si substrate on the back surface is exposed, and stripping;
(6) a copper circuit 3 is wired on the front surface of the silicon-based GaN HEMT chip by an exposure and development method, an input/output port 5 of the GaN chip is led out to the surface of a product by electroplating, and a pin 2 is formed;
(7) a bottom metal layer 7 is formed on the back of the silicon-based GaN HEMT chip in an electroplating and sputtering mode, and heat dissipation is enhanced through the bottom metal layer 7.
(8) And the front surface of the silicon-based GaN HEMT chip is plastically packaged by using a second plastic packaging material 42.
The invention has the beneficial effects that:
compared with the traditional bonding wire packaging process in which a gold wire/copper wire is used for leading out the input/output port, the invention greatly reduces the parasitic resistance and inductance caused by packaging, and further improves the upper limit of the application frequency of the product.
The back of the chip is directly connected with the metal radiating fin, and another radiating channel is provided except the bottom of the chip, so that the packaging thermal resistance is greatly reduced, and the problem of difficult radiation of the front of the GaN HEMT is solved. Forming double heat dissipation channels.
Drawings
Fig. 1 is a schematic view of a panel-level fan-out package structure of a silicon-based GaN HEMT device according to an embodiment of the present invention;
fig. 2-8 are schematic diagrams illustrating steps of a packaging method according to an embodiment of the present invention.
The chip comprises a substrate 1, a substrate 11, a GaN device layer 12, pins 2, copper lines 3, a first plastic package material 41, a second plastic package material 42, an input/output port 5, an insulating layer 6, a bottom metal layer 7 and a GaN wafer 8.
Detailed Description
As shown in fig. 1, the embodiment provides a panel-level fan-out package structure of a silicon-based GaN HEMT device, including a silicon-based GaN HEMT chip 1, where the periphery and front of the silicon-based GaN HEMT chip 1 are wrapped by a first molding compound 41, the front of the silicon-based GaN HEMT chip 1 is the upper surface of a GaN device layer 12 on a silicon substrate 11, the bottom of the silicon substrate 11 is the back of the chip, the bottom of the silicon-based GaN HEMT chip is directly connected to a bottom metal layer 7, the upper surface of the silicon-based GaN HEMT chip 1 is an insulating layer 6, an input/output port 5 is formed in the insulating layer 6 by punching, the upper surface of the insulating layer 6 is a copper line 3, a pin 2 is arranged above the copper line 3, the copper line 3 leads out the input/output port of the chip, and adjacent copper lines 3 are isolated by a second molding compound 42; the bottom metal layer 7 below the silicon-based GaN HEMT chip 1 is a first heat dissipation channel, and the copper circuit 3 above the input/output port 5 on the front surface of the silicon-based GaN HEMT chip 1 is a second heat dissipation channel.
The embodiment also provides a packaging method of the panel-level fan-out packaging structure of the silicon-based GaN HEMT device, which comprises the following steps:
(1) as shown in fig. 2, the insulating layer 6 is adhered to the surface of the GaN wafer 8;
(2) as shown in fig. 3, the input/output port 5 is exposed by laser drilling the insulating layer 6;
(3) as shown in fig. 4, the GaN wafer 8 is cut into single silicon-based GaN HEMT chips 1 and then flip-chip mounted on a carrier board;
(4) as shown in fig. 5, the periphery of the silicon-based GaN HEMT chip 1 and the back surface of the chip are plastically packaged by a first plastic package material 41,
(5) as shown in fig. 6, the first molding compound 41 on the back surface of the thinned chip is ground until the Si substrate on the back surface is exposed, and the board is removed;
(6) as shown in fig. 7, a copper circuit 3 is wired on the front surface of the silicon-based GaN HEMT chip by an exposure and development method, an input/output port 5 of the GaN chip is led out to the surface of a product by electroplating, and a pin 2 is formed;
(7) as shown in fig. 8, a bottom metal layer 7 is formed on the back surface of the silicon-based GaN HEMT chip by means of electroplating and sputtering, and heat dissipation is enhanced by the bottom metal layer 7;
(8) and the front surface of the silicon-based GaN HEMT chip is plastically packaged by using a second plastic packaging material 42.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (3)

1. The utility model provides a silica-based GaN HEMT device panel level fan-out type packaging structure which characterized in that: the silicon-based GaN HEMT chip comprises a silicon-based GaN HEMT chip (1), wherein the periphery and the front of the silicon-based GaN HEMT chip (1) are wrapped by a first plastic packaging material (41), the front of the silicon-based GaN HEMT chip (1) is the upper surface of a GaN device layer (12) on a silicon substrate (11), the bottom of the silicon substrate (11) is the back of the chip, the bottom of the GaN HEMT chip (1) is directly connected with a bottom metal layer (7), the upper surface of the silicon-based GaN HEMT chip (1) is an insulating layer (6), an input and output port (5) is formed in the insulating layer (6) through punching, the upper surface of the insulating layer (6) is a copper line (3), a pin (2) is arranged above the copper line (3), the copper line (3) leads out the input and output port of the chip, and adjacent copper lines (3) are isolated through a second plastic packaging material (42); a bottom metal layer (7) below the silicon-based GaN HEMT chip (1) is a first heat dissipation channel, and a copper circuit (3) above an input/output port (5) on the front surface of the silicon-based GaN HEMT chip (1) is a second heat dissipation channel.
2. The panel-level fan-out package structure of the silicon-based GaN HEMT device according to claim 1, which is obtained by the following packaging method:
(1) the insulating layer (6) is adhered to the surface of the GaN wafer (8);
(2) exposing the input/output port (5) by laser drilling on the insulating layer (6);
(3) cutting the GaN wafer (8) into single silicon-based GaN HEMT chips (1) and then inversely installing the chips on a carrier plate;
(4) the periphery of the silicon-based GaN HEMT chip (1) and the back surface of the chip are plastically packaged by a first plastic packaging material (41),
(5) grinding and thinning the first plastic packaging material (41) on the back surface of the chip until the Si substrate (11) on the back surface is exposed, and stripping;
(6) a copper circuit (3) is wired on the front surface of the silicon-based GaN HEMT chip by an exposure and development method, an input/output port (5) of the GaN chip is led out to the surface of a product by electroplating, and a pin (2) is formed;
(7) forming a bottom metal layer (7) on the back of the silicon-based GaN HEMT chip in an electroplating and sputtering mode, and enhancing heat dissipation through the bottom metal layer (7);
(8) and the front surface of the silicon-based GaN HEMT chip is plastically packaged by a second plastic packaging material (42).
3. A packaging method of a panel-level fan-out type packaging structure of a silicon-based GaN HEMT device is characterized by comprising the following steps:
(1) the insulating layer (6) is adhered to the surface of the GaN wafer (8);
(2) exposing the input/output port (5) by laser drilling on the insulating layer (6);
(3) cutting the GaN wafer (8) into single silicon-based GaN HEMT chips (1) and then inversely installing the chips on a carrier plate;
(4) the periphery of the silicon-based GaN HEMT chip (1) and the back of the chip are plastically packaged by a first plastic packaging material (41);
(5) grinding and thinning the first plastic packaging material (41) on the back surface of the chip until the Si substrate (11) on the back surface is exposed, and stripping;
(6) a copper circuit (3) is wired on the front surface of a silicon-based GaN HEMT chip (1) by an exposure and development method, an input/output port (5) of the GaN chip is led out to the surface of a product by electroplating, and a pin (2) is formed;
(7) forming a bottom metal layer (7) on the back of the silicon-based GaN HEMT chip in an electroplating and sputtering mode, and enhancing heat dissipation through the bottom metal layer (7);
(8) and the front surface of the silicon-based GaN HEMT chip is plastically packaged by a second plastic packaging material (42).
CN202110726218.5A 2021-06-29 2021-06-29 Panel-level fan-out type packaging structure and method for silicon-based GaN HEMT device Pending CN113314480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110726218.5A CN113314480A (en) 2021-06-29 2021-06-29 Panel-level fan-out type packaging structure and method for silicon-based GaN HEMT device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110726218.5A CN113314480A (en) 2021-06-29 2021-06-29 Panel-level fan-out type packaging structure and method for silicon-based GaN HEMT device

Publications (1)

Publication Number Publication Date
CN113314480A true CN113314480A (en) 2021-08-27

Family

ID=77380829

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110726218.5A Pending CN113314480A (en) 2021-06-29 2021-06-29 Panel-level fan-out type packaging structure and method for silicon-based GaN HEMT device

Country Status (1)

Country Link
CN (1) CN113314480A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114334672A (en) * 2022-03-08 2022-04-12 上海泰矽微电子有限公司 Fan-out type packaging structure and packaging method
CN114361025A (en) * 2022-03-21 2022-04-15 宁波芯健半导体有限公司 GaN ultrathin chip fan-out type packaging structure and packaging method
CN114883279A (en) * 2022-07-12 2022-08-09 深圳市冠禹半导体有限公司 Gallium nitride device and packaging method thereof
WO2024087083A1 (en) * 2022-10-27 2024-05-02 Innoscience (Zhuhai) Technology Co., Ltd. Semiconductor packaged device and method for manufacturing the same

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103904044A (en) * 2014-04-02 2014-07-02 华进半导体封装先导技术研发中心有限公司 Fan-out wafer-level packaging structure and manufacturing technology
CN104517915A (en) * 2013-10-01 2015-04-15 英飞凌科技股份有限公司 Arrangement and method for manufacturing the same
US20150303128A1 (en) * 2014-04-16 2015-10-22 Infineon Technologies Ag Device Including Multiple Semiconductor Chips and Multiple Carriers
US20170025379A1 (en) * 2015-07-22 2017-01-26 Delta Electronics, Inc. Power module package
CN108091617A (en) * 2016-11-22 2018-05-29 台达电子工业股份有限公司 Semiconductor device and packaging structure comprising same
US20180350772A1 (en) * 2015-12-22 2018-12-06 Intel Corporation Microelectronic devices designed with efficient partitioning of high frequency communication devices integrated on a package fabric
US10424573B1 (en) * 2018-03-27 2019-09-24 Delta Electronics Int'l (Singapore) Pte Ltd Packaging process
CN110416091A (en) * 2019-07-31 2019-11-05 中国电子科技集团公司第五十八研究所 A kind of silicon substrate fan-out package method and structure
CN110581079A (en) * 2019-09-23 2019-12-17 合肥矽迈微电子科技有限公司 Fan-out type chip packaging method and fan-out type chip packaging body
US20200144249A1 (en) * 2018-11-01 2020-05-07 Fujitsu Limited Semiconductor device and amplifier
US20200161258A1 (en) * 2018-11-19 2020-05-21 Fujitsu Limited Amplifier and amplification apparatus
CN112038305A (en) * 2020-10-12 2020-12-04 长电集成电路(绍兴)有限公司 Multi-chip ultrathin fan-out packaging structure and packaging method thereof
US20210043586A1 (en) * 2019-08-08 2021-02-11 Fujitsu Limited Semiconductor device and electronic device
CN214848592U (en) * 2021-06-29 2021-11-23 成都氮矽科技有限公司 Panel-level fan-out type packaging structure of silicon-based GaN HEMT device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104517915A (en) * 2013-10-01 2015-04-15 英飞凌科技股份有限公司 Arrangement and method for manufacturing the same
CN103904044A (en) * 2014-04-02 2014-07-02 华进半导体封装先导技术研发中心有限公司 Fan-out wafer-level packaging structure and manufacturing technology
US20150303128A1 (en) * 2014-04-16 2015-10-22 Infineon Technologies Ag Device Including Multiple Semiconductor Chips and Multiple Carriers
US20170025379A1 (en) * 2015-07-22 2017-01-26 Delta Electronics, Inc. Power module package
CN106373952A (en) * 2015-07-22 2017-02-01 台达电子工业股份有限公司 Power Module Package Structure
US20180350772A1 (en) * 2015-12-22 2018-12-06 Intel Corporation Microelectronic devices designed with efficient partitioning of high frequency communication devices integrated on a package fabric
CN108091617A (en) * 2016-11-22 2018-05-29 台达电子工业股份有限公司 Semiconductor device and packaging structure comprising same
US10424573B1 (en) * 2018-03-27 2019-09-24 Delta Electronics Int'l (Singapore) Pte Ltd Packaging process
US20200144249A1 (en) * 2018-11-01 2020-05-07 Fujitsu Limited Semiconductor device and amplifier
US20200161258A1 (en) * 2018-11-19 2020-05-21 Fujitsu Limited Amplifier and amplification apparatus
CN110416091A (en) * 2019-07-31 2019-11-05 中国电子科技集团公司第五十八研究所 A kind of silicon substrate fan-out package method and structure
US20210043586A1 (en) * 2019-08-08 2021-02-11 Fujitsu Limited Semiconductor device and electronic device
CN110581079A (en) * 2019-09-23 2019-12-17 合肥矽迈微电子科技有限公司 Fan-out type chip packaging method and fan-out type chip packaging body
CN112038305A (en) * 2020-10-12 2020-12-04 长电集成电路(绍兴)有限公司 Multi-chip ultrathin fan-out packaging structure and packaging method thereof
CN214848592U (en) * 2021-06-29 2021-11-23 成都氮矽科技有限公司 Panel-level fan-out type packaging structure of silicon-based GaN HEMT device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114334672A (en) * 2022-03-08 2022-04-12 上海泰矽微电子有限公司 Fan-out type packaging structure and packaging method
CN114361025A (en) * 2022-03-21 2022-04-15 宁波芯健半导体有限公司 GaN ultrathin chip fan-out type packaging structure and packaging method
CN114883279A (en) * 2022-07-12 2022-08-09 深圳市冠禹半导体有限公司 Gallium nitride device and packaging method thereof
CN114883279B (en) * 2022-07-12 2022-10-25 深圳市冠禹半导体有限公司 Packaging method of gallium nitride device
WO2024087083A1 (en) * 2022-10-27 2024-05-02 Innoscience (Zhuhai) Technology Co., Ltd. Semiconductor packaged device and method for manufacturing the same

Similar Documents

Publication Publication Date Title
CN113314480A (en) Panel-level fan-out type packaging structure and method for silicon-based GaN HEMT device
CN103872006B (en) Cascode circuit
CN103383921B (en) Semiconductor package part and forming method thereof
CN103972193B (en) Power transistor arrangement and method for manufacturing the same
CN103426837B (en) Semiconductor packages and the method for forming semiconductor packages
CN107039372A (en) Semiconductor structure and forming method thereof
CN102157408B (en) Through hole-interconnected wafer level MOSFET packaging structure and realization method
WO2023237064A1 (en) Four-pin to-247 encapsulation structure for power gallium nitride hemt device
CN214848592U (en) Panel-level fan-out type packaging structure of silicon-based GaN HEMT device
TW201234601A (en) Vertical semiconductor device and manufacturing method therefor
Majumdar et al. Review of integration trends in power electronics systems and devices
CN215933565U (en) Gallium nitride HEMT chip integration packaging structure and electronic device
CN102122670A (en) Groove-interconnected wafer level MOSFET encapsulation structure and implementation method
US11948927B2 (en) Semiconductor die with improved thermal insulation between a power portion and a peripheral portion, method of manufacturing, and package housing the die
CN215815838U (en) Gallium nitride HEMT chip integration packaging structure and electronic device
US11476242B2 (en) Cascode power electronic device packaging method and packaging structure thereof
WO2023249863A1 (en) Packages with backside mounted die and exposed die interconnects and methods of fabricating the same
CN113421913B (en) A kind of SOI chip, preparation method, intelligent power module, electric appliance and air conditioner
CN116190370A (en) A cascaded GaN power device packaging structure
CN213519942U (en) Packaging structure of gallium nitride device
Lee et al. A new package of high-voltage cascode gallium nitride device for high-frequency applications
CN102122671B (en) Rear through-hole interconnected wafer level MOSFET (metal oxide semiconductor field effect transistor) packaging structure and implementation method
CN113675096A (en) Packaging method and packaging structure of power electronic device connected in series
CN104979222A (en) Ultrathin MOSFET packaging structure and packaging method
CN201994303U (en) Through hole interconnection-type wafer-level MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) packaging structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination