CN113314405B - Manufacturing method of sloped field plate of semiconductor power device - Google Patents

Abstract

The invention discloses a method for manufacturing a semiconductor power device slope field plate, which comprises the steps of firstly, designing two gray scale photoetching plates corresponding to a slope region, then arranging uniform grids with the size smaller than photoetching resolution in the gray scale region of each photoetching plate, and opening holes in each grid on a chromium layer to manufacture a gray scale photoetching plate; and then, exposing the photoresist twice by taking the two gray scale photomasks as a mask, developing to generate a slope photoresist, performing plasma dry etching by taking the slope photoresist as the mask, and finally performing metal deposition and reactive ion etching to obtain the slope field plate. The method provided by the invention simplifies the process steps, reduces the process difficulty and cost, realizes the manufacture of the slope field plate by using fewer process steps and cost, and increases the selection of the range and the gradient of the slope field plate by double exposure compared with one-time exposure. The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and is used for manufacturing a slope field plate.

Description

Manufacturing method of sloped field plate of semiconductor power device

technical field

The invention belongs to the technical field of semiconductor technology, and relates to a method for preparing a junction terminal for improving the withstand voltage of a semiconductor power device, in particular to a method for fabricating a slope field plate of a semiconductor power device.

Background technique

In the field of semiconductor device preparation technology, field plate is one of the commonly used methods in junction termination technology. It mainly changes the surface potential distribution of the device, increases the radius of curvature of the curvature junction, prevents the surface electric field from being too concentrated, and improves the resistance of the device. pressure.

A conventional field plate is a biased field plate as shown in Figure 1a, which is formed by the contact metal of the N+ pole extending through the N+P junction, so it has the same potential as the N+ pole. The field plate, the underlying oxide layer and the silicon substrate form a MOS structure. When the reverse bias voltage is applied to the N+P junction, the surface of the silicon substrate of the field plate MOS structure is depleted, thereby expanding the area of the depletion region and increasing the radius of curvature of the depletion region, thereby improving the withstand voltage. After the bias field plate is used, the electric field of the silicon substrate under the field plate decreases and the distribution becomes uniform, but the electric force lines are concentrated at the edge of the field plate, forming a high peak electric field, which easily leads to the breakdown of the edge of the field plate.

According to the simulation results, it is found that the transverse electric field of the field plate decays approximately exponentially with the end point of the off-field plate. In order to overcome the defect of the breakdown caused by the concentration of electric field at the edge of the bias field plate, someone proposed a sloped field plate as shown in Fig. 1b. As the field plate extends to the left, the thickness of the oxide layer increases gradually, so that a high electric field peak will not be formed at the edge of the sloped field plate, which avoids the breakdown of the field plate edge. The concept of the sloped field plate is proposed, which can effectively reduce the peak electric field of the PN junction in theory and avoid the edge breakdown caused by the electric field concentration at the edge of the field plate, but it is very difficult to realize in the process.

At present, the multi-step field plate shown in Figure 1c is generally used to simulate the effect of the inclined field plate, but the realization of the multi-step field plate requires more layout and metallization steps, which increases the process complexity and process cost. FIG. 2 is a schematic diagram of the principle of grayscale lithography in the prior art of the present invention.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for manufacturing a slope field plate of a semiconductor power device. The method is based on the design of a grayscale lithography, and converts the slope into the transmittance change of two grayscale lithography plates, which simplifies the process. steps, reducing the difficulty and cost of the process, and realizing the fabrication of the slope field plate with fewer process steps and costs, and at the same time, compared with one exposure, the double exposure increases the selection of the range and gradient of the slope field plate.

The present invention is to realize the above-mentioned purpose, and the technical scheme adopted is as follows:

A manufacturing method of a semiconductor power device slope field plate, which is performed in the following sequence of steps:

1. Making grayscale lithography

① Make the first grayscale lithography

On the first lithography plate, the area corresponding to the slope field plate is divided into n grids with a uniform area of S, and then the chromium layer is opened in the center of each grid to obtain a first grayscale lithography plate ;

For the mth grid on the first grayscale lithography, the area of the opening in the chromium layer is S _m , and its transmittance a _1m =S _m /S;

②Make the second grayscale lithography

On the second lithography plate, the area corresponding to the slope field plate is divided into n grids with a uniform area S, and then the chromium layer is opened in the center of each grid to obtain a second grayscale lithography plate ;

For the mth grid on the second grayscale lithography plate, the area of the opening in the chromium layer is T _m , and its transmittance a _2m =T _m /S;

the n≥1, m∈[1,n];

Two, double exposure

First, the photoresist on the semiconductor device substrate with the surface growth medium layer is exposed for the first time by using the first grayscale lithography as a mask;

In the first exposure process, the exposure dose of the mth grid is d _1m ;

Next, the photoresist after the first exposure is exposed for the second time using the second grayscale photoresist as a mask, and the exposure dose is d _2m , and then developed, so far, the slope photoresist is obtained;

In the second exposure process, the exposure dose of the mth grid is d _2m ;

Steps 1 and 2 satisfy D _m = d _1m *S _m /S+d _2m *T _m /S, where D _m is the total exposure amount of the photoresist area corresponding to the mth grid;

3. Plasma dry etching

Using the slope photoresist as a mask, plasma dry etching is performed on the dielectric layer, so that the etching ratio of the dielectric layer and the slope photoresist is 1:1, and a slope-shaped dielectric layer is obtained;

Fourth, the production of slope field board

Metal deposition and reactive ion etching were performed on the slope-shaped SiO ₂ to produce sloped field plates.

As a limitation, the sloped field plate is a one-dimensional transversely structured sloped field plate;

In the step 1, the n grids are all square grids with side length A, S=A ² ;

In step ①, in the mth grid, the chromium layer is provided with a square hole with a side length of B _m , S _m =B _m ² ;

In step ②, in the mth grid, a square hole with a side length of C _m is opened in the chromium layer, and T _m =C _m ² .

As a second limitation, the sloping field plate is a sloping field plate with a one-dimensional transverse structure;

In the step 1, the n grids are all square grids with side length A, S=A ² ;

In step ①, in the mth grid, the chromium layer is provided with k square holes with side length e, S _m =k*e ² , where k≥1;

In step ②, in the mth grid, j square holes with side length e are opened in the chromium layer, T _m =j*e ² , where j≥1.

As the third limitation: the slope field plate is a slope field plate with a circular arc track-shaped structure;

In the step 1, divide n arc-shaped grid stripes with a uniform radius of ΔR along the direction of the slope change,

In step ①, in the mth grid, a circular arc opening with a radius change of △r _1m is performed on the chromium layer at the center of the grid, a _1m =△r _1m /△R;

In step ②, in the mth grid, a circular arc opening with a radius change of Δr _2m is performed on the chromium layer at the center of the grid, a _2m =Δr _2m /ΔR.

Because the present invention adopts the above-mentioned technical scheme, compared with the prior art, the technical progress achieved is:

(1) The present invention converts the slope into the retained thickness after development, and then according to the relationship between the retained thickness and the exposure intensity, and then converts the slope into the light transmittance change of two grayscale lithography plates; The ratio of the light transmission area in the grid to the grid area is made by making the corresponding openings in the chromium layer of the lithography; Process difficulty and cost, using less process steps and cost to realize the production of slope field plate;

(2) Compared with one exposure, the double exposure of the present invention increases the selection of the range and gradient of the slope field plate;

(3) The technological process of the present invention is compatible with the existing technology.

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and is used for manufacturing a slope field plate.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the specification, and are used to explain the present invention together with the embodiments of the present invention, and do not constitute a limitation to the present invention.

In the attached image:

1a is a schematic structural diagram of a common bias field plate in the prior art of the present invention;

Fig. 1b is a schematic diagram of the structure of the slope field plate in the prior art of the present invention;

Fig. 1c is a schematic diagram of the structure of a stepped field plate in the prior art of the present invention;

2 is a schematic diagram of the principle of grayscale lithography in the prior art of the present invention;

3a is a schematic diagram of the opening of the grayscale area of the lithography plate according to Embodiment 1 of the present invention;

3b is a schematic diagram of openings in the grayscale area of the lithography plate according to Embodiment 2 of the present invention;

4 is a schematic diagram of openings in the grayscale area of a lithography plate according to Embodiment 3 of the present invention;

5 is a partial process flow diagram of Embodiment 1 of the present invention;

FIG. 6 is a comparison diagram of single exposure and double exposure with the same total dose in Example 4 of the present invention.

Detailed ways

The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, but not to limit the present invention.

Embodiment 1 A manufacturing method of a semiconductor power device slope field plate

The sloping field plate in this embodiment is a sloping field plate with a one-dimensional transverse structure.

This embodiment is carried out according to the following sequence of steps:

1. Making grayscale lithography

In this step, two grayscale lithography plates need to be made; for the convenience of expression, this embodiment takes the lithography plate shown in FIG. 3 as an example for description;

① Make the first grayscale lithography

On the first lithography plate, the area corresponding to the slope field plate is divided into n uniform square grids with side length A, and then the chromium layer is opened in the center of each grid to obtain the first grayscale lithography version, the area of each grid is S=A ² ;

As shown in Figure 3a, for the mth grid on the first grayscale lithography plate, the chromium layer has a square hole with a side length of B _m , and the area of the opening in the chromium layer is S _m =B _m ² , and its light transmittance a _1m =S _m /S;

②Make the second grayscale lithography

The second lithography is the same as the first lithography;

First, according to the same method as step ①, the area corresponding to the slope field plate on the second lithography plate is divided into n uniform square grids with side length A, and then the chromium layer is opened in the center of each grid. hole to obtain a second grayscale lithography, and the area of each grid is S=A ² ;

For the mth grid on the second grayscale lithography plate, square holes with side length C _m are opened in the chromium layer, the area of the openings in the chromium layer is T _m =C _m ² , and its transmittance a _2m =T _m /S;

In steps ① and ②, n≥1, m∈[1,n];

Two, double exposure

As shown in FIG. 5 , firstly, the photoresist grown on the SiO ₂ dielectric layer on the surface of the semiconductor device is exposed for the first time by using the first grayscale lithography as a mask;

In the first exposure process, the exposure dose of the mth grid is d _1m ;

Next, the photoresist after the first exposure is exposed for a second time by using the second grayscale photoresist as a mask, and then developed, so far, the slope photoresist is obtained;

In the second exposure process, the exposure dose of the mth grid is d _2m ;

Steps 1 and 2 satisfy D _m = d _1m *S _m /S+d _2m *T _m /S, where D _m is the total exposure amount of the photoresist area corresponding to the mth grid;

3. Plasma dry etching

Using the slope photoresist as a mask, plasma dry etching is performed on the SiO ₂ dielectric layer, so that the etching ratio of the SiO ₂ dielectric layer and the slope photoresist is 1:1, and a slope-shaped SiO ₂ dielectric layer is obtained;

Fourth, the production of slope field board

Metal deposition and reactive ion etching are performed on the slope-shaped SiO ₂ dielectric layer to obtain a slope field plate.

In this embodiment, the side length A of the grid divided on the first lithography plate and the second lithography plate is smaller than the resolution of the lithography machine. The side length A of the square grid needs to be less than 380nm.

To realize the sloped field plate, it is necessary to obtain a lithography plate with a linear change in grayscale. For a one-dimensional transverse sloped field plate, the realization method is as follows: according to the range of the exposure depth and the received ultraviolet light dose, and the positive photoresist The maximum thickness and minimum thickness remaining after development are obtained to obtain the corresponding minimum and maximum transmittance.

Embodiment 2 A manufacturing method of a semiconductor power device sloped field plate

The sloping field plate in this embodiment is a sloping field plate with a one-dimensional transverse structure.

The process flow of this embodiment is roughly the same as that of Embodiment 1, except that: in Embodiment 1, a square hole is opened in each grid; Variation in the number of optical apertures.

The steps of making the first grayscale lithography and the second grayscale lithography in this embodiment are as follows:

In this step, two grayscale lithography plates need to be made; for the convenience of expression, this embodiment takes the lithography plate of FIG. 3 b as an example for description;

A1. Make the first grayscale lithography

First, on the first lithography plate, the area corresponding to the slope field plate is divided into n uniform square grids with side length A, S=A ² ;

Then, the chromium layer is perforated in the center of each grid to obtain a first grayscale lithography;

Taking the mth grid as an example, the chrome layer has k square holes with side length e, S _m =k*e ² , where k≥1;

A2. Make the second grayscale lithography

First, on the second lithography plate, the area corresponding to the slope field plate is divided into n uniform square grids with side length A, S=A ² ;

Then, the chromium layer is perforated in the center of each grid to obtain a second grayscale lithography;

Taking the mth grid as an example, the chrome layer has j square holes with side length e, T _m =j*e ² , where j≥1.

In steps A1 and A2, n≥1, m∈[1,n].

Embodiment 3 A fabrication method of a semiconductor power device sloped field plate

The process flow of this embodiment is substantially the same as that of Embodiment 1, the difference is that the slope field plate of this embodiment is a slope field plate with a circular arc racetrack structure; the method of opening the chromium layer is also different.

The steps of making the first grayscale lithography and the second grayscale lithography in this embodiment are as follows:

In this step, two grayscale lithography plates need to be made; for the convenience of expression, this embodiment takes the lithography plate shown in FIG. 4 as an example for description;

B1. Make the first grayscale lithography

First, on the first lithography plate, divide n arc-shaped stripe grids with a uniform radius of ΔR along the direction of the slope change;

Then, the chromium layer is perforated in the center of each grid to obtain a first grayscale lithography;

Taking the mth grid as an example, the chrome layer is opened in a circular arc shape with a radius change of △r _1m at the center of the grid. Obviously, its transmittance a _1m =△r _1m /△R;

B2. Making the second grayscale lithography

First, on the second lithography plate; in the same way as in step B1, divide n arc-shaped grid stripes with a uniform radius of ΔR along the direction of the slope change;

Then, the chromium layer is perforated in the center of each grid to obtain a second grayscale lithography;

Taking the mth grid as an example, the chrome layer is opened in a circular arc shape with a radius change of Δr _2m at the center of the grid. Obviously, its transmittance a _2m = Δr _2m /ΔR.

In steps B1 and B2, n≥1, m∈[1,n].

For Embodiments 1-3, only the schematic diagrams of making the first grayscale lithography are shown in FIGS. 3 and 4. It can be seen from the text description that, in fact, in a specific embodiment, the second grayscale is made The method of dividing the grid when making the first grayscale lithography is exactly the same as the method of dividing the grid when making the first grayscale lithography, just to meet the total exposure dose of the first grayscale lithography and the second grayscale lithography. It is required that the area of the openings of the chromium layer in a specific grid is different, and the size of the grid is smaller than the lithography resolution.

Example 4 Comparison of single exposure and double exposure with the same total dose

Double exposure means that after the photoresist is coated on the wafer, two exposures are performed on the same photoresist using different masks. While double exposures mostly use adjacent exposures, where each step is applied to the unexposed photoresist, it is also possible to stack two partial exposures to produce gray levels that cannot be achieved with a single exposure. As shown in Figure 6, for the comparison of single exposure and double exposure with the same total dose, at a certain exposure dose, even if double exposure is used, dividing the total dose into two amounts has no effect on the final exposure depth.

The exposure dose is the product of the light intensity I and the exposure time t, and the double exposure dose d _de is defined as the sum of the individual doses for each exposure, so the total exposure dose can be written as d _de =I ₁ t ₁ +I ₂ t ₂ , And its exposure depth is the same as the depth of one exposure with dose d _de . Due to the certain processing accuracy of the photolithography plate, the length slope of the non-uniform part of the photoresist thickness formed after one exposure and development is limited, and the double exposure method provided in Examples 1-4 can increase its range.

Claims (4)

1. A method for manufacturing a semiconductor power device slope field plate is characterized by comprising the following steps:

first, make the gray scale photolithography mask

First, a first gray scale photolithography plate is manufactured

Dividing a region corresponding to the slope field plate on a first photoetching plate into n grids with uniform areas of S, and then opening a chromium layer at the center of each grid to obtain a first gray photoetching plate;

for the mth grid on the first gray scale photoetching plate, the area of the openings of the chromium layer is S _m Transmittance of a thereof _1m =S _m /S；

Second Gray level photolithography

Dividing a region corresponding to the slope field plate on a second photoetching plate into n grids with uniform areas of S, and then opening a chromium layer at the center of each grid to obtain a second gray photoetching plate;

for the mth grid on the second gray scale reticle, the area of the openings of the chromium layer is T _m Light transmittance of a thereof _2m =T _m /S；

N is more than or equal to 1, and m belongs to [1, n ];

the side length or the size of the grids divided on the first photoetching plate and the second photoetching plate is smaller than the resolution of the photoetching machine;

two and two exposures

Firstly, taking a first gray scale photoetching plate as a mask to carry out first exposure on photoresist on a semiconductor device substrate with a surface growth dielectric layer;

during the first exposure, the exposure dose of the m-th grid is d _1m ；

Then, taking the second gray scale reticle as a mask to carry out the second exposure on the photoresist after the first exposure, wherein the exposure dose is d _2m Then developing to obtain the slope photoresist;

during the second exposure, the exposure dose of the m-th grid is d _2m ；

Step one and stepStep two satisfies D _m = d _1m *S _m /S+d _2m *T _m S, wherein D _m The total exposure amount of the photoresist area corresponding to the mth grid is calculated;

third, plasma dry etching

Performing plasma dry etching on the dielectric layer by taking the slope photoresist as a mask to enable the etching ratio of the dielectric layer to the slope photoresist to be 1:1, and obtaining a slope-shaped dielectric layer;

fourthly, manufacturing a slope field plate

And carrying out metal deposition and reactive ion etching on the slope-shaped dielectric layer to obtain the slope field plate.

2. The method for manufacturing the semiconductor power device ramp field plate according to claim 1, wherein the ramp field plate is a one-dimensional lateral structure ramp field plate;

in the first step, n grids are square grids with side length of A, and S = A ² ；

In the mth grid, the chromium layer is provided with a side length of B _m Square hole of (S) _m =B _m ² ；

In the mth grid, the chromium layer is provided with a side length of C _m Square hole of (a), T _m =C _m ² 。

3. The method of claim 1, wherein the sloped field plate is a one-dimensional lateral structure;

in the first step, the n grids are square grids with the side length of A, and S = A ² ；

In the mth grid, the chromium layer is provided with k square holes with the side length of e, and S _m =k*e ² Wherein k is more than or equal to 1;

in the mth grid, the chromium layer is provided with j square holes with the side length of e and T _m =j*e ² Wherein j is more than or equal to 1.

4. The method for manufacturing the semiconductor power device ramp field plate according to claim 1, wherein: the slope field plate is a slope field plate with an arc runway-shaped structure;

in the first step, n arc grid stripes with uniformly changed deltaR radius are divided along the direction of slope change,

in the mth grid, the chromium layer is subjected to radius variation delta r at the center of the grid _1m Circular arc-shaped opening of (a) _1m =△r _1m /△R；

Step two, in the mth grid, the chromium layer is subjected to radius variation delta r at the center of the grid _2m Circular arc-shaped opening of (a) _2m =△r _2m /△R。

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