CN113312274B - Data sorting method of memory, memory storage device and control circuit unit - Google Patents

Abstract

The invention provides a memory data organizing method, a memory storage device and a memory control circuit unit, which are used in a memory storage device including a rewritable non-volatile memory module. The data organizing method of the memory includes: receiving an instruction from a host system, wherein the instruction includes a data interval; and erasing entities of multiple physical erase units based on logical estimates of multiple logical block addresses of the data interval and logical block address mapping. The estimated value is used to calculate the data fragmentation degree; and based on the data fragmentation degree and the threshold value, it is determined whether to perform a data defragmentation operation to move the data in the physical erasure unit according to the logical block address.

Description

Memory data organization method, memory storage device and control circuit unit

Technical field

The present invention relates to a memory data sorting technology, and in particular to a memory data sorting method, a memory storage device and a memory control circuit unit.

Background technique

Digital cameras, mobile phones and MP3 players have grown rapidly in recent years, causing consumer demand for storage media to increase rapidly. Since the rewriteable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, it is very suitable for built-in Among the various portable multimedia devices exemplified above.

However, if the write data from the host system belongs to discontinuous data, for example, the write data belongs to discontinuous logical sub-units, then the logical sub-units in one logical unit may be mapped to different physical erase units. Entity programming unit. In this case, when the host system wants to read data belonging to multiple logical subunits corresponding to consecutive addresses in a logical unit, the controller may need to load different logical-entity mapping tables to find out the data scattered in different entities. Erase multiple physical programmed units of a unit. Afterwards, the controller needs to send multiple read instructions to read data from these scattered physical programming units, so that it takes a long time to perform the read operation, causing the data read speed to slow down.

Contents of the invention

The invention provides a memory data sorting method, a memory storage device and a memory control circuit unit, which can determine whether a data sorting operation is required.

Embodiments of the present invention provide a memory data organization method for use in a memory storage device including a rewritable non-volatile memory module. The data organizing method of the memory includes: receiving an instruction from a host system, wherein the instruction includes a data interval; logical estimates of multiple logical block addresses according to the data interval and multiple logical block address mappings. The physical estimation value of the physical erasure unit calculates the data scattering degree; and determines whether to perform a data sorting operation to move the data in the physical erasure unit according to the logical block address according to the data scattering degree and the threshold value.

In an embodiment of the present invention, the instructions include fragment reassembly instructions.

In an embodiment of the present invention, the method is calculated based on the logical estimated value of the logical block address of the data interval and the physical estimated value of the physical erasure unit mapped by the logical block address. The step of describing the data scatter degree includes: calculating the said data according to the number of the logical block addresses in the data interval, the capacity of the logical block address and the physical page capacity of the rewritable non-volatile memory module. a logical estimated value; determining the physical estimated value according to the number of physical pages in the physical erasure unit mapped by the logical block address; and calculating a ratio of the logical estimated value to the physical estimated value to determine the Data scatter.

In an embodiment of the present invention, according to the number of the logical block addresses of the data interval, the capacity of the logical block address and all the values of the rewritable non-volatile memory module The step of calculating the logical estimated value of the physical page capacity includes: calculating the data capacity of the data interval according to the number of the logical block addresses and the capacity of the logical block address; and according to the data The logical estimate is calculated using the capacity and the physical page capacity of the rewritable non-volatile memory module.

In an embodiment of the present invention, the step of determining whether to perform the data sorting operation to move the data in the physical erasure unit according to the logical block address according to the data fragmentation degree and the threshold value includes: When the data fragmentation is not greater than the first threshold, the data sorting operation is performed according to the logical block address.

In an embodiment of the present invention, the method is calculated based on the logical estimated value of the logical block address of the data interval and the physical estimated value of the physical erasure unit mapped by the logical block address. The step of describing the data scatter degree includes: determining the logical estimated value according to the number of logical pages corresponding to the logical block address of the data interval; and determining the logical estimation value according to the physical erasure unit corresponding to the logical block address mapping. The number of entity planes determines the entity estimate value; and the data scatter degree is calculated based on the logical estimate value and the entity estimate value.

In an embodiment of the present invention, the step of determining whether to perform the data sorting operation to move the data in the physical erasure unit according to the logical block address according to the data fragmentation degree and the threshold value includes: Calculate a second threshold based on the data fragmentation and the third threshold; and the number of pages configured in one of the physical planes corresponding to the physical erasure unit mapped by the logical block address is not less than the At the second threshold, the data sorting operation is performed according to the logical block address.

The invention proposes a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The connection interface unit is used for coupling to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to receive instructions from the host system, where the instructions include data intervals. The memory control circuit unit is further configured to calculate a data scatter degree based on logical estimation values of multiple logical block addresses of the data interval and physical estimation values of multiple physical erasure units mapped by the logical block address. And the memory control circuit unit is also used to determine whether to perform a data sorting operation according to the data scatter degree and the threshold value to move the data in the physical erasure unit according to the logical block address.

In an embodiment of the present invention, the instructions include fragment reassembly instructions.

In an embodiment of the present invention, the memory control circuit unit is further configured to perform physical erasure based on the logical estimate of the logical block address of the data interval and the physical erase of the logical block address mapping. The operation of calculating the data scatter degree based on the physical estimate value of the unit includes: based on the number of the logical block addresses of the data interval, the capacity of the logical block address and the rewritable non-volatile Calculate the logical estimated value based on the physical page capacity of the memory module; determine the physical estimated value according to the number of physical pages in the physical erasure unit mapped by the logical block address; and calculate the logical estimated value and the The ratio of entity estimates to determine the data scatter.

In an embodiment of the present invention, according to the number of the logical block addresses of the data interval, the capacity of the logical block address and all the values of the rewritable non-volatile memory module The operation of calculating the logical estimated value of the physical page capacity includes: calculating the data capacity of the data interval according to the number of the logical block addresses and the capacity of the logical block address; and according to the data The logical estimate is calculated using the capacity and the physical page capacity of the rewritable non-volatile memory module.

In an embodiment of the present invention, the memory control circuit unit is further used to determine whether to perform the data sorting operation according to the data fragmentation degree and the threshold value to move the physical erase according to the logical block address. The operation of removing data in the unit includes: performing the data sorting operation according to the logical block address when the data fragmentation degree is not greater than a first threshold.

In an embodiment of the present invention, the memory control circuit unit is further configured to perform physical erasure based on the logical estimate of the logical block address of the data interval and the physical erase of the logical block address mapping. The operation of calculating the data scatter degree based on the physical estimated value of the unit includes: determining the logical estimated value based on the number of logical pages corresponding to the logical block address of the data interval; and determining the logical estimated value based on the logical block address mapping. The number of entity planes corresponding to the entity erasure unit determines the entity estimate value; and the data scatter degree is calculated based on the logical estimate value and the entity estimate value.

In an embodiment of the present invention, the memory control circuit unit is further used to determine whether to perform the data sorting operation to move the entity according to the logical block address according to the data fragmentation degree and the threshold value. The operation of erasing the data in the unit includes: calculating a second threshold based on the data scatter degree and a third threshold; and erasing one of the entities corresponding to the physical erasure unit mapped to the logical block address. When the number of pages configured in the plane is not less than the second threshold, the data sorting operation is performed according to the logical block address.

The present invention proposes a memory control circuit unit for controlling a memory storage device including a rewritable non-volatile memory module, and the memory control circuit unit includes a host interface, a memory interface and a memory management circuit. The host interface is used to couple to a host system. The memory interface is used to couple to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory control circuit unit is configured to receive instructions from the host system, where the instructions include data intervals. The memory control circuit unit is further configured to calculate a data scatter degree based on logical estimation values of multiple logical block addresses of the data interval and physical estimation values of multiple physical erasure units mapped by the logical block address. And the memory control circuit unit is also used to determine whether to perform a data sorting operation according to the data scatter degree and the threshold value to move the data in the physical erasure unit according to the logical block address.

In an embodiment of the present invention, the instructions include fragment reassembly instructions.

In an embodiment of the present invention, the memory control circuit unit is further configured to perform physical erasure based on the logical estimate of the logical block address of the data interval and the physical erase of the logical block address mapping. The operation of calculating the data scatter degree based on the physical estimate value of the unit includes: based on the number of the logical block addresses of the data interval, the capacity of the logical block address and the rewritable non-volatile Calculate the logical estimated value based on the physical page capacity of the memory module; determine the physical estimated value according to the number of physical pages in the physical erasure unit mapped by the logical block address; and calculate the logical estimated value and the The ratio of entity estimates to determine the data scatter.

In an embodiment of the present invention, according to the number of the logical block addresses of the data interval, the capacity of the logical block address and all the values of the rewritable non-volatile memory module The operation of calculating the logical estimated value of the physical page capacity includes: calculating the data capacity of the data interval according to the number of the logical block addresses and the capacity of the logical block address; and according to the data The logical estimate is calculated using the capacity and the physical page capacity of the rewritable non-volatile memory module.

In an embodiment of the present invention, the memory control circuit unit is further used to determine whether to perform the data sorting operation according to the data fragmentation degree and the threshold value to move the physical erase according to the logical block address. The operation of removing data in the unit includes: performing the data sorting operation according to the logical block address when the data fragmentation degree is not greater than a first threshold.

In an embodiment of the present invention, the memory control circuit unit is further configured to perform physical erasure based on the logical estimate of the logical block address of the data interval and the physical erase of the logical block address mapping. The operation of calculating the data scatter degree based on the physical estimated value of the unit includes: determining the logical estimated value based on the number of logical pages corresponding to the logical block address of the data interval; and determining the logical estimated value based on the logical block address mapping. The number of entity planes corresponding to the entity erasure unit determines the entity estimate value; and the data scatter degree is calculated based on the logical estimate value and the entity estimate value.

In an embodiment of the present invention, the memory control circuit unit is further used to determine whether to perform the data sorting operation according to the data fragmentation degree and the threshold value to move the physical erase according to the logical block address. The operation of erasing the data in the unit includes: calculating a second threshold based on the data scatter degree and a third threshold; and erasing one of the physical planes corresponding to the physical erase unit mapped in the logical block address. When the number of pages configured in is not less than the second threshold, the data sorting operation is performed according to the logical block address.

Based on the above, the memory data sorting method, memory storage device and memory control circuit unit provided by embodiments of the present invention can be based on the logical estimation values and logical block address mapping of multiple logical block addresses in the data interval included in the instruction. Calculate the data scatter degree based on the entity estimation values of multiple entity erasure units, and compare the data scatter degree with the threshold to determine whether the data is concentrated or scattered. In this way, it can be determined whether this data interval requires data sorting operation, and thereby improve the speed of reading data.

Description of drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment;

Figure 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment;

Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

6 and 7 are exemplary schematic diagrams of management entity blocks according to an exemplary embodiment of the present invention;

Figure 8 is a flow chart of a data organizing method in a memory according to an exemplary embodiment of the present invention;

Figure 9 is a flow chart of a data organizing method in a memory according to an exemplary embodiment of the present invention;

FIG. 10 is a flow chart of a memory data organizing method according to an exemplary embodiment of the present invention.

Explanation of reference numbers

10, 30: Memory storage device

11, 31: Host system

110: System bus

111: Processor

112: Random Access Memory

113: Read-only memory

114: Data transmission interface

12: Input/output (I/O) device

20: Motherboard

201: USB flash drive

202: Memory card

203: Solid state drive

204: Wireless memory storage device

205: Global Positioning System Module

206: Network interface card

207: Wireless transmission device

208: Keyboard

209: Screen

210: Speaker

32: SD card

33: CF card

34: Embedded storage device

341: Embedded multimedia card

342: Embedded multi-chip package storage device

402: Connect interface unit

404: Memory control circuit unit

406: Rewritable non-volatile memory module

410(0)~410(N): Physical erase unit

502: Memory management circuit

504: Host interface

506: Memory interface

508: Error checking and correction circuit

510: Buffer memory

512: Power management circuit

602: Data area

604: Idle area

606: System area

608: Replacement area

LBA(0)～LBA(H): logical block address

LZ(0)～LZ(M): logical area

S802～S806, S902～S912, S1002～S1014: steps.

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and description to refer to the same or similar parts.

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit unit). Typically a memory storage device is used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another exemplary embodiment.

Referring to FIGS. 1 and 2 , the host system 11 generally includes a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 and a data transmission interface 114 . The processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 are all coupled to a system bus 110 .

In this exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 can write data to or read data from the memory storage device 10 via the data transmission interface 114 . In addition, the host system 11 is coupled to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O device 12 via system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be coupled to the memory storage device 10 via wired or wireless methods. The memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203 or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication Storage (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (eg, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to various I/Os such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an example embodiment, the host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Please refer to FIG. 3 . In another exemplary embodiment, the host system 31 can also be a digital camera, video camera, communication device, audio player, video player or tablet computer, and the memory storage device 30 can be used therefor. Various non-volatile memory storage devices such as SD card 32, CF card 33 or embedded storage device 34. The embedded storage device 34 includes an embedded multimedia card (embeddedMMC, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342. The memory module is directly coupled to the substrate of the host system. embedded storage device.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

The connection interface unit 402 is used to couple the memory storage device 10 to the host system 11 . The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402 . In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be in compliance with the Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, high-speed peripheral component interface (Peripheral Component Interconnect Express, PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) Interface standards, Ultra High Speed-II (UHS-II) interface standards, Memory Stick (MS) interface standards, MCP interface standards, MMC interface standards, eMMC interface standards, Universal Flash Memory (Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 and the memory control circuit unit 404 may be packaged in a chip, or the connection interface unit 402 may be arranged outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used to execute multiple logic gates or control instructions implemented in hardware or firmware and write and read data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 Operations such as fetching and erasing.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and used to store data written by the host system 11 . The rewritable non-volatile memory module 406 may be a single-level cell (SLC) NAND flash memory module (that is, a flash memory module that can store 1 bit in one memory cell), a multi-level Memory cell (Multi Level Cell, MLC) NAND type flash memory module (that is, a flash memory module that can store 2 bits in one memory cell), Triple Level Cell (Triple Level Cell, TLC) NAND type flash memory module (that is, a flash memory module that can store 3 bits in one storage unit), Quad Level Cell (QLC) NAND flash memory module (that is, a flash memory module that can store 4 bits in one storage unit) flash memory module), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits based on changes in voltage (hereinafter also referred to as critical voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell." As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple memory states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the storage units of the rewritable non-volatile memory module 406 may constitute multiple physical programming units, and these physical programming units may constitute multiple physical erasing units. Specifically, memory cells on the same word line may form one or more physical programming units. If each storage unit can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the Least Significant Bit (LSB) of a storage unit belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a storage unit belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit will be greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. Reliability of programmed units.

In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the entity programming unit may be an entity page (page) or an entity sector (sector). If the physical programming units are physical pages, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors to store user data, while the redundant bit area is used to store system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other example embodiments, the data bit zone may also include 8, 16, or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of erased memory cells. For example, the physical erasure unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 and a memory interface 506 .

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions will be executed to perform data writing, reading, erasing and other operations. When the operation of the memory management circuit 502 is described below, it is equivalent to describing the operation of the memory control circuit unit 404.

In this exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware form. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions will be executed by the microprocessor unit to perform data writing, reading, erasing and other operations.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in code form (for example, a system area in the memory module dedicated to storing system data). . In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store the data in the rewritable non-volatile memory module. The control instructions in 406 are loaded into the random access memory of the memory management circuit 502 . Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or memory cell groups of the rewritable non-volatile memory module 406 . The memory writing circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory reading circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erasure circuit is used to issue an erasure instruction sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 406 and data to be read from the rewritable non-volatile memory module 406 . The write command sequence, the read command sequence and the erase command sequence may respectively include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding writing, reading and erasing. Divide and other operations. In an exemplary embodiment, the memory management circuit 502 can also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct the execution of corresponding operations.

Host interface 504 is coupled to memory management circuit 502 . Memory management circuitry 502 may communicate with host system 11 through host interface 504. The host interface 504 can be used to receive and identify instructions and data transmitted by the host system 11 . For example, instructions and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504 . In addition, the memory management circuit 502 can transmit data to the host system 11 through the host interface 504 . In this example embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto. The host interface 504 may also be compatible with the PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, and MS standard. , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is coupled to the memory management circuit 502 and used to access the rewritable non-volatile memory module 406 . That is to say, the data to be written to the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 through the memory interface 506 . Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence instructing to write data, a read instruction sequence instructing to read data, an erase instruction sequence instructing to erase data, and to instruct various memory operations (e.g., change read corresponding instruction sequence to obtain voltage levels or perform garbage collection operations, etc.). These instruction sequences are generated, for example, by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506 . These command sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or codes. For example, the read instruction sequence will include the read identification code, memory address and other information.

In an exemplary embodiment, the memory control circuit unit 404 also includes an error checking and correction circuit 508, a buffer memory 510 and a power management circuit 512.

The error checking and correcting circuit 508 is coupled to the memory management circuit 502 and is used to perform error checking and correcting operations to ensure the accuracy of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 generates a corresponding error correcting code (ECC) and /or error detecting code (EDC), and the memory management circuit 502 will write the data corresponding to this write instruction and the corresponding error correction code and/or error checking code into the rewritable non-volatile memory In module 406. Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will also read the error correction code and/or error checking code corresponding to the data, and the error checking and correction circuit 508 will This error correction code and/or error checking code performs error checking and correction operations on the data being read.

The buffer memory 510 is coupled to the memory management circuit 502 and used to temporarily store data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . The power management circuit 512 is coupled to the memory management circuit 502 and used to control the power supply of the memory storage device 10 .

In an exemplary embodiment, the rewritable non-volatile memory module 406 of FIG. 4 is also called a flash memory module, and the memory control circuit unit 404 is also called a flash memory module for controlling the flash memory module. memory controller. In an exemplary embodiment, the memory management circuit 502 of FIG. 5 is also called a flash memory management circuit.

6 and 7 are exemplary schematic diagrams of management entity blocks according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory control circuit unit 404 (or the memory management circuit 502) will logically group the physical erasure units 410(0)˜410(N) into a data area 602, an idle area 604, a system area 606 and a replacement area. 608.

The physical erase units logically belonging to the data area 602 and the free area 604 are used to store data from the host system 11 . Specifically, the physically erased units of the data area 602 are regarded as the physically erased units that have stored data, and the physically erased units of the free area 604 are used to replace the physical erased units of the data area 602 . That is to say, when receiving a write command and data to be written from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) will use the physical erase unit to extract the data from the idle area 604 to write the data. , to replace the physically erased unit of the data area 602.

The physical erasure unit logically belonging to the system area 606 is used to record system data. For example, the system data includes information about the manufacturer and model of the rewritable non-volatile memory module, the number of physical erasure units of the rewritable non-volatile memory module, the number of physical programming units for each physical erasure unit, etc. .

The physical erase units logically belonging to the replacement area 608 are used for the bad physical erase unit replacement process to replace the damaged physical erase units. Specifically, if there are still normal physical erasure units in the replacement area 608 and the physical erasure units in the data area 602 are damaged, the memory control circuit unit 404 (or the memory management circuit 502) will extract the normal physical erasure units from the replacement area 608. Use the physical erasure unit to replace the damaged physical erasure unit.

In particular, the number of physical erase units in the data area 602, the free area 604, the system area 606 and the replacement area 608 will vary according to different memory specifications. In addition, it must be understood that during the operation of the memory storage device 10 , the grouping relationship between the physical erasure unit and the data area 602 , the free area 604 , the system area 606 and the replacement area 608 may dynamically change. For example, when the physical erasure unit in the free area 604 is damaged and replaced by the physical erasure unit in the replacement area 608, the physical erasure unit originally in the replacement area 608 will be associated with the free area 604.

Referring to FIG. 7 , the memory control circuit unit 404 (or the memory management circuit 502 ) configures the logical block addresses LBA(0)˜LBA(H) to map the physical erase unit of the data area 602 , where each logical block address A physical programming unit having multiple logical addresses to map corresponding physical erasure units. Moreover, when the host system 11 wants to write data to a logical address or update data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) will extract a physical erase unit from the idle area 604 as a function. The physical erase unit is moved to write data to alternate the physical erase units of the data area 602. Moreover, when the physical erasure unit as the active physical erasure unit is full, the memory management circuit 502 will extract an empty physical erasure unit from the idle area 604 as an active physical erasure unit to continue writing. Update data corresponding to the write command from the host system 1000 is entered. In addition, when the number of available physical erase units in the free area 604 is less than a preset value, the memory management circuit 502 will perform a garbage collection operation (also known as a valid data merging operation) to organize the data in the data area 602 Valid data, so as to re-associate the physical erase units in the data area 602 that do not store valid data to the idle area 604.

It should be noted that when the operation of the memory control circuit unit 404 is described below, it can be regarded as describing the operation of the memory management circuit 502 .

In order to solve the problem of slow data reading speed caused by continuous data being scattered in different physical pages, the data organization method of the memory in this embodiment is used in the memory storage device 10 including the rewritable non-volatile memory module 406. You can decide whether to reshape the data by analyzing whether it is concentrated or scattered. In another embodiment, whether to reshape the data can also be determined by analyzing whether the data is evenly distributed in each channel. In yet another embodiment, it is possible to simultaneously analyze whether the data is concentrated or scattered, and whether the data is evenly distributed in each channel to determine whether to reorganize the data.

The memory control circuit unit 404 receives instructions from the host system 11 . The instruction transmitted by the host system 11 is a defragment instruction, and the instruction includes a data interval. This data interval is the range within which the host system 11 determines that data sorting operation is required.

In this embodiment, after receiving the instruction from the host system 11, the memory control circuit unit 404 can calculate the logical estimation values of multiple logical block addresses (Logical Block Address, LBA) in the data interval and the number of mappings of these logical block addresses. The entity estimation value of each entity erasure unit is used to calculate the data scatter. Furthermore, the memory control circuit unit 404 can determine whether to perform a data sorting operation to move the data in the physical erasure unit according to the logical block address according to the data fragmentation degree and a threshold value. The memory control circuit unit 404 performs a data sorting operation and can copy the physical erasure units corresponding to the respective mappings of the consecutive logical subunits in the logical block address to the same physical erasure unit according to the logical block address. Here, continuous logical subunits means that the logical block address of one logical subunit continues after the logical block address of another logical subunit. In other words, the starting logical block address of one logical subunit is continued after the ending logical block address of another logical subunit. It should be noted that those skilled in the art should know how to perform data sorting operations, so they will not be described in detail here.

In the first embodiment, the degree of data scatter is determined by analyzing whether the data is concentrated or scattered. That is, whether the data is concentrated or scattered is determined by judging the number of physical pages that the physical erasure units corresponding to the data are actually distributed on the physical page, and whether to reorganize the data is decided based on the judgment result.

In detail, assume that the capacity of a physical page is 16K, and the instruction received by the memory control circuit unit 404 from the host system 11 includes a data interval of a continuous logical row address LCA(0)~LCA(7), a total of 8 4K data is 32K data. Ideally, 32K of data only needs to be stored in 2 physical pages. In other words, under the condition of minimum physical configuration, 32K data is arranged in 32/16 = 2 physical pages, and the memory control circuit unit 404 only needs to read the rewritable non-volatile memory module 406 twice. All data can be read. However, if under the maximum physical configuration, 32K data is arranged in 32/4 = 8 physical pages, the memory control circuit unit 404 needs to read the rewritable non-volatile memory module 406 eight times before it can be read. fetch all the data, resulting in slower reading speed. Based on this, the method provided by this embodiment calculates the logical estimate value and the entity estimate value, and determines the data scatter degree based on the ratio of the logical estimate value (ie, the minimum entity configuration amount) and the entity estimate value (ie, the actual entity configuration amount), Determine whether the data is concentrated or scattered. And the calculated data scatter degree is compared with a threshold (also called the first threshold) to determine whether to perform data sorting. Here, the first threshold is, for example, preset to 0.75 or other preset thresholds, which is not limited by the present invention.

Specifically, after receiving the instruction from the host system 11 , the memory control circuit unit 404 can determine the number of logical blocks, the logical block capacity, and the rewritable non-volatile memory module 406 according to the logical block address of the data interval included in the instruction. Logical estimate of physical page capacity calculation. In detail, the memory control circuit unit 404 calculates the data capacity of the data interval based on the number of logical blocks and the logical block capacity, and calculates the logical estimation value based on the data capacity and the physical page capacity of the rewritable non-volatile memory module 406 .

Furthermore, the memory control circuit unit 404 determines the physical estimation value according to the number of physical pages in the physical erasure unit mapped by the logical block address, where each logical block address has multiple logical addresses to map entities corresponding to the physical erasure unit. Physical Block Address (PBA).

Next, the memory control circuit unit 404 calculates the ratio of the logical estimate value and the physical estimate value to determine the data scatter degree, and determines whether to perform a data sorting operation to move the physical erase unit according to the logical block address according to the data scatter degree and the first threshold. data in. In detail, the memory control circuit unit 404 can determine whether the data fragmentation is not greater than the first threshold, and when the data fragmentation is not greater than the first threshold, perform a data sorting operation according to the logical block address.

For example, the memory control circuit unit 404 obtains the number of logical blocks corresponding to multiple logical block addresses in the data interval included in the instruction, the capacity of each logical block, and the physical page of the rewritable non-volatile memory module 406 capacity, and calculate the logical estimate based on the following equations (1), (2). Furthermore, the memory control circuit unit 404 obtains the number of physical pages corresponding to the multiple physical erasure units mapped by these logical block addresses, and sets the number of physical pages as the physical estimated value.

Number of logical blocks × logical block capacity = data capacity (1)

Data capacity ÷ entity page capacity = logical estimate (2)

For example, take the memory control circuit unit 404 receiving an instruction whose data interval is a continuous logical row address LCA(0)~LCA(7). The number of logical blocks is 8, the logical page capacity is assumed to be 4K, and the physical page capacity is assumed to be 4K. Assume that it is 16K, and the number of physical pages in the multiple physical erasure units mapped by the logical row addresses LCA(0) to LCA(7) is 3. Accordingly, the calculated logical estimate is 8×4÷16=2, while the physical estimate is 3. It should be noted that the present invention does not limit the logical page capacity and physical page capacity, and the logical page capacity and physical page capacity may vary according to memory storage devices of different specifications. In this embodiment, the memory control circuit unit 404 can calculate that the ratio of the logical estimated value to the physical estimated value is 2/3, that is, the ratio is 0.66. Since the calculated ratio is 0.66 (that is, the data scatter degree), which is less than the first threshold (for example, 0.75 in this embodiment), it means that the data in this data interval is not concentrated enough, so a data sorting operation must be performed.

In another embodiment of the same memory storage device, the number of physical pages corresponding to the multiple physical erasure units mapped by the logical row addresses LCA(0)˜LCA(7) is 2, so the physical estimation value is 2. Accordingly, the memory control circuit unit 404 can calculate that the ratio of the logical estimated value to the physical estimated value is 2/2, that is, the ratio is 1. Since the calculated ratio is 1, which is greater than the first threshold (for example, 0.75 in this embodiment), it represents that the data in this data interval is concentrated, so there is no need to perform data sorting operations.

In the second embodiment, the degree of data scatter is determined by analyzing whether the data is evenly distributed in each channel. That is, whether to reorganize the data is determined by judging whether the number of logical pages corresponding to the data distributed on the plane is even.

Assume that the capacity of a physical page is 16K, and the data interval included in the instruction received by the memory control circuit unit 404 from the host system 11 is a continuous logical row address LCA(0)~LCA(7), a total of eight pieces of 4K data, That is 32K of data. Ideally, 32K of data only needs to be stored in 2 physical pages. In a better state, these two entity pages are distributed on different entity planes, which means that the data on each entity plane is average. In this case, the memory control circuit unit 404 can read data in each physical plane, and the reading efficiency is better. On the contrary, if the two physical pages are distributed on the same physical plane, it means that the data on each physical plane is concentrated. In this case, the reading efficiency of the memory control circuit unit 404 is poor. Based on this, the method provided in this embodiment calculates the number of logical pages and the number of physical planes to determine the degree of data scatter, so as to determine whether the data included in each physical plane is concentrated or average. And the number of pages configured in one of the physical planes corresponding to the physical erasure unit mapped by the logical block address included in the data interval is compared with the second threshold to determine whether to perform data defragmentation. Among them, the number of pages here refers to the number of physical pages. Here, the second threshold is determined by the third threshold and the data scatter degree. The third threshold is, for example, preset to 2 or other preset thresholds, which is not limited by the present invention.

Specifically, after receiving the instruction from the host system 11 , the memory control circuit unit 404 determines the logical estimation value according to the number of logical pages corresponding to the logical block address of the data interval included in the instruction. Furthermore, the memory control circuit unit 404 determines the physical estimation value according to the number of physical planes corresponding to the physical erasure unit mapped by the logical block address. Next, the memory control circuit unit 404 calculates the data scatter degree according to the logical estimate value and the physical estimate value, and calculates the second threshold value according to the data scatter degree and the third threshold value. When the number of pages configured in one of the physical planes corresponding to the physical erase unit mapped by the logical block address is not less than the second threshold, the memory control circuit unit 404 performs a data sorting operation according to the logical block address.

In detail, the memory control circuit unit 404 obtains the number of logical pages corresponding to multiple logical block addresses in the data interval included in the instruction, and sets it as a logical estimated value. Furthermore, the memory control circuit unit 404 obtains the number of physical planes corresponding to the multiple physical erasure units mapped by these logical block addresses, and sets them as physical estimated values. Next, the memory control circuit unit 404 calculates the data scatter degree according to the following equations (3) and (4).

Logical estimate ÷ entity estimate = A (3)

Logical estimate % entity estimate = B (4)

The calculated A is set as the data scatter degree, which represents the minimum number of pages configured in an entity plane under ideal data average conditions. The calculated A+B represents the optimal maximum number of pages for each entity plane. The least ideal situation is that each logical page configuration is concentrated on the same entity plane. In this embodiment, a third threshold is preset as the allowable threshold for the number of pages configured in each entity plane, and the second threshold is determined based on the third threshold and the degree of data scatter.

For example, the number of logical pages corresponding to the multiple logical block addresses included in the data interval received by the memory control circuit unit 404 is 17, and the entities corresponding to the multiple physical erasure units mapped by these logical block addresses are The number of planes is 4 as an example. That is, in this embodiment, the logical estimated value is 17, and the physical estimated value is 4. The memory control circuit unit 404 may calculate A=4 according to equation (3), and calculate the second threshold value as A+the third threshold value (for example, 2 in this embodiment)=6. If the memory control circuit unit 404 determines that the number of pages configured in the physical plane corresponding to the physical erasure unit mapped by the logical block address included in the data interval is not less than 6 (ie, the second threshold), it means that the data is too concentrated in some physical plane, the memory control circuit unit 404 performs a data sorting operation according to the logical block address. On the contrary, if the memory control circuit unit 404 determines that the number of pages configured in the physical plane corresponding to the physical erasure unit mapped by the logical block address included in the data interval is less than 6 (ie, the second threshold), it means that the data is evenly dispersed in each physical plane, the memory control circuit unit 404 does not perform data sorting operations.

In the third embodiment, the memory control circuit unit 404 may simultaneously use the methods of the first embodiment and the second embodiment to determine whether to reorganize data. The methods of the first embodiment and the second embodiment are described in detail as above, and will not be described again here.

FIG. 8 is a flow chart of a memory data organizing method according to an exemplary embodiment of the present invention. Referring to FIG. 8, in step S802, an instruction is received from the host system, where the instruction includes a first data interval. In step S804, the data scatter degree is calculated based on the logical estimation values of the plurality of logical block addresses in the first data interval and the physical estimation values of the plurality of physical erasure units mapped by the logical block address. In step S806, it is determined whether to perform a data sorting operation to move the data in the physical erasure unit according to the logical block address according to the data fragmentation degree and the threshold value.

FIG. 9 is a flowchart of a data organizing method in a memory according to an exemplary embodiment of the present invention. Referring to FIG. 9, in step S902, an instruction is received from the host system, where the instruction includes a first data interval. In step S904, a logical estimate is calculated based on the number of logical blocks of the logical block address of the first data interval, the logical block capacity, and the physical page capacity of the rewritable non-volatile memory module. In step S906, the physical estimation value is determined according to the number of physical pages in the physical erasure unit mapped by the logical block address. In step S908, the ratio of the logical estimate value and the entity estimate value is calculated to determine the data scatter degree. In step S910, it is determined whether the data scatter degree is not greater than a first threshold. If the data fragmentation is not greater than the first threshold (step S910, the determination is yes), then in step S912, a data sorting operation is performed according to the logical block address. If the data scatter is greater than the first threshold (step S910, judged as No), then return to step S902 to wait for receiving instructions.

FIG. 10 is a flow chart of a memory data organizing method according to an exemplary embodiment of the present invention. In step S1002, an instruction is received from the host system, where the instruction includes a first data interval. In step S1004, the logical estimation value is determined according to the number of logical pages corresponding to the logical block address of the first data interval. In step S1006, the physical estimation value is determined according to the number of physical planes corresponding to the physical erasure unit mapped by the logical block address. In step S1008, the data scatter degree is calculated based on the logical estimation value and the entity estimation value. In step S1010, the second threshold is calculated based on the data scatter degree and the third threshold. In step S1012, it is determined whether the number of pages configured in one of the physical planes corresponding to the physical erasure unit mapped by the logical block address is not less than a second threshold. If the number of pages is not less than the second threshold (step S1012, the determination is yes), then in step S1014, a data sorting operation is performed according to the logical block address. If the number of pages is less than the second threshold (step S1012, determination is No), then return to step S1002 to wait for receiving instructions.

It is worth noting that each step in Figures 8 to 10 can be implemented as multiple codes or circuits, and the present invention is not limited thereto. In addition, the methods in Figures 8 to 10 can be used in conjunction with the above exemplary embodiments or can be used alone, and are not limited by the present invention.

To sum up, the memory data sorting method, memory storage device and memory control circuit unit provided by the embodiments of the present invention can be based on the logical estimation values and logical blocks of multiple logical block addresses in the data interval included in the instruction. The entity estimation value of multiple entity erasure units of address mapping calculates the data scatter degree, and compares the data scatter degree with the threshold value to determine whether the data is concentrated or scattered. In this way, it can be determined whether this data interval requires data sorting operation, and thereby improve the speed of reading data.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, but not to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention. scope.

Claims (18)

1. A method of data sort of a memory for a memory storage device comprising a rewritable non-volatile memory module, the method comprising:

Receiving an instruction from a host system, wherein the instruction includes a data interval;

calculating data scattering degree according to the logic estimated values of a plurality of logic block addresses of the data interval and the entity estimated values of a plurality of entity erasure units mapped by the plurality of logic block addresses, wherein the data scattering degree is the ratio of the logic estimated values to the entity estimated values; and

judging whether to execute data sorting operation according to the data disorder degree and the threshold value to move the data in the entity erasing units according to the logic block addresses, wherein the data interval is the range of the host system to execute the data sorting operation,

wherein the step of calculating the data scrambling degree according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses comprises:

calculating the logic estimation value according to the number of the plurality of logic block addresses of the data interval, the capacity of the plurality of logic block addresses and the physical page capacity of the rewritable nonvolatile memory module;

Determining the entity estimation value according to the entity page quantity in the entity erasing units mapped by the logic block addresses; and

calculating the ratio of the logic estimation value to the entity estimation value to determine the data divergence.

2. The data sort method of the memory according to claim 1, wherein the instruction includes a defragmentation instruction.

3. The data sort method of the memory according to claim 1, wherein the step of calculating the logical evaluation value from the number of the plurality of logical block addresses of the data section, the capacity of the plurality of logical block addresses, and the physical page capacity of the rewritable nonvolatile memory module includes:

calculating a data capacity of the data interval according to the number of the plurality of logical block addresses and the capacities of the plurality of logical block addresses; and

the logical estimate is calculated from the data capacity and the physical page capacity of the rewritable non-volatile memory module.

4. The method of claim 1, wherein determining whether to perform the data sort operation to move the data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

And executing the data sorting operation according to the plurality of logic block addresses when the data divergence is not greater than a first threshold.

5. A method of data sort of a memory for a memory storage device comprising a rewritable non-volatile memory module, the method comprising:

receiving an instruction from a host system, wherein the instruction includes a data interval;

calculating data scattering degree according to the logic estimated values of a plurality of logic block addresses of the data interval and the entity estimated values of a plurality of entity erasure units mapped by the plurality of logic block addresses, wherein the data scattering degree is the ratio of the logic estimated values to the entity estimated values; and

judging whether to execute data sorting operation according to the data disorder degree and the threshold value to move the data in the entity erasing units according to the logic block addresses, wherein the data interval is the range of the host system to execute the data sorting operation,

wherein the step of calculating the data scrambling degree according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses comprises:

Determining the logic estimation value according to the number of the logic pages corresponding to the plurality of logic block addresses in the data interval;

determining the entity estimation value according to the number of entity planes corresponding to the entity erasure units mapped by the logic block addresses; and

and calculating the data divergence according to the logic estimation value and the entity estimation value.

6. The method of claim 5, wherein determining whether to perform the data sort operation to move the data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

calculating a second threshold according to the data divergence and a third threshold; and

and executing the data sorting operation according to the plurality of logical block addresses when the number of pages configured in one entity plane corresponding to the plurality of entity erasing units mapped by the plurality of logical block addresses is not smaller than the second threshold value.

7. A memory storage device, comprising:

the connection interface unit is used for being coupled to the host system;

a rewritable nonvolatile memory module; and

A memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is to receive an instruction from the host system, wherein the instruction includes a data interval;

the memory control circuit unit is further configured to calculate a data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses, wherein the data divergence is a ratio of the logical estimation values to the physical estimation values, and

the memory control circuit unit is further configured to determine whether to perform a data sort operation according to the data scattering degree and a threshold value, so as to move data in the plurality of physical erase units according to the plurality of logical block addresses, wherein the data interval is a range in which the host system is to perform the data sort operation,

the operation of the memory control circuit unit further for calculating the data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses comprises:

Calculating the logic estimation value according to the number of the plurality of logic block addresses of the data interval, the capacity of the plurality of logic block addresses and the physical page capacity of the rewritable nonvolatile memory module;

determining the entity estimation value according to the entity page quantity in the entity erasing units mapped by the logic block addresses; and

calculating the ratio of the logic estimation value to the entity estimation value to determine the data divergence.

8. The memory storage device of claim 7, wherein the instructions comprise a defragmentation instruction.

9. The memory storage device of claim 7, wherein calculating the logical estimate from the number of the plurality of logical block addresses, the capacity of the plurality of logical block addresses, and the physical page capacity of the rewritable non-volatile memory module of the data interval comprises:

calculating a data capacity of the data interval according to the number of the plurality of logical block addresses and the capacities of the plurality of logical block addresses; and

the logical estimate is calculated from the data capacity and the physical page capacity of the rewritable non-volatile memory module.

10. The memory storage device of claim 7, wherein the memory control circuit unit further to determine whether to perform the data sort operation to move data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

and executing the data sorting operation according to the plurality of logic block addresses when the data divergence is not greater than a first threshold.

11. A memory storage device, comprising:

the connection interface unit is used for being coupled to the host system;

a rewritable nonvolatile memory module; and

a memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is configured to receive an instruction from the host system, wherein the instruction comprises a data interval,

the memory control circuit unit is further configured to calculate a data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses, wherein the data divergence is a ratio of the logical estimation values to the physical estimation values, and

The memory control circuit unit is further configured to determine whether to perform a data sort operation according to the data scattering degree and a threshold value, so as to move data in the plurality of physical erase units according to the plurality of logical block addresses, wherein the data interval is a range in which the host system is to perform the data sort operation,

the operation of the memory control circuit unit further for calculating the data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses comprises:

determining the logic estimation value according to the number of the logic pages corresponding to the plurality of logic block addresses in the data interval;

determining the entity estimation value according to the number of entity planes corresponding to the entity erasure units mapped by the logic block addresses; and

and calculating the data divergence according to the logic estimation value and the entity estimation value.

12. The memory storage device of claim 11, wherein the memory control circuit unit further to determine whether to perform the data sort operation to move data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

Calculating a second threshold according to the data divergence and a third threshold; and

and executing the data sorting operation according to the plurality of logical block addresses when the number of pages configured in one entity plane corresponding to the plurality of entity erasing units mapped by the plurality of logical block addresses is not smaller than the second threshold value.

13. A memory control circuit unit for controlling a memory storage device including a rewritable nonvolatile memory module, and comprising:

a host interface for coupling to a host system;

a memory interface for coupling to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory control circuit unit is to receive an instruction from the host system, wherein the instruction includes a data interval;

the memory control circuit unit is further configured to calculate a data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses, wherein the data divergence is a ratio of the logical estimation values to the physical estimation values, and

The memory control circuit unit is further configured to determine whether to perform a data sort operation according to the data scattering degree and a threshold value, so as to move data in the plurality of physical erase units according to the plurality of logical block addresses, wherein the data interval is a range in which the host system is to perform the data sort operation,

the operation of the memory control circuit unit further for calculating the data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses comprises:

calculating the logic estimation value according to the number of the plurality of logic block addresses of the data interval, the capacity of the plurality of logic block addresses and the physical page capacity of the rewritable nonvolatile memory module;

determining the entity estimation value according to the entity page quantity in the entity erasing units mapped by the logic block addresses; and

calculating the ratio of the logic estimation value to the entity estimation value to determine the data divergence.

14. The memory control circuit unit of claim 13, wherein the instruction comprises a defragmentation instruction.

15. The memory control circuit unit of claim 13, wherein calculating the logical estimate from the number of the plurality of logical block addresses, the capacity of the plurality of logical block addresses, and the physical page capacity of the rewritable non-volatile memory module of the data interval comprises:

calculating a data capacity of the data interval according to the number of the plurality of logical block addresses and the capacities of the plurality of logical block addresses; and

the logical estimate is calculated from the data capacity and the physical page capacity of the rewritable non-volatile memory module.

16. The memory control circuit unit of claim 13, wherein the memory control circuit unit further configured to determine whether to perform the data sort operation to move data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

and executing the data sorting operation according to the plurality of logic block addresses when the data divergence is not greater than a first threshold.

17. A memory control circuit unit for controlling a memory storage device including a rewritable nonvolatile memory module, and comprising:

A host interface for coupling to a host system;

a memory interface for coupling to the rewritable non-volatile memory module; and

a memory management circuit coupled to the host interface and the memory interface,

wherein the memory control circuit unit is to receive an instruction from the host system, wherein the instruction includes a data interval;

the memory control circuit unit is further configured to calculate a data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses, wherein the data divergence is a ratio of the logical estimation values to the physical estimation values, and

the memory control circuit unit is further configured to determine whether to perform a data sort operation according to the data scattering degree and a threshold value, so as to move data in the plurality of physical erase units according to the plurality of logical block addresses, wherein the data interval is a range in which the host system is to perform the data sort operation,

the operation of the memory control circuit unit further for calculating the data divergence according to the logical estimation values of the plurality of logical block addresses of the data interval and the physical estimation values of the plurality of physical erasure units mapped by the plurality of logical block addresses comprises:

Determining the logic estimation value according to the number of the logic pages corresponding to the plurality of logic block addresses in the data interval;

determining the entity estimation value according to the number of entity planes corresponding to the entity erasure units mapped by the logic block addresses; and

and calculating the data divergence according to the logic estimation value and the entity estimation value.

18. The memory control circuit unit of claim 17, wherein the memory control circuit unit further configured to determine whether to perform the data sort operation to move data in the plurality of physical erase units according to the plurality of logical block addresses based on the data divergence and the threshold comprises:

calculating a second threshold according to the data divergence and a third threshold; and

and executing the data sorting operation according to the plurality of logical block addresses when the number of pages configured in one entity plane corresponding to the plurality of entity erasing units mapped by the plurality of logical block addresses is not smaller than the second threshold value.