CN113300710B - A conversion circuit and digital-to-analog converter based on resistive voltage division and voltage interpolation - Google Patents

Abstract

The invention provides a conversion circuit and a digital-to-analog converter based on resistor voltage division and voltage interpolation, and relates to the technical field of integrated circuits. The circuit comprises: the resistor voltage dividing unit receives the reference voltage, the row selection signal and the column selection signal and outputs top voltage and bottom voltage to the voltage interpolation unit; the voltage interpolation unit receives the top voltage and the bottom voltage and outputs a result voltage. The resistor voltage dividing unit includes: the state of the switches is controlled by a row selection signal and a column selection signal, and the number of the unit resistors is determined by the number of coarse conversion bits; the voltage interpolation unit includes: the number of the PMOS transistors is determined by the number of the fine conversion bits. The conversion circuit of the invention greatly reduces the number of unit resistors and the number of switches, reduces the physical area occupied by the unit resistors and the switches, reduces the complexity of control logic and has higher practical value on the basis of ensuring high-precision conversion and good monotonicity of the digital-analog converter.

Description

A conversion circuit and digital-to-analog converter based on resistor voltage division and voltage interpolation

Technical field

The present invention relates to the technical field of integrated circuits, and in particular to a conversion circuit and a digital-to-analog converter based on resistor voltage division and voltage interpolation.

Background technique

Currently, digital-to-analog converters that implement high-precision digital-to-analog conversion functions based on resistor voltage-dividing structures require a large number of unit resistors and a large number of switches, which not only results in a larger physical area of the entire digital-to-analog converter, but also reduces the control logic More complex.

For example: Taking a 16-bit Digital to Analog Convertor (DAC) as an example, if a resistor-divided X-Y Selection structure is used, a large number of switches and resistors are required. A total of 65,792 switches and 65,536 unit resistance. Such a number of unit resistors and switches will inevitably occupy a large physical area. In addition, the control logic based on 65,792 switches is also relatively complex. Therefore, how to reduce the number of unit resistors and switches on the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter to reduce the physical area occupied and reduce the complexity of the control logic is an urgent problem that needs to be solved.

Contents of the invention

The present invention provides a conversion circuit and a digital-to-analog converter based on resistor voltage division and voltage interpolation, and proposes a technology that not only ensures high-precision conversion and good monotonicity of the digital-to-analog converter, but also reduces the number of unit resistors and switches. plan.

A first aspect of the embodiment of the present invention provides a conversion circuit based on resistor voltage division and voltage interpolation. The conversion circuit is used to convert digital quantities into corresponding analog quantities. The conversion circuit includes: a resistor voltage dividing unit and a voltage interpolation unit. unit;

The resistor voltage dividing unit receives a reference voltage, a row selection signal and a column selection signal, and outputs a top voltage and a bottom voltage to the voltage interpolation unit;

The voltage interpolation unit receives the top voltage, the bottom voltage and the converted digital code, and outputs a result voltage, where the result voltage represents the analog quantity corresponding to the digital quantity;

Wherein, the resistor voltage dividing unit includes: a plurality of unit resistors and a plurality of switches, the states of the plurality of switches are controlled by the row selection signal and the column selection signal, and the number of the plurality of unit resistors is determined by Determined by the number of coarse conversion digits;

The top voltage and the bottom voltage represent the result of the coarse conversion;

The voltage interpolation unit includes: a plurality of PMOS transistors, and the number of the plurality of PMOS transistors is determined by the number of fine conversion bits.

Optionally, the plurality of switches include: row control switches;

The plurality of unit resistors are connected in series and connected in a snake shape between the reference voltage and the ground potential;

The number of rows and columns formed by the plurality of unit resistors connected in series in a serpentine shape is determined by the number of bits of the rough conversion, and each row is provided with a row control switch;

Two ends of each unit resistor in the plurality of unit resistors are each connected to a switch. One end of the first switch among the two switches is connected to the first end of the unit resistor, and the other end is connected to the row control of the row where the unit resistor is located. The first end of the switch is connected, and the second end of the row control switch outputs the top voltage to the voltage interpolation unit;

One end of the second switch among the two switches is connected to the second end of the unit resistor, the other end is connected to the third end of the row control switch in the row where the unit resistor is located, and the fourth end of the row control switch outputs the bottom voltage to the voltage interpolation unit.

Optionally, the high-digit digital code in the coarse conversion bits generates the row selection signal;

The low-digit digital code in the rough conversion bits generates the column selection signal;

Set the lowest bit in the high-order digital code as a flag bit. When the flag bit is high level, it determines that the row selection signal selects even rows. When the flag bit is low level, it determines that the row selection signal selects odd rows. .

Optionally, the voltage interpolation unit includes: a positive input module, a negative input module, and a folding and output module;

The positive input module includes: the plurality of PMOS transistors and the first PMOS transistor;

The plurality of PMOS tubes are connected in parallel, and their sources are respectively connected to the source of the first PMOS tube and the source of the PMOS tube in the negative input terminal module;

The drains of the plurality of PMOS transistors are connected to the source of the third NMOS transistor M12 in the folding and output module;

The gate of each PMOS tube in the plurality of PMOS tubes is connected to two gate switches, one gate switch receives the top voltage, and the other gate switch receives the bottom voltage;

The gate of the first PMOS transistor receives the bottom voltage.

Optionally, the negative input module includes: a third PMOS transistor;

The source of the third PMOS transistor is connected to the sources of the plurality of PMOS transistors respectively;

The gate of the third PMOS transistor is connected to the drain of the sixth PMOS transistor in the folding and output module;

The drain of the third PMOS transistor is connected to the source of the second NMOS transistor in the folding and output module.

Optionally, the folding and output module includes: a second PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a first NMOS transistor. tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first resistor, a second resistor, a first capacitor, and a second capacitor;

The source of the second PMOS tube receives the power supply voltage;

The gate of the second PMOS tube receives a bias voltage;

The drain of the second PMOS transistor is connected to the source of the third PMOS transistor and the sources of the plurality of PMOS transistors respectively;

The source of the fourth PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor all receive the power supply voltage;

The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, the drain of the seventh PMOS transistor, and the drain of the second NMOS transistor respectively;

The drain of the fourth PMOS transistor is connected to the source of the seventh PMOS transistor;

The drain of the fifth PMOS transistor is connected to the source of the eighth PMOS transistor;

The gate of the sixth PMOS transistor, the drain of the eighth PMOS transistor, the source of the ninth PMOS transistor, the drain of the first NMOS transistor, and the first end of the first resistor are respectively connect;

The drain of the sixth PMOS transistor and the gate of the third PMOS transistor, the second end of the first capacitor, the second end of the second capacitor, and the drain of the sixth NMOS transistor are respectively connect;

The gate of the seventh PMOS transistor and the gate of the eighth PMOS transistor both receive the bias voltage;

The gate of the ninth PMOS tube receives the bias voltage;

The drain of the ninth PMOS transistor, the source of the first NMOS transistor, the drain of the third NMOS transistor, the first end of the second resistor, and the gate of the sixth NMOS transistor are respectively connect;

The gate of the first NMOS transistor receives the bias voltage;

The gate of the second NMOS transistor and the gate of the third NMOS transistor both receive the bias voltage;

The source of the second NMOS transistor is connected to the drain of the third PMOS transistor and the drain of the fourth NMOS transistor respectively;

The source of the third NMOS transistor is connected to the drains of the plurality of PMOS transistors, the drain of the first PMOS transistor and the drain of the fifth NMOS transistor respectively;

The gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor both receive the bias voltage;

The source of the fourth NMOS transistor, the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor are all grounded;

The second end of the first resistor is connected to the first end of the first capacitor;

The second end of the second resistor is connected to the first end of the second capacitor.

Optionally, the width-to-length ratio of the third PMOS tube is determined by the number of bits of the fine conversion.

Optionally, two gate switches connected to the gate of each PMOS tube in the plurality of PMOS tubes are controlled by the digital code in the fine conversion bit number;

For one PMOS tube among the plurality of PMOS tubes: Assume that the PMOS tube corresponds to the lowest digital code among the fine conversion bits;

The first gate switch among the two gate switches connected to the PMOS tube is closed when the lowest digital code among the fine conversion bits is 1. At the same time, the two gate switches connected to the PMOS tube are closed. The second gate switch in is turned off when the lowest digital code among the fine conversion bits is 1, and the PMOS tube receives the top voltage;

The first gate switch among the two gate switches connected to the PMOS tube is turned off when the lowest digital code in the fine conversion bits is 0. At the same time, the two gate switches connected to the PMOS tube The second gate switch in the switch is closed when the lowest digital code among the fine conversion bits is 0, and the PMOS tube receives the bottom voltage.

Optionally, the width-to-length ratio of the plurality of PMOS tubes is determined by the number of bits of the fine conversion;

For one PMOS tube among the plurality of PMOS tubes: assuming that the PMOS tube corresponds to the lowest digital code among the fine conversion bits, the width-to-length ratio of the PMOS tube is 1W/L;

For one PMOS tube among the plurality of PMOS tubes: assuming that the PMOS tube corresponds to the second-lowest number among the fine conversion bits, the width-to-length ratio of the PMOS tube is 2W/L;

For one PMOS tube among the plurality of PMOS tubes: assuming that the PMOS tube corresponds to a digital code that is one bit higher than the next lowest bit in the fine conversion bits, the width-to-length ratio of the PMOS tube is 4W/L.

A second aspect of the embodiments of the present invention provides a digital-to-analog converter. The digital-to-analog converter includes: the conversion circuit described in any one of the first aspects.

The invention provides a conversion circuit based on resistor voltage division and voltage interpolation. The conversion circuit is used to convert digital quantities into corresponding analog quantities; the resistor voltage divider unit receives the reference voltage, row selection signal and column selection signal, and outputs the top voltage and The bottom voltage to voltage interpolation unit, and the top voltage and the bottom voltage represent the results of the rough conversion; the resistor voltage dividing unit specifically includes: multiple unit resistors and multiple switches, the status of the multiple switches is controlled by the row selection signal and For column select signals, the number of multiple unit resistors is determined by the number of coarse conversion bits. That is, in the conversion circuit of the present invention, the number of unit resistors is no longer determined by the number of digits of the entire digital quantity, but by the number of coarse conversion digits. For example: In a 16-bit DAC, 16 bits are currently used to determine the number of unit resistors, so the number of unit resistors is 2 ¹⁶ = 65536. Assuming that the number of coarse conversion bits is 10, the number of unit resistors is only 2 ¹⁰ =1024. This undoubtedly greatly reduces the number of unit resistors, and the number of switches is determined by the unit resistor. The smaller the number of unit resistors, the fewer the number of switches. This undoubtedly greatly reduces the physical space occupied by unit resistors and switches. area, and due to the reduction in the number of switches, the natural control logic becomes simpler.

Since coarse conversion only converts part of the number of bits, the remaining number of bits is converted by fine conversion. Specifically, the fine conversion function is implemented by the voltage interpolation unit. The voltage difference unit receives the top voltage and the bottom voltage and outputs the result voltage, which represents the analog quantity corresponding to the digital quantity; the voltage interpolation unit includes: multiple PMOS tubes, the number of multiple PMOS tubes is determined by the number of fine conversion bits. That is, there are as many PMOS tubes as there are number of fine conversion bits. For example: in a 16-bit DAC, assuming that the number of coarse conversion bits is 10, then the number of fine conversion bits is 6, then 6 PMOS tubes are needed. Through the above structure, the digital-to-analog conversion function of the digital-to-analog converter is realized. On the basis of ensuring the high-precision conversion and good monotonicity of the digital-to-analog converter, the number of unit resistors and switches is greatly reduced, thereby reducing the physical space occupied by them. area, reducing the control logic complexity, and the conversion circuit of the present invention has high practical value.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present invention more clearly, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative labor.

Figure 1 is a modular schematic diagram of a conversion circuit based on resistor voltage division and voltage interpolation according to an embodiment of the present invention;

Figure 2 is a schematic structural diagram of a preferred resistive voltage dividing unit in the embodiment of the present invention;

Figure 3 is a schematic structural diagram of a preferred voltage interpolation unit in the embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

Referring to Figure 1 , a modular schematic diagram of a conversion circuit based on resistor voltage division and voltage interpolation according to an embodiment of the present invention is shown. The conversion circuit according to the embodiment of the present invention is used to convert digital quantities into corresponding analog quantities, that is, to achieve Digital to analog conversion function. The conversion circuit includes: a resistor voltage dividing unit and a voltage interpolation unit. The resistor voltage dividing unit receives the reference voltage V _REF , the row selection signal and the column selection signal, and outputs the top voltage and the bottom voltage to the voltage interpolation unit. The top voltage and the bottom voltage represent the result of the coarse conversion. The voltage interpolation unit _receives the top voltage, the bottom voltage and the converted digital code, and outputs the result voltage V _out , which represents the analog quantity corresponding to the digital quantity.

Since the resistor voltage dividing unit implements coarse conversion and the voltage interpolation unit implements fine conversion, it is assumed that the number of bits for coarse conversion is Mbit and the number of bits for fine conversion is N bit. The resistor voltage dividing unit includes: multiple unit resistors and multiple switches. The status of the multiple switches is controlled by the row selection signal and the column selection signal. The number of multiple unit resistors is determined by the number of coarse conversion bits. The voltage interpolation unit includes: multiple PMOS transistors, and the number of multiple PMOS transistors is determined by the number of fine conversion bits. Therefore, the resistor voltage dividing unit receives the M bit digital code, and the M bit digital code determines the specific number of unit resistors. At the same time, it also determines the specific values of the row selection signal and column selection signal based on the M bit digital code. The voltage interpolation unit receives the N-bit digital code, and the N-bit digital code determines the specific number of PMOS transistors.

Through the structure of the above conversion circuit, the digital-to-analog conversion function of the digital-to-analog converter is realized. On the basis of ensuring the high-precision conversion and good monotonicity of the digital-to-analog converter, the number of unit resistors and switches is greatly reduced, thereby reducing its It occupies less physical area and reduces the complexity of control logic.

In the following, the conversion circuit of the embodiment of the present invention will be specifically described using a 16-bit DAC as an example. For DACs with other digits, please refer to the structure of the 16-bit DAC, and will not be listed one by one. It is assumed that the number of bits for coarse conversion is 10 bits and the number of bits for fine conversion is 6 bits. Referring to Figure 2, a schematic structural diagram of a preferred resistor voltage dividing unit in an embodiment of the present invention is shown. Figure 2 includes: multiple resistors, multiple switches, a high-order decoder and a low-order decoder.

Since the number of digits for rough conversion is 10, the number of unit resistors is 2 ¹⁰ = 1024. The resistor voltage dividing unit adopts the XY Selection structure. The 1024 unit resistors are distributed on 32 row lines. After they are connected in series, Connect in a serpentine shape between the reference voltage (V _REF in Figure 2) and the ground potential (GND in Figure 2). For simplicity of illustration, Figure 2 exemplarily shows the first row, the second row, the thirty-first row, and the thirty-second row, which are marked as X ₁ , X ₂ , X ₃₁ and X ₃₂ respectively. Each row is equipped with a row selection _switch . In Figure 2, the row selection switch of the _32nd row

The first column, the second column, the thirty-first column and the thirty-second column are also exemplarily shown, respectively identified as Y ₁ , Y ₂ , Y ₃₁ and Y ₃₂ . Among the 1024 unit resistors, both ends of each resistor are connected to a switch. One end of the first switch among the two switches is connected to the first end of the unit resistor, and the other end is connected to the row control switch of the row where the unit resistor is located. The first end is connected, and the second end of the row control switch outputs the top voltage (V _TOP in Figure 2) to the voltage interpolation unit; one end of the second switch of the two switches is connected to the second end of the unit resistor, and the other end is connected to the second end of the unit resistor. The third terminal of the row control switch in the row where the unit resistor is located is connected, and the fourth terminal of the row control switch outputs the bottom voltage (V _BOT in Figure 2) to the voltage interpolation unit.

Specifically, take a unit resistor marked R ₃₂ in Figure 2 as an example. The other unit resistors are connected in the same way as the unit resistor R _32. The row where the unit resistor R ₃₂ is located is row 32 X ₃₂ , and its row selection switch is S _32. . Both ends of the unit resistor R ₃₂ are connected to the switches S ₁ and S ₂ respectively. One end of the first switch S ₁ is connected to one end of the unit resistor R ₃₂ . The other end of the first switch S ₁ is connected to the row selection switch. The first terminal 1 of S ₃₂ is connected, and the second terminal 2 of the row selection switch S ₃₂ is used in conjunction with the first terminal 1 of the row selection switch S _32. Therefore, the second terminal 2 of the row selection switch S ₃₂ can output the top voltage V _TOP to the voltage interpolation unit. One end of the second switch S ₂ is connected to the other end of the unit resistor R _32. The other end of the second switch S ₂ is connected to the third end 3 of the row selection switch S _32. The row selection switch is the fourth end of S ₃₂ . The terminal 4 is used in conjunction with the third terminal 3 of the row selection switch S ₃₂ , so the fourth terminal 4 of the row selection switch S ₃₂ can output the bottom voltage V _BOT to the voltage interpolation unit.

According to the characteristics of the X-Y Selection structure, a 10-bit digital code is required to determine the row selection signal and column selection signal. Set the high-digit digital code in the coarse conversion digits to generate a row selection signal; set the low-digit digital code in the coarse conversion digits to generate a column selection signal; set the lowest bit in the high-digit digital code as a flag bit, when the flag bit is high level It is determined that the row selection signal selects even rows. When this flag is low level, it is determined that the row selection signal selects odd rows.

Specifically, since the rough conversion is 10 bits: D ₁₅ ~ D ₆ , D ₁₀ ~ D ₆ are used as the low bits of the 10 bits, and D ₁₅ ~ D ₁₁ are used as the high bits of the 10 _{bits .} The value is input to the high-order decoder, and the high-order decoder selects a row line based on the value. The values of D ₁₀ ~ D ₆ are input to the low-order decoder, and the low-order decoder selects the column line based on the value. In this way, the row selection signal X and column selection signal Y are given, and the unit resistance is selected, and then the top voltage V _TOP and the bottom voltage V _BOT are uniquely determined, so the following two equations can be obtained:

Therefore, the following formula can be derived:

Since the high-order decoder generates a row selection control signal to select one of the 32 rows, the low-order decoder generates a column selection control signal to select one of the 32 unit resistors in the row. Since the first tap of the odd row and the even row The last tap, determines the first voltage of the row, so the low decoder has to swap the direction chosen by the low decoder depending on whether the high decoder points to an odd or even row, so the design utilizes D ₁₁ as the low decoder The flag bit, if D ₁₁ is high level, it means that the high-order decoder has selected the even-numbered row; if D ₁₁ is low level, it means that the high-order decoder has selected the odd-numbered row.

Through the above-mentioned resistor voltage dividing unit, a 10-bit coarse conversion is realized, producing the results of the coarse conversion: top voltage V _TOP and bottom voltage V _BOT , and then the top voltage V _TOP and bottom voltage V _BOT are output to the voltage interpolation unit.

The voltage interpolation unit in the embodiment of the present invention includes: a positive input module, a negative input module, and a folding and output module; the positive input module includes: a plurality of PMOS tubes and a first PMOS tube; the negative input module includes: a second PMOS tube, third PMOS tube; the folding and output module includes: fourth PMOS tube, fifth PMOS tube, sixth PMOS tube, seventh PMOS tube, eighth PMOS tube, ninth PMOS tube, first NMOS tube, Two NMOS transistors, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first resistor, a second resistor, a first capacitor, and a second capacitor. Referring to FIG. 3 , a schematic structural diagram of a preferred voltage interpolation unit in an embodiment of the present invention is shown. FIG. 3 includes: multiple PMOS transistors, marked by a dotted box 10 in FIG. 3 . The first PMOS transistor M ₁ , the second PMOS transistor M ₂ , the third PMOS transistor M ₃ , the fourth PMOS transistor M ₄ , the fifth PMOS transistor M ₅ , the sixth PMOS transistor M ₆ , the seventh PMOS transistor M ₇ , Eight PMOS tube M ₈ , ninth PMOS tube M ₉ , first NMOS tube M ₁₀ , second NMOS tube M ₁₁ , third NMOS tube M ₁₂ , fourth NMOS tube M ₁₃ , fifth NMOS tube M ₁₄ , sixth NMOS transistor M ₁₅ , first resistor R ₁ , second resistor R ₂ , first capacitor C ₁ , second capacitor C ₂ .

In Figure 3, multiple PMOS tubes are connected in parallel within the dotted box 10, and their sources are connected to the source of the first PMOS tube _M1 and the drain of the second PMOS tube _M2 respectively; the drains of the multiple PMOS tubes are connected to the third The source of the NMOS tube M ₁₂ is connected; the gate of each PMOS tube among the multiple PMOS tubes is connected to two gate switches, receiving the top voltage V _TOP through one gate switch, and receiving the bottom voltage through the other gate switch. voltage V _BOT ; at the same time, the gate of the first PMOS transistor M ₁ receives the bottom voltage V _BOT .

Specifically, since the number of bits for fine conversion is 6, that is: D ₅ ~D ₀ , there should be 6 PMOS transistors in the dotted box 10 . For the simplicity of the illustration, only 3 PMOS are shown as an example. Tube. The gate of each PMOS tube is equipped with two gate switches, and the two gate switches are controlled by the digital code in the fine conversion bits; take the leftmost PMOS tube in the virtual box 10 in Figure 3 as an example: This PMOS The tube corresponds to the digital code of the lowest bit D ₀ in the fine conversion bits; the first gate switch of the two gate switches connected to the PMOS tube, when the digital code of the lowest bit D ₀ in the fine conversion bits is 1 Closed; at the same time, the second gate switch of the two gate switches connected to the PMOS tube is turned off when the lowest digital code D ₀ in the fine conversion bits is 1. At this time, the PMOS tube receives the top voltage V _TOP . In the figure, D ₀ is used to represent the controlled condition of the first gate switch, that is, when D ₀ =1, the first gate switch is closed, and when D ₀ =1, it is not Therefore the second gate switch is turned off.

In the same way, the first gate switch of the two gate switches connected to the PMOS tube is turned off when the digital code of the lowest bit D ₀ in the fine conversion digits is 0. At the same time, the two gate switches connected to the PMOS tube are turned off. The second gate switch among the three gate switches is closed when the digital code of the lowest bit D ₀ among the fine conversion bits is 0, and the PMOS tube receives the bottom voltage V _BOT .

In the embodiment of the present invention, the width-to-length ratio of multiple PMOS tubes is determined by the number of fine conversion bits. Taking the leftmost PMOS tube in the virtual box 10 in Figure 3 as an example: this PMOS tube corresponds to the lowest bit D ₀ in the fine conversion bits. , so its width-to-length ratio is W/L. The PMOS tube next to the PMOS tube on the left corresponds to the second-lowest bit D ₁ in the fine conversion bits, so its width-to-length ratio is 2W/L. By analogy, the dotted box The rightmost PMOS tube in 10 corresponds to the highest bit D ₅ among the fine conversion bits, so its width-to-length ratio is 32W/L.

The above-mentioned dotted box 10 and the first PMOS transistor M ₁ constitute the positive input module. The structure of the third PMOS transistor M ₃ in the negative input module is:

The source of the third PMOS transistor _M3 and the sources of the multiple PMOS transistors in the virtual frame 10 are respectively connected; the gate of the third PMOS transistor _M3 is connected with the drain of the sixth PMOS transistor M6; the third PMOS transistor M6 The drain of ₃ is connected to the source of the second NMOS transistor _M11 . The width-to-length ratio of the third PMOS transistor M ₃ is determined by the number of fine conversion bits. Since the number of fine conversion bits is 6, 2 ⁶ =64, the width-to-length ratio of the third PMOS transistor M ₃ is 64W/L.

The structure of the folding and output module is: the source of the second PMOS transistor _M2 receives the power supply voltage VDD; the gate of the second PMOS transistor _M2 receives the bias voltage _Vb1 ; the drain of the second PMOS transistor _M2 is connected to the third The source of the PMOS transistor _M3 and the sources of the multiple PMOS transistors in the virtual frame 10 are connected respectively; the source of the fourth PMOS transistor _M4 , the source of the fifth PMOS transistor _M5 and the source of the sixth PMOS transistor _M6 The sources all receive the power supply voltage; the gate of the fourth PMOS transistor _M4 is connected to the gate of the fifth PMOS transistor _M5 , the drain of the seventh PMOS transistor _M7 , and the drain of the second NMOS transistor _M11 respectively; The drain of the fourth PMOS transistor _M4 is connected to the source of the seventh PMOS transistor _M7 ; the drain of the fifth PMOS transistor _M5 is connected to the source of the eighth PMOS transistor _M8 ; the gate of the sixth PMOS transistor _M6 The drain of the eighth PMOS transistor M ₈ , the source of the ninth PMOS transistor M ₉ , the drain of the first NMOS transistor M ₁₀ and the first end of the first resistor R ₁ are respectively connected.

The drain of the sixth PMOS transistor M ₆ and the gate of the third PMOS transistor M ₃ , the second terminal of the first capacitor C ₁ , the second terminal of the second capacitor C ₂ and the drain of the sixth NMOS transistor M ₁₅ are respectively connection; the gate of the seventh PMOS transistor M ₇ and the gate of the eighth PMOS transistor M ₈ both receive the bias voltage V _b2 ; the gate of the ninth PMOS transistor M ₉ receives the bias voltage V _bp ; the ninth PMOS transistor M The drain of ₉ is connected to the source of the first NMOS transistor M ₁₀ , the drain of the third NMOS transistor M ₁₂ , the first end of the second resistor R ₂ and the gate of the sixth NMOS transistor M ₁₅ respectively; the first NMOS The gate of the tube M ₁₀ receives the bias voltage V _bn ; the gate of the second NMOS tube M ₁₁ and the gate of the third NMOS tube M ₁₂ both receive the bias voltage V _b3 ; the source of the second NMOS tube M ₁₁ and The drain of the third PMOS transistor M ₃ and the drain of the fourth NMOS transistor M ₁₃ are respectively connected.

The source of the third NMOS transistor M ₁₂ is connected to the drains of the plurality of PMOS transistors in the virtual frame 10 , the drain of the first PMOS transistor M ₁ and the drain of the fifth NMOS transistor M ₁₄ respectively; the fourth NMOS transistor M ₁₃ The gate of the fourth NMOS transistor M ₁₄ and the gate of the fifth NMOS transistor M 14 both receive the bias voltage V _b4 ; the source of the fourth NMOS transistor M ₁₃ , the source of the fifth NMOS transistor M ₁₄ and the source of the sixth NMOS transistor M ₁₅ Both are grounded GND; the second end of the first resistor R ₁ is connected to the first end of the first capacitor C ₁ ; the second end of the second resistor R ₂ is connected to the first end of the second capacitor C ₂ . The second terminal of the first capacitor C ₁ , the second terminal of the second capacitor C ₂ , the drain of the sixth PMOS transistor M ₆ and the drain of the sixth NMOS transistor M ₁₅ are connected together to output the resulting voltage V _out .

According to the principle that the value of the current I _p in the positive input module should be equal to the value of the current _In in the negative input module, the following formula can be obtained:

in, μ _p is the carrier mobility, Cox is the gate oxide capacitance per unit area, V _THP is the threshold voltage of the PMOS tube, V _pi (i=1, 2, 3, 4, 5, 6) is the threshold voltage of multiple pmos tubes gate terminal voltage.

From this we can get the following formula:

Simplified into the following formula:

V _BoT +V _p1 +2*V _p2 +…32*V _p6 =64*V _out

Among them, g _m =2*k*(V _x -V _BOT -|V _THP |).

The following formula is derived from this:

This completes the function of fine conversion, that is, based on the joint action of the resistor voltage dividing unit and voltage interpolation unit shown in Figure 2 and Figure 3 above, taking 10-bit coarse conversion and 6-bit fine conversion as an example, a 16-bit DAC is implemented digital-to-analog conversion.

To sum up, in the conversion circuit of the embodiment of the present invention, the resistor voltage dividing unit receives the reference voltage and generates the row selection signal and the column selection signal based on the digital code of the coarse conversion bits, and outputs the top voltage and column selection signal that represent the coarse conversion result. From the bottom voltage to the voltage interpolation unit, since the coarse conversion only converts part of the number of bits, the remaining number of bits are finely converted by the voltage interpolation unit. The voltage difference unit receives the top voltage and the bottom voltage, uses the positive input module, the negative input module, and the folding and output module to achieve fine conversion, and outputs the resulting voltage representing the analog quantity corresponding to the digital quantity.

Through the above structure, the number of unit resistors is no longer determined by the number of digits of the entire digital quantity, but by the number of coarse conversion digits. It greatly reduces the number of unit resistors, and the number of switches is determined by the unit resistor. The smaller the number of unit resistors, the fewer the number of switches. This undoubtedly greatly reduces the physical area occupied by the unit resistors and switches. And due to the reduction in the number of switches, the natural control logic becomes simpler. On the basis of ensuring high-precision conversion and good monotonicity of the digital-to-analog converter, it greatly reduces the number of unit resistors and switches, thereby reducing the physical area it occupies and reducing the complexity of the control logic. The conversion circuit of the present invention has High practical value.

Based on the above conversion circuit, an embodiment of the present invention further provides a digital-to-analog converter, where the digital-to-analog converter includes: any one of the above conversion circuits.

It should be noted that, in this document, the terms "comprising", "comprises" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements, It also includes other elements not expressly listed or inherent in the process, method, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.

The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art will Under the inspiration of the present invention, many forms can be made without departing from the spirit of the present invention and the scope protected by the claims, and these all fall within the protection of the present invention.

Claims (8)

1. A conversion circuit based on resistor voltage division and voltage interpolation, characterized in that the conversion circuit is used to convert digital quantities into corresponding analog quantities; the conversion circuit includes: a resistor voltage dividing unit and a voltage interpolation unit; The resistor voltage dividing unit receives a reference voltage, a row selection signal and a column selection signal, and outputs a top voltage and a bottom voltage to the voltage interpolation unit; The voltage interpolation unit receives the top voltage, the bottom voltage and the digital code with fine conversion digits, and outputs a result voltage, where the result voltage represents the analog quantity corresponding to the digital quantity; Wherein, the resistor voltage dividing unit is used to implement coarse conversion, which includes: multiple unit resistors and multiple switches, the states of the multiple switches are controlled by the row selection signal and the column selection signal, the The number of multiple unit resistors is determined by the number of coarse conversion bits; The top voltage and the bottom voltage represent the result of the coarse conversion; The voltage interpolation unit is used to implement fine conversion, which includes: a plurality of PMOS transistors, the number of the plurality of PMOS transistors is determined by the number of fine conversion bits; The plurality of switches include: row control switches; The plurality of unit resistors are connected in series and connected in a snake shape between the reference voltage and the ground potential; The number of rows and columns formed by the plurality of unit resistors connected in series in a serpentine shape is determined by the number of bits of the rough conversion, and each row is provided with a row control switch; Two ends of each unit resistor in the plurality of unit resistors are each connected to a switch. One end of the first switch among the two switches is connected to the first end of the unit resistor, and the other end is connected to the row control of the row where the unit resistor is located. The first end of the switch is connected, and the second end of the row control switch outputs the top voltage to the voltage interpolation unit; One end of the second switch among the two switches is connected to the second end of the unit resistor, the other end is connected to the third end of the row control switch in the row where the unit resistor is located, and the fourth end of the row control switch outputs the the bottom voltage to the voltage interpolation unit; The high-digit digital code in the coarse conversion bits generates the row selection signal; The low-digit digital code in the rough conversion bits generates the column selection signal; Set the lowest bit in the high-order digital code as a flag bit. When the flag bit is high level, it determines that the row selection signal selects even rows. When the flag bit is low level, it determines that the row selection signal selects odd rows. . 2. The conversion circuit according to claim 1, characterized in that the voltage interpolation unit includes: a positive input module, a negative input module and a folding and output module; The positive input module includes: the plurality of PMOS transistors and a first PMOS transistor; The plurality of PMOS tubes are connected in parallel, and their sources are respectively connected to the source of the first PMOS tube and the source of the PMOS tube in the negative input terminal module; The drains of the plurality of PMOS transistors are connected to the source of the third NMOS transistor in the folding and output module; The gate of each PMOS tube in the plurality of PMOS tubes is connected to two gate switches, one gate switch receives the top voltage, and the other gate switch receives the bottom voltage; The gate of the first PMOS transistor receives the bottom voltage. 3. The conversion circuit according to claim 2, characterized in that the negative input module includes: a third PMOS transistor; The source of the third PMOS transistor is connected to the sources of the plurality of PMOS transistors respectively; The gate of the third PMOS transistor is connected to the drain of the sixth PMOS transistor in the folding and output module; The drain of the third PMOS transistor is connected to the source of the second NMOS transistor in the folding and output module. 4. The conversion circuit according to claim 3, wherein the folding and output module includes: a second PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, Eight PMOS tubes, ninth PMOS tubes, first NMOS tube, second NMOS tube, third NMOS tube, fourth NMOS tube, fifth NMOS tube, sixth NMOS tube, first resistor, second resistor, first capacitor , the second capacitor; The source of the second PMOS tube receives the power supply voltage; The gate of the second PMOS tube receives a bias voltage; The drain of the second PMOS transistor is connected to the source of the third PMOS transistor and the sources of the plurality of PMOS transistors respectively; The source of the fourth PMOS transistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor all receive the power supply voltage; The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, the drain of the seventh PMOS transistor, and the drain of the second NMOS transistor respectively; The drain of the fourth PMOS transistor is connected to the source of the seventh PMOS transistor; The drain of the fifth PMOS transistor is connected to the source of the eighth PMOS transistor; The gate of the sixth PMOS transistor, the drain of the eighth PMOS transistor, the source of the ninth PMOS transistor, the drain of the first NMOS transistor, and the first end of the first resistor are respectively connect; The drain of the sixth PMOS transistor and the gate of the third PMOS transistor, the second end of the first capacitor, the second end of the second capacitor, and the drain of the sixth NMOS transistor are respectively connect; The gate of the seventh PMOS transistor and the gate of the eighth PMOS transistor both receive the bias voltage; The gate of the ninth PMOS tube receives the bias voltage; The drain of the ninth PMOS transistor, the source of the first NMOS transistor, the drain of the third NMOS transistor, the first end of the second resistor, and the gate of the sixth NMOS transistor are respectively connect; The gate of the first NMOS transistor receives the bias voltage; The gate of the second NMOS transistor and the gate of the third NMOS transistor both receive the bias voltage; The source of the second NMOS transistor is connected to the drain of the third PMOS transistor and the drain of the fourth NMOS transistor respectively; The source of the third NMOS transistor is connected to the drains of the plurality of PMOS transistors, the drain of the first PMOS transistor and the drain of the fifth NMOS transistor respectively; The gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor both receive the bias voltage; The source of the fourth NMOS transistor, the source of the fifth NMOS transistor, and the source of the sixth NMOS transistor are all grounded; The second end of the first resistor is connected to the first end of the first capacitor; The second end of the second resistor is connected to the first end of the second capacitor. 5. The conversion circuit according to claim 3, wherein the width-to-length ratio of the third PMOS transistor is determined by the number of bits of the fine conversion. 6. The conversion circuit according to claim 2, characterized in that two gate switches connected to the gate of each PMOS transistor in the plurality of PMOS transistors are controlled by the digital code of the fine conversion digits. ; For any PMOS tube among the plurality of PMOS tubes: the first gate switch among the two gate switches connected to the PMOS tube has a digital code of 1 conversion digit to control its closing or opening. When closed, at the same time, the second gate switch of the two gate switches connected to the PMOS tube is opened when the digital code of the fine conversion digit that controls its closing or opening is 1, and the PMOS tube receives all the The top voltage; The first gate switch among the two gate switches connected to the PMOS tube is turned off when the digital code of the fine conversion digit that controls its closing or opening is 0. At the same time, the two gate switches connected to the PMOS tube are turned off. The second gate switch in the gate switch is closed when the digital code of the fine conversion digit that controls its closing or opening is 0, and the PMOS tube receives the bottom voltage. 7. The conversion circuit according to claim 2, characterized in that the width-to-length ratio of the plurality of PMOS tubes is determined by the number of bits of the fine conversion; For one PMOS tube among the plurality of PMOS tubes: assuming that the PMOS tube corresponds to the lowest digital code among the fine conversion bits, the width-to-length ratio of the PMOS tube is 1W/L; For one PMOS tube among the plurality of PMOS tubes: assuming that the PMOS tube corresponds to the second-lowest number among the fine conversion bits, the width-to-length ratio of the PMOS tube is 2W/L; For one PMOS tube among the plurality of PMOS tubes: assuming that the PMOS tube corresponds to a digital code that is one bit higher than the next lowest bit in the fine conversion bits, the width-to-length ratio of the PMOS tube is 4W/L. 8. A digital-to-analog converter, characterized in that the digital-to-analog converter includes: the conversion circuit according to any one of claims 1 to 7.