Initial signal fan-out device of neutron spectrometer
Technical Field
The invention relates to a starting signal fan-out device for a neutron spectrometer, and belongs to the neutron spectrometer data acquisition, test measurement and synchronous timing technology of particle physics experiments.
Background
In a spallation neutron source, protons impact a metal tungsten target at a certain frequency to produce spallation neutrons. The neutron spectrometer performs a neutron experiment by using the neutrons generated by the spallation reaction to act on a sample and using a neutron detector to detect the neutrons after the action.
A neutron spectrometer on a spallation neutron source adopts a neutron flight time technology, and a data acquisition system needs to accurately know the time zero point of each proton pulse target so as to accurately measure the flight time of neutrons. Thus, the signal associated with the targeted proton beam cluster, which is generated by an external neutron monitor, accelerator system, or primary gamma ray detector, is used as a start signal, representing the time at which neutrons are generated from the target.
The start signal has two effects on the data acquisition system. On one hand, the electronic system takes the effective signal of each channel detector as a neutron flight ending time mark, and obtains the neutron flight time of the reaction of the neutron and the substance represented by the detection signal through the measurement of the effective information threshold crossing triggering time point and the leading edge of the starting signal. On the other hand, the start signal is also distributed to each stage of system modules of the electronic system as a global synchronization signal.
The starting signal is distributed to each acquisition channel in an electronic system in a remote laboratory from the fan-out of the ground control station, and the accuracy of the fan-out of the starting signal is ensured while the transmission is carried out through a coaxial cable which is hundreds of meters long. And the number of acquisition channels of an electronic system in the neutron spectrometer is large, so that the synchronization precision of initial signals of the acquisition channels is ensured while the number of fan-out channels is met. Therefore, the reasonably designed starting signal fan-out method is an important guarantee for the neutron flight time measurement accuracy and the electronic system synchronization. In the process of accurately fanning out the starting signal in a long distance, the specific problems to be solved include: long-distance high-precision starting signal fanout and multi-channel synchronous fanout technology.
At present, the starting signal of a spallation neutron source is generally collected at an RTBT (RCS to Target Beam Transfer line) timing station, and fanout of the starting signal is realized by electro-optical conversion and special hardware based on an optical fiber link.
The equipment for fanning out the initial signal of the Chinese spallation neutron source CSNS target station spectrometer is a mother-son board hardware framework, and is combined with a multimode fiber transceiver based on a CPLD chip to realize the initial signal receiving, sending and fanning out. 1 path of I/O of the optical signal collection daughter board is transmitted to the mother board through the PMC connector, and 1 is completed through input, logic fan-out and output of the mother board I/O to 8 paths of I/O of the optical fiber sending daughter board: the start signal of 8 fans out.
The spallation neutron source SNS of OPNL uses a fiber fan-out Module (Optical Distribution Module) to accomplish the fanout of the initiation signal, the hardware of which is based on FPGA chips and fiber transceivers, again relying on FPGA hardware logic to accomplish 1: the start signal of 8 fans out.
Such dedicated hardware fan-out channels based on fiber optic links are low in number and, for electronics systems with a high number of channels, require a large number of cables and fiber transceivers and are not easy to install and maintain. Meanwhile, in order to ensure the synchronization of the initial signals, the lengths of the optical fibers of all the channels need to be manually calibrated in advance, so that the lengths are ensured to be equal, and the workload is undoubtedly and greatly increased.
Disclosure of Invention
The invention solves the problems: the device overcomes the defects of the prior art, and provides a starting signal fan-out device for a neutron spectrometer, wherein a two-stage accurate fan-out method combining simulation and digital is used for finishing accurate global synchronous fan-out from a starting signal to an electronic system. The method has the advantages of multi-channel fan-out, high timing precision, high synchronization precision and the like, so that an electronic system can finish accurate measurement on the output signal of the detector, and accurate time information and energy information of interaction nuclear reaction of neutrons and substance atomic nuclei are obtained.
The technical scheme of the invention is as follows: a neutron spectrometer initiation signal fanout apparatus, comprising: a starting signal fan-out module, an electronics system; in a control station, a starting signal fan-out module carries out multi-path fan-out on a starting signal, and the starting signal is transmitted to a remote electronic system through a long-distance cable after being driven and processed by a first-stage long distance; in an electronic system, the signal receiving and digitizing node further carries out synchronous coding processing on the initial signal, and fans out the digital coding of the initial signal to each acquisition node of the electronic system to complete second-stage fan-out; the long distance is greater than or equal to 100 m.
The start signal fan-out module includes: the device comprises a supersaturation amplifying part, a threshold crossing screening part, a multi-path fan-out part and a long-distance driving part; the oversaturated amplifying part is used for oversaturating and amplifying the initial signal, so that the rising edge of the amplified initial signal is irrelevant to the amplitude change of an input signal and almost keeps unchanged, and then the threshold crossing part is used for carrying out front edge timing on an output signal of the oversaturated amplifying part by adopting a threshold crossing screening method, so that time information carried by the initial signal is accurately reserved, and the front edge of a timing signal swinging by less than 50ps can be obtained; after the starting signal is timed, the multi-path fan-out part carries out multi-path synchronous fan-out on the starting signal through a clock fan-out driver; the long-distance driving parts respectively drive multiple paths of starting signals to be transmitted to an electronic system through cables with the length of more than 100 m.
And aiming at the initial signals with different polarities, performing reverse amplification on the initial signals, and performing front edge timing processing by adopting a threshold crossing screening part.
The long-distance driving part is implemented as follows: the method adopts a high-precision timing lengthened distance driving method, pre-emphasis processing is carried out on the initial signal by a long-distance driving chip DS15BA101, high-precision leading edge timing is carried out at the tail end by using a high-speed comparator AD8465 with the bandwidth of 500MHz after long-distance transmission, and the leading edge timing precision is less than 50 ps.
The electronic system is composed of a plurality of chassis, the functional plug-in a single chassis comprises a signal receiving and digitizing node and a plurality of acquisition nodes, wherein the signal receiving and digitizing node is used for carrying out digitized coding and distribution of initial signals, overall clock distribution in the chassis and clock synchronization among the multiple chassis, and the acquisition nodes are used for acquiring and uploading the subdata; a star-shaped framework is adopted among a plurality of chassis, a high-speed serial digitization technology is adopted to construct a digital synchronous fan-out network, one of the chassis is used as a main node chassis, and the other chassis are used as slave nodes; the signal receiving and digitizing node in the main node case accesses the initial signal of the first fan-out to the electronic system, and after digital coding, the initial signal coding fan-out is carried out to the signal receiving and digitizing node in other sub-node cases through the high-speed serial transceiver module; the signal receiving and digitizing node in the subnode case adopts high speed serial clock data recovery technology to recover the clock from the data, and decodes the initial signal to generate the initial signal of the subnode case; a signal receiving and digitizing node in a single case fans out an initial signal to each acquisition node in the case through a special signal connecting channel or a special back board bus of the digital case to be used as a measurement starting point of neutron flight time; in order to ensure the synchronism of the initial signal reaching each sub-node case node and give full play to the advantages of the star-shaped architecture, equal-length cables are adopted among a plurality of cases, and the hardware design and the logic design of the signal receiving and digital node of each sub-node case are kept the same, so that the physical transmission delay from the main node case to each sub-node case is kept consistent.
The signal receiving and digitizing nodes are divided into a master signal receiving and digitizing node and a slave signal receiving and digitizing node, and the PCB design of the two signal receiving and digitizing nodes is completely the same, and the difference is only that the working modes determined by FPGA logic are different. The signal receiving and digitizing node comprises: the system comprises a high-speed comparator, an FPGA, a clock fan-out module and a special connecting channel interface. The high-speed comparator is used for receiving a starting signal of the first-stage fan-out, converting an analog signal into a digital signal and inputting the digital signal into the FPGA. The FPGA synchronously encodes the initial signal and sends and receives a clock and the initial signal code through a high-speed serial transceiving module in the FPGA; the clock fan-out module comprises a local crystal oscillator, a PLL (phase locked loop) and a clock fan-out buffer, and fans out a local crystal oscillator clock or a clock recovered by the high-speed serial transceiving module to each acquisition node in the chassis.
The accurate fan-out process of the initial signal by the signal receiving and digitizing node in the mainframe box is as follows: in the main node case, the digital pulse of the initial signal screened by the high-speed comparator is an asynchronous signal relative to an electronic system, synchronous processing is carried out before further coding, and when the asynchronous initial signal is detected, an asynchronous initial signal synchronous module in the FPGA gives out a synchronous initial signal after a fixed period of time t 2; because an uncertain time difference t1 exists between the leading edge of the asynchronous starting signal and the leading edge of the system clock, an uncertain transmission delay t3 exists between the asynchronous starting signal and the synchronous starting signal, and the uncertain delay t2 and the uncertain delay t1 jointly form an asynchronous starting signal time difference t 3; in order to ensure the fan-out precision of the initial signal, the uncertain delay is corrected by adopting a real-time measurement method, a high-precision time measurement conversion circuit is realized by utilizing a carry chain in the FPGA, the phase difference t1 between each asynchronous initial signal and a system clock is measured by utilizing the precision time measurement conversion circuit, and the asynchronous initial signal time difference t3 is obtained, wherein the asynchronous initial signal time difference t3 can be packed and uploaded along with each corresponding initial signal data packet; and when the flight time is measured every time, the corresponding fan-out delay of the starting signal is determined so as to eliminate the delay uncertainty of the starting signal in the fan-out process in the case and finish the accurate fan-out of the starting signal.
Compared with the prior art, the invention has the advantages that:
(1) the method is based on analog signal conditioning and digital signal processing, realizes the multichannel accurate global synchronous fan-out from the initial signal of the neutron spectrometer to an electronic system, and ensures the measurement precision of the neutron flight time and the synchronization of the electronic system;
(2) analog signal pre-emphasis is utilized to realize high timing precision analog fan-out in a long distance, so that a starting signal after fan-out has a very fast signal rising front edge, the signal transmission quality is improved, and the timing precision is improved;
(3) the digital synchronous fan-out network is constructed by utilizing a high-speed serial digitization technology, high-precision synchronous fan-out among multiple channels can be realized based on a special wiring channel and a high-performance backboard resource of a digital case, the integration level of a system is improved, the difficulty of optical fiber length calibration and installation and maintenance is reduced, and the digital synchronous fan-out network has universality and usability.
Drawings
FIG. 1 is a schematic diagram of a structure of a neutron spectrometer initial signal fan-out device according to the present invention;
FIG. 2 is a schematic block diagram of a start signal fan-out module of the present invention;
FIG. 3 is a block diagram of the long distance cable drive concept of the present invention;
FIG. 4 is a schematic block diagram of a signal receiving and digitizing node of the present invention;
fig. 5 shows a method for accurately distributing the start signal in the master node enclosure, where (a) is a logic diagram of the start signal distribution in the master node enclosure, and (b) is a timing chart of the start signal distribution synchronization process in the master node enclosure.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
As shown in fig. 1, to meet the requirement of starting signal fan-out, the present invention adopts a two-stage starting signal long-distance accurate fan-out architecture. The starting signal is distributed from the fan-out of the control station to each acquisition channel in an electronic system in a remote laboratory, and the starting signal is transmitted by a coaxial cable which is nearly 100m long, and the fan-out precision of the starting signal is ensured.
First, the first stage is the starting signal fanout from the control station to a plurality of remote laboratories, the starting signal of the first stage fanout is an analog signal, and the timing precision of the starting signal needs to be ensured while the starting signal fanout and long-distance transmission are completed. The analog signals are distorted in the transmission process of the long cable, the fan-out work of the initial signals is completed in the control station by designing the special fan-out module for the initial signals supporting multi-path fan-out, and the initial signals are driven by adopting a long-distance driving and high-precision timing method to complete long-distance transmission. The initial signal is transmitted to a plurality of experimental halls through long cables respectively and is accessed to a plurality of electronic systems. In addition, a path of initial signal is sent to an acquisition channel of the acquisition node, so that the quality of the initial signal sent by the control station is evaluated in real time, and effective treatment measures are conveniently taken for abnormal conditions in the experimental process.
The second stage of starting signal fan-out is to complete the fan-out work of the multichannel synchronous trigger signals to all the acquisition channels in an electronic system, and the starting signal of the first stage of fan-out is a digital coding signal. An electronic system can be developed based on standard chassis (such as VME, ATCA, PXI, PXIe and the like), the system is composed of a plurality of chassis, a digital synchronous fanout network is constructed among the chassis by adopting a high-speed serial digitization technology, and signal receiving and digitization nodes in each chassis are connected through cables with equal length. The initial signal fan-out between multiple chassis is a star architecture, in which one of the chassis acts as a master chassis and the other chassis acts as a slave. The functional plug-in a single case comprises a signal receiving and digitizing node and a plurality of collecting nodes, wherein the collecting nodes are used for collecting and uploading the subdata, and the signal receiving and digitizing node is used for digitally coding and distributing the initial signal and synchronizing the clocks among the plurality of cases. The starting signal is used as a measuring starting point of neutron flight time, a signal receiving and digitizing node in the main node case is accessed to an electronic system, an analog signal is converted into a digital coding signal, and starting signal fan-out is carried out on the signal receiving and digitizing node in other sub-node cases through a high-speed serial transceiving module. The signal receiving and digitizing nodes in the subnode chassis adopt high-speed serial clock data recovery technology, can recover the clock which is the same as the sending end from the data, and use the clock to decode the initial signal, generate the initial signal which needs fan out in the local chassis. The signal receiving and digitizing nodes within a single chassis fan out the start signal to other electronics cards within the chassis over dedicated signal connection channels (e.g., coaxial cable or differential cable) or dedicated backplane buses of a digital chassis (e.g., DSTAR differential bus of PXIe chassis). In order to ensure the synchronism of the initial signal reaching each subnode chassis and give full play to the advantages of the star-shaped architecture, equal-length cables are adopted, and the hardware design and the logic design of the signal receiving and digitizing nodes of each subnode chassis are kept the same, so that the physical transmission delay from the master chassis node to each slave chassis node is kept consistent.
As shown in fig. 2, a start signal fan-out module for first stage fan-out includes an oversaturation amplifying section, a threshold crossing discriminating section, a multi-fan-out section, and a long distance driving section. The starting signal fan-out module first oversaturates and amplifies the starting signal and then performs leading edge timing on the output signal of the amplifier. Because the amplifier works in a state close to saturation, the leading edge of the output signal is mainly limited by the slew rate parameter of the amplifier and is independent of the amplitude change of the input signal, so that the time information carried by the initial signal can be accurately reserved. Therefore, the rising edge of the initial signal amplified by the amplifier is almost kept unchanged. And then, the front edge timing is carried out by adopting a threshold crossing discrimination method, so that the front edge of a timing signal with timing jitter less than 50ps can be obtained. And aiming at the starting signals with different polarities, performing reverse amplification on the starting signals, and performing fan-out by adopting the same processing such as front edge timing and the like. After the starting signal is timed, the multi-path synchronous fan-out processing is needed, and the multi-path fan-out part drives cables which are longer than 100m respectively through a clock fan-out driver to transmit the starting signal to an electronic system.
The long-distance electric signal transmission process can distort signals, so that timing information is damaged, the timing precision of an electronic system in an experimental hall is poor, and the precision of neutron flight time measurement is influenced finally. In order to solve the problem of long-distance high-precision start signal transmission during the first stage fan-out process, a method of long-distance driving high-precision timing is used, and a schematic block diagram of the method is shown in fig. 3. The method adopts a high-precision timing lengthened distance driving method, pre-emphasis processing is carried out on the initial signal by a long-distance driving chip DS15BA101, and high-precision leading edge timing is carried out at the tail end by using a high-speed comparator AD8465 with a 500MHz bandwidth after long-distance transmission.
The start signal is further fanned out to each electronics channel at the electronics chassis. And the signal receiving and digitizing nodes in the case complete the timing, synchronization and fan-out of the initial signals. The starting signal fan-out device comprises a master signal receiving node, a slave signal receiving node and a digitization node, wherein the PCB design of the two signal receiving nodes and the PCB design of the digitization node are completely the same, and the difference is only that the working modes determined by FPGA logic are different. A functional block diagram of a signal receiving and digitizing node is shown in fig. 4. The high-speed comparator is used for receiving a starting signal of the first-stage fan-out, converting an analog signal into a digital signal and inputting the digital signal into the FPGA. The FPGA carries out synchronous coding on the initial signal, and sends and receives a clock and the initial signal code through a high-speed serial transceiving module in the FPGA. The clock fan-out module comprises a local crystal oscillator, a PLL (phase locked loop) and a clock fan-out buffer, and fans out a local crystal oscillator clock or a clock recovered by the high-speed serial transceiving module to each acquisition node in the chassis through a special connection channel.
In order to ensure accurate fan-out of the start signal, the transmission delay of the start signal in the chassis needs to be controlled. The initial signal transmission delay from the master node chassis to the child node chassis is maintained deterministic and consistent by employing equal length cables and using the same signal reception and digitization node hardware design and logic design. And the starting signal fanout in the sub-box is also deterministic in transmission delay because the recovery clock and the starting signal coded data are synchronous and the hardware of the special connecting channel for fanout is consistent. Therefore, what needs to be accurately controlled is fan-out of a starting signal inside the main node chassis, a schematic block diagram of a method for accurately fanning out the starting signal inside the main node chassis is shown in fig. 5, and a high-speed comparator is used for carrying out timing discrimination inside the chassis to obtain a starting signal pulse, wherein the starting signal pulse is an asynchronous signal relative to an electronic system. Before further digitally encoded fanout of the start signal, an asynchronous start signal synchronization module is required to perform synchronous processing on the asynchronous start signal. Due to the uncertain time difference t1 between the leading edge of the asynchronous start signal and the leading edge of the signal receiving and digitizing node master clock, there is an uncertain propagation delay t3 between the asynchronous start signal and the synchronous start signal. In order to ensure the fan-out precision of the initial signal, the uncertain delay is corrected by adopting a real-time measurement method, and the fine initial measurement module measures the phase difference between each asynchronous initial signal and the system clock by using a time measurement conversion circuit to obtain the asynchronous initial signal phase difference t 1. The time measurement conversion circuit is realized by utilizing carry chains in the FPGA, and covers an accurate time measurement range of 8ns through about 127 cascade carry chains. When the asynchronous starting signal synchronization module detects an asynchronous starting signal, the asynchronous starting signal synchronization module gives a synchronous starting signal after a fixed number of clock cycles t2, t2 and a phase difference t1 jointly form an asynchronous starting signal time difference t3, the asynchronous starting signal time difference t3 is packed and uploaded along with encoded data of each corresponding starting signal, and during each flight time measurement, fan-out delay of the corresponding starting signal is determined, so that delay uncertainty in the fan-out process of the starting signal is eliminated, and accurate fan-out of the starting signal is completed.
The above examples are provided only for the purpose of describing the present invention, and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims. Various equivalent substitutions and modifications can be made without departing from the spirit and principles of the invention, and are intended to be within the scope of the invention.