CN113284949B

CN113284949B - Gallium nitride based device and method of making the same

Info

Publication number: CN113284949B
Application number: CN202110816506.XA
Authority: CN
Inventors: 李俊
Original assignee: Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Current assignee: Smic Yuezhou Integrated Circuit Manufacturing Shaoxing Co ltd
Priority date: 2021-07-20
Filing date: 2021-07-20
Publication date: 2021-11-19
Anticipated expiration: 2041-07-20
Also published as: CN113284949A

Abstract

The present invention provides a gallium nitride-based device and a manufacturing method thereof, wherein a gate trench is formed in a substrate and then a gallium nitride-based epitaxial stack is produced, and a gate dielectric layer is further formed, a gate is filled, and a parallel The source ohmic contact structure and the drain ohmic contact structure in the gate trench can reduce the size of the device on the premise of having the same performance as the planar structure, and can make the thickness of the GaN-based epitaxial stacks all over the wafer. The uniformity is improved, and the flow direction of the 2DEG is made perpendicular to the gate, which ultimately improves the turn-on voltage and in-plane yield of the device.

Description

Gallium nitride-based device and method of manufacturing the same

Technical Field

The invention relates to the technical field of semiconductor device manufacturing, in particular to a gallium nitride-based device and a manufacturing method thereof.

Background

A heterojunction structure formed by an AlGaN layer and a GaN layer has a natural two-dimensional electron gas channel (2 DEG), so that the GaN-based device has a depletion-type switching characteristic and is used as a switching power device in various working environments such as motor driving and power supply.

The current GaN-based devices are mostly planar structures, i.e. they have a 2DEG heterojunction structure, and the source, gate and drain are all designed on the same plane of the device. The GaN-based device with the planar structure has the defects of large volume, no further improvement of the turn-on voltage and the in-plane yield and the like.

Disclosure of Invention

The invention aims to provide a gallium nitride-based device and a manufacturing method thereof, so as to obtain smaller volume and higher turn-on voltage.

To achieve the above object, the present invention provides a method for manufacturing a gallium nitride-based device, comprising:

providing a substrate, and etching the substrate to form a grid groove;

sequentially epitaxially growing a transition layer, a buffer layer, a gallium nitride-based channel layer and a barrier layer on the gate trench and the substrate to form a gallium nitride-based epitaxial lamination;

depositing a gate dielectric layer on the surface of the gallium nitride-based epitaxial lamination and forming a gate filled in the gate groove;

etching and opening the gate dielectric layers on two sides of the gate trench to form a first trench and a second trench which respectively expose the surface of the gallium nitride-based epitaxial lamination, wherein the first trench and the second trench are parallel to the gate trench;

and forming a source ohmic contact structure filled in the first groove and a drain ohmic contact structure filled in the second groove.

Based on the same inventive concept, the present invention also provides a gallium nitride-based device, comprising:

a substrate having a gate trench formed therein;

a gallium nitride-based epitaxial stack including a transition layer, a buffer layer, a gallium nitride-based channel layer and a barrier layer stacked in sequence on the gate trench and the substrate;

the grid dielectric layer covers the surface of the gallium nitride-based epitaxial lamination and is provided with a first groove and a second groove which are exposed out of the surfaces of the gallium nitride-based epitaxial lamination on two sides of the grid groove, and the first groove and the second groove are parallel to the grid groove;

the grid electrode is filled in the grid electrode groove and positioned on the surface of the grid electrode dielectric layer;

the source electrode ohmic contact structure is filled in the first groove and is electrically contacted with the gallium nitride-based epitaxial lamination;

and the drain ohmic contact structure is filled in the second groove and is electrically contacted with the gallium nitride-based epitaxial lamination.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

1. the gallium nitride-based device with the deep groove structure is formed, and the size of the device can be reduced on the premise of having the same performance as a plane structure.

2. Because the gallium nitride-based epitaxial lamination grows in the grid groove, the thickness uniformity of the gallium nitride-based epitaxial lamination at each position of the wafer can be improved, and the first groove for defining the source electrode and the second groove for defining the drain electrode are parallel to the grid groove (namely the grid, the source and the drain are parallel), so that the flow direction of the 2DEG is perpendicular to the grid electrode, and the turn-on voltage of the device is improved.

3. The grid is formed by filling the P-type or N-type gallium nitride in the grid groove, so that the problem that the machine utilization rate and the in-plane yield cannot be further improved due to poor etching uniformity when the P-type or N-type gallium nitride is etched in the wafer plane to form the grid in the prior art can be solved, namely, the technical scheme of the invention can improve the in-plane yield and the machine utilization rate of the wafer.

Drawings

Fig. 1 is a flow chart of a method of fabricating a gallium nitride based device according to an embodiment of the present invention.

Fig. 2 to 6 are schematic cross-sectional views of device structures in a method of manufacturing a gallium nitride-based device according to an embodiment of the present invention.

Fig. 7 is a schematic top view of the device structure in the method of fabricating a gallium nitride-based device according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "or" connected to "other elements or layers, it can be directly on, connected to, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …", "directly connected to" other elements or layers, there are no intervening elements or layers present. Although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. Spatial relationship terms such as "below … …", "below", "lower", "above … …", "above", "upper", and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" … …, or "beneath" would then be oriented "on" other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Referring to fig. 1, an embodiment of the present invention provides a method for manufacturing a gallium nitride-based device, which includes the following steps:

s1, providing a substrate, and etching the substrate to form a gate groove;

s2, sequentially epitaxially growing a transition layer, a buffer layer, a gallium nitride-based channel layer and a barrier layer on the grid groove and the substrate to form a gallium nitride-based epitaxial lamination;

s3, depositing a gate dielectric layer on the surface of the gallium nitride-based epitaxial lamination and forming a gate filled in the gate groove;

s4, etching and opening the gate dielectric layers on two sides of the gate trench to form a first trench and a second trench which are respectively exposed out of the surface of the GaN-based epitaxial lamination, wherein the first trench and the second trench are parallel to the gate trench;

and S5, forming a source ohmic contact structure filled in the first groove and a drain ohmic contact structure filled in the second groove.

Referring to fig. 2, in step S1, first, a substrate 100 is provided, wherein the substrate 100 may be any suitable substrate material known to those skilled in the art, and the material of the substrate 100 is, for example, sapphire (α -Al)₂O₃) Gallium nitride (GaN), gallium arsenide (GaAs), silicon (Si), silicon carbide (SiC), aluminum nitride (AlN) or indium phosphide (InP), etc., wherein the substrate 100 preferably has a resistivity of less than 0.04 Ω. cm, such as a low-resistance silicon (Si) substrate or a low-resistance silicon carbide (SiC) substrate as the substrate 100, to effectively reduce the on-resistance of the finally formed gallium nitride-based device and improve the device performance; then, one or more dielectric layers are formed on the surface of the substrate as a mask layer (not shown) by a thermal oxidation process, a chemical vapor deposition process, or the like; then, patterning the mask layer through photoetching processes such as photoresist coating, exposure, development and the like and further combining with an etching process to define a region in which a gate groove is to be formed; then, with the patterned mask layer as a mask, etching the substrate 100 to a required depth by a dry etching process to form a gate trench 101; and finally, removing the mask layer.

Optionally, after the substrate 100 is etched to form the gate trench 101 in step S1, the inner surface of the gate trench 101 is also rounded and smoothed by any suitable surface rounding process known to those skilled in the art to ensure film thickness uniformity during subsequent epitaxial growth of each layer in the gan-based epitaxial stack. The surface rounding process includes, for example, a process of performing surface thermal oxidation on the trench and then removing a thermal oxide layer on the surface, and then, for example, a process of performing ion doping on the inner surface of the gate trench to form an ion doped layer and then removing the ion doped layer.

Referring to fig. 3, in step S2, a transition layer (not shown), a buffer layer (not shown), a gallium nitride-based channel layer 102, a barrier layer 103, and the like may be sequentially formed on the surfaces of the substrate 100 and the gate trench 101 by using a suitable epitaxial growth process such as Metal Organic Chemical Vapor Deposition (MOCVD) to form a gallium nitride-based epitaxial stack.

The transition layer and the buffer layer are jointly used for releasing interface stress, reducing defect density, improving the film quality of subsequent active layers such as a gallium nitride-based channel layer, a barrier layer and the like, reducing the static current leakage of the device and improving the performance of the device.

The transition layer may be a GaN layer, an AlGaN layer or an AlN layer, or may be a composite structure in which a plurality of layers of films are laminated, and the plurality of films may be a plurality of layers of Al having different Al compositions_xGa_（1-x）N, where x is the molar content and is lower closer to the buffer layer. The buffer layer may be a single layer film or a composite structure of a multilayer film stack including, but not limited to, an AlN layer, an SiC layer, a GaN layer, an AlGaN (aluminum gallium nitride) layer, and a multilayer Al having a graded Al composition_xGa_（1-x）N, where x is the molar content and is lower the further away from the transition layer.

The barrier layer 103 may have a thickness smaller than, equal to, or larger than the gallium nitride-based channel layer 102, and the material of the barrier layer 103 includes at least one of AlGaN, InAlN (indium aluminum nitride), and AlN. Further, the barrier layer 103 may include a plurality of layers of AlGaN different in Al composition, and/or the barrier layer 103 may include a plurality of layers of InAlN different in Al composition.

As an example, the transition layer is an n-type doped GaN layer, the buffer layer is a P-type doped GaN layer, the gallium nitride-based channel layer 102 is an undoped GaN layer, the barrier layer 103 is an AlGaN layer having a uniform Al composition, and the thickness of the barrier layer 103 and the content of the Al composition are designed according to the on-voltage of the gallium nitride-based device to be manufactured.

It should be noted that, in the present embodiment, the barrier layer 103 is directly formed on the surface of the gallium nitride-based channel layer 102, but the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, it is allowed that other layers, such as an insertion layer (for example, AlN) and an epitaxial cap layer (for example, InAlN) are also formed between the barrier layer 103 and the gallium nitride-based channel layer 102, so as to further effectively protect the two-dimensional electron gas conduction channel formed in the gallium nitride-based channel layer 102, and avoid the problems of introducing impurities such as Si and O on the surface and forming a leakage channel at the homoepitaxial interface when the gallium nitride-based material is thick-film in homoepitaxy, thereby further increasing the breakdown voltage of the device. In other embodiments of the present invention, it is also allowed that other epitaxial layers, such as an epitaxial cap layer (e.g., InAlN) and the like, are further formed on the surface of the barrier layer 103 to further improve the device performance.

Referring to fig. 3, in step S3, first, a gate dielectric layer 104 is deposited on the surface of the topmost film layer of the gan-based epitaxial stack by a chemical vapor deposition or atomic layer deposition process, and the gate dielectric layer 104 covers not only the surface of the topmost film layer of the gan-based epitaxial stack (in this embodiment, the barrier layer 103) in the gate trench 101, but also the surface of the topmost film layer of the gan-based epitaxial stack at the periphery of the gate trench 101.

The gate dielectric layer 104 is preferably a high-k dielectric with a dielectric constant k higher than that of silicon dioxide and silicon oxynitride, such as hafnium oxide, lanthanum oxide, zinc oxide, aluminum oxide, and the like, and the high-k dielectric is used as the gate dielectric layer 104, so that on one hand, the physical thickness of the gate dielectric can be increased while the gate capacitance is kept unchanged, and the purposes of reducing gate leakage current, improving the turn-on voltage and improving the reliability of the device can be achieved, and on the other hand, the high-k dielectric retained at the periphery of the gate trench 101 in the following process can be used as a passivation layer to protect the gallium nitride-based epitaxial stacked layer at the periphery of the gate trench 101, thereby omitting the process of additionally forming the passivation layer and reducing the cost.

Referring to fig. 4 to 5, in step S3, a gate material layer 105 may be covered on the surface of the gate trench 101 and the gate dielectric layer 104 around the gate trench by using a suitable process such as metal organic chemical vapor deposition, wherein the gate material layer 105 is deposited to a thickness sufficient to fill the gate trench 101, and the material of the gate material layer 105 may include P-type gallium nitride or N-type gallium nitride; thereafter, the gate material layer 105 at the periphery of the gate trench 101 is removed by a Chemical Mechanical Polishing (CMP) or an etch-back process to form a gate 105a filled in the gate trench 101, wherein a top surface of the gate 105a may be flush with or lower than a top surface of the gate dielectric layer 104 at the periphery of the gate trench 101.

Referring to fig. 6 and 7, in step S4, a patterned photoresist layer is formed through a series of photolithography processes including photoresist coating, exposure, and development; then, using the patterned photoresist layer as a mask, the gate dielectric layer 104 on both sides of the periphery of the gate trench 101 is etched until the surface of the gan-based epitaxial stack under the gate dielectric layer 104 is exposed (for example, the top surface of the barrier layer 103 is exposed), so as to form a first trench (not shown) for defining a source region and a second trench (not shown) for defining a drain region, where the first trench and the second trench are both parallel to the gate trench 101, i.e., the length extending direction of the first trench and the second trench is the same as the length extending direction of the gate trench 101. In addition, the first trench and the second trench are disposed at both sides of the gate trench 101 and have a desired interval from the gate trench 101.

With continued reference to fig. 6 and 7, in step S5, the first trench and the second trench are filled with metal by any suitable process known to those skilled in the art, such as evaporation, sputtering, and the like, and annealing is performed to react the filled metal with the surface layer of the gan-based epitaxial stack, so as to form the source ohmic contact structure 106b filled in the first trench and the drain ohmic contact structure 106c filled in the second trench. Wherein, the filled metal can comprise any one or combination of Ti, Ni, Al, Mo, Pt, Pd, Au, Ta or W.

Wherein the thickness of the metal used to form the ohmic contact may be relatively thin, insufficient to fill the first trench and the second trench, after annealing to form the source ohmic contact structure 106b and the drain ohmic contact structure 106c, the excess metal at the periphery of the first trench and the second trench may be further removed, and depositing a thicker metal layer (not shown) on the bottom surfaces and other areas of the first and second trenches by a suitable process such as physical vapor deposition (e.g., evaporation, sputtering, etc.) or chemical vapor deposition, wherein the thickness of the deposited metal layer at least fills the first and second trenches, then, the excess metal layer is removed by an appropriate process such as a CMP (chemical mechanical polishing) process or an etch-back process, so that metal electrodes (not shown) are formed at the positions of the first trench and the second trench. The metal electrode may be a single-layer film or a multilayer film, and the material thereof includes at least one of Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN, TaN, and the like.

It should be noted that, in the technical solution of the present embodiment, after the step S3, a schottky contact structure 106a located on the top surface of the gate 105a and electrically contacted with the gate 105a needs to be further formed.

As an example, the step of forming the schottky contact structure 106a includes: after step S3, and before step S4, a metal layer is formed on the top surface of the gate 105a by any suitable process known to those skilled in the art, such as evaporation, sputtering, etc., and annealed to react the metal on the top surface of the gate 105a with the surface layer of the gate 105a to form the schottky contact structure 106 a. Wherein, the deposited metal can comprise any one or combination of Ti, Ni, Al, Mo, Pt, Pd, Au, Ta or W.

As another example, the step of forming the schottky contact structure 106a includes: in step S4, a metal is applied to the device surface by any suitable process known to those skilled in the art, such as evaporation, sputtering, etc., to fill the metal in the first and second trenches and also to cover the top surface of the gate 105a, and during annealing, the metal filled in the first and second trenches reacts with the surface layer of the gan-based epitaxial stack to form a source ohmic contact 106b filled in the first trench and a drain ohmic contact 106c filled in the second trench, and the metal covered on the top surface of the gate 105a reacts with the surface layer of the gate 105a to form a schottky contact 106 a.

As yet another example, the step of forming the schottky contact structure 106a includes: after step S5, a metal layer is formed on the top surface of the gate 105a by any suitable process known to those skilled in the art, such as evaporation, sputtering, etc., and an anneal is performed to react the metal on the top surface of the gate 105a with the surface layer of the gate 105a to form the schottky contact structure 106 a.

Based on the same inventive concept, please refer to fig. 6 and 7, an embodiment of the present invention further provides a gallium nitride-based device, which preferably adopts the method for manufacturing the gallium nitride-based device of the present invention. The gallium nitride-based device includes: the substrate 100, the gallium nitride-based epitaxial stack, the gate dielectric layer 104, the gate electrode 105a, the source ohmic contact structure 106b, and the drain ohmic contact structure 106 c.

The resistivity of the substrate 100 is less than 0.04 Ω · cm, so as to effectively reduce the on-resistance of the finally formed gallium nitride-based device and improve the device performance. A gate trench 101 is formed in the substrate 100.

The gallium nitride-based epitaxial stack includes a transition layer (not shown), a buffer layer (not shown), a gallium nitride-based channel layer 102, and a barrier layer 103, which are sequentially stacked on the inner surface of the gate trench 101 and the surface of the substrate 100 at the periphery of the gate trench 101.

The gate dielectric layer 104 covers the gate trench 101 and the surface of the gan-based epitaxial stack at the periphery of the gate trench 101, and has a first trench (not shown) and a second trench (not shown) that expose the surface of the gan-based epitaxial stack at both sides of the gate trench 101, where the first trench and the second trench are both parallel to the gate trench 101, and the first trench and the second trench are both located at both sides of the gate trench 101 and have a required spacing from the gate trench. Preferably, the gate dielectric layer 104 is a high-k dielectric having a dielectric constant k higher than that of silicon dioxide and silicon oxynitride.

The gate 105a is filled in the gate trench 101 and located on the surface of the gate dielectric layer 104, i.e. the sidewall and the bottom surface of the gate 105a are both wrapped by the gate dielectric layer 104. The material of the gate 105a includes P-type gallium nitride or N-type gallium nitride.

The source ohmic contact structure 106b is filled in the first trench of the gate dielectric layer 104 and electrically contacts the gallium nitride-based epitaxial stacked layer exposed at the bottom surface of the first trench, and the drain ohmic contact structure 106c is filled in the second trench of the gate dielectric layer 104 and electrically contacts the gallium nitride-based epitaxial stacked layer exposed at the bottom surface of the second trench.

The gan-based device of the present embodiment further includes a gate ohmic contact structure 106a, and the gate ohmic contact structure 106a is formed on top of the gate 105a and is in electrical contact with the gate 105 a.

In the gallium nitride-based device and the manufacturing method thereof of the present invention, the three regions of the gate, the source and the drain are formed in parallel, and thus the flow direction of the formed 2DEG is perpendicular to the gate electrode 105 a. And because the gallium nitride-based epitaxial lamination is grown in the gate trench 101, the thickness uniformity of the gallium nitride-based epitaxial lamination at each position of the wafer can be ensured to be good, and the etching damage to the gallium nitride-based epitaxial lamination when the gate material layer is etched to form the gate in the prior art can be avoided, so that the starting voltage of the device and the in-plane yield of the wafer are improved.

In addition, because the polarization effect on the side wall of the grid groove is weaker, and the polarization effect on the bottom surface of the grid groove is stronger, the number of 2 DEGs on the side wall of the grid groove is relatively less, the starting voltage can be improved, the device can be turned off more easily, the number of 2 DEGs on the bottom surface of the grid groove is relatively more, and the requirement of large current can be met.

In addition, the depth of the grid groove is deepened, so that the unit device area can be increased, and the device with smaller volume can be obtained.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.

Claims

1. a manufacturing method of a gallium nitride based device, is characterized in that, comprising:

providing a substrate, and etching the substrate to form gate trenches;

A transition layer, a buffer layer, a GaN-based channel layer and a barrier layer are sequentially epitaxially grown on the gate trench and the substrate to form a GaN-based epitaxial stack;

A gate dielectric layer is deposited on the surface of the gallium nitride-based epitaxial stack and a gate is formed to fill the gate trench, the gate is P-type gallium nitride, and the top surface of the gate is being flush with or lower than the top surface of the gate dielectric layer at the periphery of the gate trench;

Etching open the gate dielectric layers on both sides of the gate trench to form a first trench and a second trench respectively exposing the surface of the gallium nitride-based epitaxial stack, and the first trench and the second trenches are both parallel to the gate trenches;

forming a source ohmic contact structure filled in the first trench and a drain ohmic contact structure filled in the second trench, wherein the source ohmic contact structure, the drain ohmic contact structure and The gate forms parallel gate, source and drain regions, and two-dimensional electron gas is formed on the sidewall and bottom surface of the gate trench. The polarization effect is weaker than the polarization effect on the bottom surface of the gate trench, so that the two-dimensional electron gas on the sidewall of the gate trench is less than the two-dimensional electron gas on the bottom surface of the gate trench.

2 . The manufacturing method according to claim 1 , wherein the resistivity of the substrate is less than 0.04 Ω·cm. 3 .

3 . The manufacturing method of claim 1 , wherein the gate dielectric layer is a high-k dielectric with a dielectric constant k higher than that of silicon dioxide and silicon oxynitride. 4 .

4 . The manufacturing method according to claim 1 , further comprising: before etching and opening the gate dielectric layer on both sides of the gate trench, or before forming a source ohmic contact structure and a drain ohmic contact structure. 5 . Simultaneously with the contact structure, or after forming the source ohmic contact structure and the drain ohmic contact structure, a Schottky contact structure is formed on top of the gate.

5. A gallium nitride-based device, characterized in that, comprising:

a substrate, a gate trench is formed in the substrate;

A GaN-based epitaxial stack, comprising a transition layer, a buffer layer, a GaN-based channel layer and a barrier layer stacked on the gate trench and the substrate in sequence;

A gate dielectric layer covering the surface of the gallium nitride-based epitaxial stack and having a first trench and a second trench exposing the surfaces of the gallium nitride-based epitaxial stack on both sides of the gate trench two trenches, and both the first trench and the second trench are parallel to the gate trench;

a gate, filled in the gate trench and located on the surface of the gate dielectric layer, the gate is P-type gallium nitride, and the top surface of the gate is flush with or lower than the gate the top surface of the gate dielectric layer around the trench;

a source ohmic contact structure, filled in the first trench and in electrical contact with the gallium nitride-based epitaxial stack;

a drain ohmic contact structure, filled in the second trench and in electrical contact with the gallium nitride-based epitaxial stack;

Wherein, the source ohmic contact structure, the drain ohmic contact structure and the gate form three parallel regions of gate, source and drain, and the GaN-based device is also in the gate trench Two-dimensional electron gas is formed on the sidewall and bottom surface of the gate trench, and the polarization effect on the sidewall of the gate trench is weaker than that on the bottom surface of the gate trench, so that the gate trench is The two-dimensional electron gas on the sidewalls is less than the two-dimensional electron gas on the bottom surface of the gate trench.

6 . The gallium nitride-based device of claim 5 , wherein the resistivity of the substrate is less than 0.04 Ω·cm. 7 .

7 . The gallium nitride based device according to claim 5 , wherein the gate dielectric layer is a high-k dielectric with a dielectric constant k higher than that of silicon dioxide and silicon oxynitride. 8 .

8. The gallium nitride based device of claim 5, further comprising: a gate ohmic contact structure formed on top of the gate and in electrical contact with the gate.