CN113257672B - Super junction device zero-layer marking method and zero-layer marking structure - Google Patents
Super junction device zero-layer marking method and zero-layer marking structure Download PDFInfo
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Abstract
本发明公开了一种超级结器件零层标记制作方法，包括以下步骤：提供衬底；在衬底表面形成超级结结构；从超级结结构上表面，沿垂直衬底上表面方向，向下形成标记槽，标记槽贯穿超级结结构，并深入至衬底内部；在标记槽内形成填充材料层，形成零层标记，该零层标记的深宽比小于0.5。本发明能提升硬掩模版膜层填充能力，使得零层套刻标记/对位标记处PEOX膜层没有空洞，在外延填充后没有发生损坏。既能避免台阶覆盖性较差的硬掩模版造成零层标记损坏，又能避免深沟槽式硬掩模版淀积造成零层标记损坏，能保障对准作业，提高超级结产品对位精度。
The invention discloses a method for making a zero-layer mark of a super junction device, which comprises the following steps: providing a substrate; forming a super junction structure on the surface of the substrate; marking grooves, the marking grooves penetrate the super junction structure and penetrate deep into the substrate; a filling material layer is formed in the marking grooves to form a zero-layer mark, and the aspect ratio of the zero-layer mark is less than 0.5. The invention can improve the filling ability of the hard mask film layer, so that the PEOX film layer at the zero-layer overlay mark/alignment mark has no voids, and no damage occurs after epitaxial filling. It can not only avoid the damage of the zero-layer mark caused by the hard mask with poor step coverage, but also avoid the damage of the zero-layer mark caused by the deposition of the deep trench hard mask, which can ensure the alignment operation and improve the alignment accuracy of the super junction product.
Description
技术领域technical field
本发明涉及半导体制造领域，特别是涉及一种超级结器件零层标记制作方法。本发明还涉及一种超级结器件零层标记结构。The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing zero-layer marking of a super junction device. The invention also relates to a zero-layer marking structure of a super junction device.
背景技术Background technique
基于超级结技术(super-junction)的功率MOSFET已成为高压开关转换器领域的业界规范。它们提供更低的RDS(on)，同时具有更少的栅极和和输出电荷，这有助于在任意给定频率下保持更高的效率。Power MOSFETs based on super-junction technology have become the industry norm in the field of high voltage switching converters. They provide lower RDS(on) with less gate and output charge, which helps maintain higher efficiency at any given frequency.
在SJ(super-junction)工艺中，当使用台阶覆盖性较差的硬掩模版(如PECVD生长的PEOX)，且零层标记深宽比大于某阈值时，零层套刻标记/对位标记在外延填充后发生损坏，容易导致套刻标记量测失败或Wafer reject，无法作业。In the SJ (super-junction) process, when a hard mask with poor step coverage (such as PEOX grown by PECVD) is used, and the aspect ratio of the zero-layer mark is greater than a certain threshold, the zero-layer overlay mark/alignment mark Damage after epitaxial filling can easily lead to the failure of the overlay mark measurement or the Wafer reject, making it impossible to work.
深沟槽式硬掩模版淀积后(硬掩模版结构：PEOX+SiN+SiO2)，PEOX膜层形成空洞，在深沟槽刻蚀之后，零层套刻标记/对位标记的硬掩模版被刻开。外延填充时，外延沿着Si生长，标记四周损坏，也会造成标记量测失败，导致无法作业。After the deep trench hard mask is deposited (hard mask structure: PEOX+SiN+SiO2), the PEOX film layer forms voids, and after the deep trench etching, the hard mask of the zero-layer overlay mark/alignment mark was carved. During epitaxy filling, the epitaxy grows along the Si, and the surrounding area of the mark is damaged, which will also cause the mark measurement to fail, resulting in inoperability.
发明内容SUMMARY OF THE INVENTION
在发明内容部分中引入了一系列简化形式的概念,该简化形式的概念均为本领域现有技术简化，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。A series of concepts in simplified form are introduced in the summary of the invention, and the concepts in the simplified form are all simplifications of the prior art in the art, which will be further described in detail in the detailed description. The Summary of the Invention section of the present invention is not intended to attempt to limit the key features and essential technical features of the claimed technical solution, nor is it intended to attempt to determine the protection scope of the claimed technical solution.
本发明要解决的技术问题是提供一种用于超级结器件能避免台阶覆盖性较差的硬掩模版和/或深沟槽式硬掩模版淀积造成零层标记损坏的超级结器件零层标记制作方法。The technical problem to be solved by the present invention is to provide a zero-layer super junction device that can avoid the damage of the zero-layer mark caused by the deposition of the hard mask and/or the deep trench hard mask with poor step coverage for the super junction device. Mark making method.
本发明要解决的另一技术问题是提供一种用于超级结器件能避免台阶覆盖性较差的硬掩模版和/或深沟槽式硬掩模版淀积造成零层标记损坏的超级结器件零层标记结构。Another technical problem to be solved by the present invention is to provide a super junction device for super junction devices, which can avoid the damage of the zero-layer mark caused by the deposition of the hard mask and/or the deep trench hard mask with poor step coverage. Zero-level markup structure.
为解决上述技术问题，本发明提供的超级结器件零层标记制作方法，包括以下步骤：In order to solve the above-mentioned technical problems, the method for making a zero-layer mark of a super junction device provided by the present invention includes the following steps:
S1)提供衬底；S1) provide a substrate;
S2)在衬底表面形成超级结结构；S2) forming a super junction structure on the surface of the substrate;
S3)从超级结结构上表面，沿垂直衬底上表面方向，向下形成标记槽，标记槽贯穿超级结结构，并深入至衬底内部；S3) From the upper surface of the super junction structure, along the direction perpendicular to the upper surface of the substrate, a marking groove is formed downward, and the marking groove penetrates the super junction structure and penetrates into the interior of the substrate;
S4)在标记槽内形成填充材料层，形成零层标记，该零层标记的深宽比小于0.5。经过实验发现，缩小零层标记的深宽比，能降低零层标记的损坏几率。S4) forming a filling material layer in the marking groove to form a zero-layer mark, and the aspect ratio of the zero-layer mark is less than 0.5. Through experiments, it is found that reducing the aspect ratio of the zero-layer mark can reduce the damage probability of the zero-layer mark.
可选择的，进一步改进超级结器件零层标记制作方法，该零层标记的深宽比范围为大于0.1且小于0.5。经过实验发现，缩小零层标记的深宽比，能降低零层标记的损坏几率，但是过小的零层标记不利于对准作业。Optionally, a method for fabricating a zero-layer mark for a super junction device is further improved, and the aspect ratio of the zero-layer mark ranges from greater than 0.1 to less than 0.5. Through experiments, it is found that reducing the aspect ratio of the zero-layer mark can reduce the damage probability of the zero-layer mark, but the zero-layer mark that is too small is not conducive to the alignment operation.
可选择的，进一步改进超级结器件零层标记制作方法该零层标记的深宽比范围大于0.15且小于0.25。经过实验发现，缩小零层标记的深宽比至0.15～-0.25在降低零层标记的损坏几率的同时能确保对对准作业无影响。Optionally, the method for fabricating a zero-layer mark of a super junction device is further improved. The aspect ratio of the zero-layer mark is greater than 0.15 and less than 0.25. Through experiments, it is found that reducing the aspect ratio of the zero-layer mark to 0.15 to -0.25 can reduce the damage probability of the zero-layer mark and ensure no influence on the alignment operation.
可选择的，进一步改进超级结器件零层标记制作方法，所述超级结器件的硬掩模版是气相沉积法(PECVD)生长的聚氧化乙烯(PEOX)。Optionally, a method for fabricating a zero-layer marking of a super junction device is further improved, and the hard mask of the super junction device is polyethylene oxide (PEOX) grown by vapor deposition (PECVD).
可选择的，进一步改进超级结器件零层标记制作方法，所述零层标记是零层套刻标记和/或零层对位标记。Optionally, a method for making a zero-layer mark for a super junction device is further improved, where the zero-layer mark is a zero-layer overlay mark and/or a zero-layer alignment mark.
为解决上述技术问题，本发明提供一种超级结器件零层标记结构，包括：在衬底表面形成的超级结结构，从超级结结构上表面，沿垂直衬底上表面方向，向下形成的标记槽，标记槽贯穿超级结结构，并深入至衬底内部，在标记槽内形成填充材料层形成的零层标记，该零层标记的深宽比小于0.5。In order to solve the above-mentioned technical problems, the present invention provides a zero-layer marking structure of a super junction device, comprising: a super junction structure formed on the surface of a substrate, formed downward from the upper surface of the super junction structure along the direction perpendicular to the upper surface of the substrate. The marking groove penetrates the super junction structure and penetrates deep into the substrate, and a zero-layer mark formed by a filling material layer is formed in the marking groove, and the aspect ratio of the zero-layer mark is less than 0.5.
可选择的，进一步改进所述的超级结器件零层标记结构，该零层标记的深宽比范围为大于0.1且小于0.5。Optionally, the zero-layer marking structure of the super junction device is further improved, and the aspect ratio range of the zero-layer marking is greater than 0.1 and less than 0.5.
可选择的，进一步改进所述的超级结器件零层标记结构，该零层标记的深宽比范围大于0.15且小于0.25。Optionally, the zero-layer marking structure of the super junction device is further improved, and the aspect ratio range of the zero-layer marking is greater than 0.15 and less than 0.25.
可选择的，进一步改进所述的超级结器件零层标记结构，所述超级结器件的硬掩模版是气相沉积法(PECVD)生长的聚氧化乙烯(PEOX)。Optionally, to further improve the zero-layer marking structure of the super junction device, the hard mask of the super junction device is polyethylene oxide (PEOX) grown by vapor deposition (PECVD).
可选择的，进一步改进所述的超级结器件零层标记结构，所述零层标记是零层套刻标记和/或零层对位标记。Optionally, the zero-layer mark structure of the super junction device is further improved, and the zero-layer mark is a zero-layer overlay mark and/or a zero-layer alignment mark.
在超级结工艺中，当使用台阶覆盖性较差的硬掩模版(如PECVD生长的PEOX)时，经过实验发现，缩小零层标记的深宽比，能降低零层标记的损坏几率，但是无限制的缩小零层标记的深宽比会对对准工艺造成困难。经过无数次实验，意外的发现在零层标记深宽比为0.15-0.25(例如0.2)时，能提升硬掩模版膜层填充能力，使得零层套刻标记/对位标记处PEOX膜层没有空洞，在外延填充后没有发生损坏。既能避免台阶覆盖性较差的硬掩模版造成零层标记损坏，又能避免深沟槽式硬掩模版淀积造成零层标记损坏，能保障对准作业，提高超级结产品对位精度。In the super junction process, when a hard mask with poor step coverage (such as PEOX grown by PECVD) is used, it is found through experiments that reducing the aspect ratio of the zero-layer marking can reduce the damage probability of the zero-layer marking, but no The limited aspect ratio of shrinking zero-level marks can cause difficulties in the alignment process. After countless experiments, it was unexpectedly found that when the aspect ratio of the zero-layer marking is 0.15-0.25 (eg 0.2), the filling capacity of the hard mask film layer can be improved, so that the PEOX film layer at the zero-layer overlay mark/alignment mark is not. voids, no damage occurred after epitaxial filling. It can not only avoid the damage of the zero-layer mark caused by the hard mask with poor step coverage, but also avoid the damage of the zero-layer mark caused by the deposition of the deep trench hard mask, which can ensure the alignment operation and improve the alignment accuracy of the super junction product.
附图说明Description of drawings
本发明附图旨在示出根据本发明的特定示例性实施例中所使用的方法、结构和/或材料的一般特性，对说明书中的描述进行补充。然而，本发明附图是未按比例绘制的示意图，因而可能未能够准确反映任何所给出的实施例的精确结构或性能特点，本发明附图不应当被解释为限定或限制由根据本发明的示例性实施例所涵盖的数值或属性的范围。下面结合附图与具体实施方式对本发明作进一步详细的说明：The drawings of the present invention are intended to supplement the description in the specification by illustrating the general characteristics of methods, structures and/or materials used in certain exemplary embodiments according to the present invention. However, the drawings of the present invention are schematic representations not to scale and thus may not accurately reflect the precise structural or performance characteristics of any given embodiment, and the drawings of the present invention should not be construed as limiting or limiting the scope of the invention in accordance with the present invention. The range of values or properties encompassed by the exemplary embodiments. The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments:
图1是本发明流程示意图。Figure 1 is a schematic flow chart of the present invention.
图2是发明结构示意图。Figure 2 is a schematic diagram of the structure of the invention.
具体实施方式Detailed ways
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所公开的内容充分地了解本发明的其他优点与技术效果。本发明还可以通过不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点加以应用，在没有背离发明总的设计思路下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。本发明下述示例性实施例可以多种不同的形式来实施，并且不应当被解释为只限于这里所阐述的具体实施例。应当理解的是，提供这些实施例是为了使得本发明的公开彻底且完整，并且将这些示例性具体实施例的技术方案充分传达给本领域技术人员。The embodiments of the present invention are described below through specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without departing from the general design idea of the invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other under the condition of no conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
第一实施例；first embodiment;
如图1所示，本发明提供超级结器件零层标记制作方法，包括以下步骤：As shown in FIG. 1 , the present invention provides a method for fabricating a zero-layer mark of a super junction device, comprising the following steps:
S1)提供衬底；S1) provide a substrate;
S2)在衬底表面形成超级结结构；S2) forming a super junction structure on the surface of the substrate;
S3)从超级结结构上表面，沿垂直衬底上表面方向，向下形成标记槽，标记槽贯穿超级结结构，并深入至衬底内部；S3) From the upper surface of the super junction structure, along the direction perpendicular to the upper surface of the substrate, a marking groove is formed downward, and the marking groove penetrates the super junction structure and penetrates into the interior of the substrate;
S4)在标记槽内形成填充材料层，形成零层标记，该零层标记的深宽比小于0.5。S4) forming a filling material layer in the marking groove to form a zero-layer mark, and the aspect ratio of the zero-layer mark is less than 0.5.
第二实施例；second embodiment;
继续参考图1所示，本发明提供超级结器件零层标记制作方法，包括以下步骤：Continuing to refer to FIG. 1, the present invention provides a method for fabricating a zero-layer mark of a super junction device, including the following steps:
S1)提供衬底；S1) provide a substrate;
S2)在衬底表面形成超级结结构；S2) forming a super junction structure on the surface of the substrate;
S3)从超级结结构上表面，沿垂直衬底上表面方向，向下形成标记槽，标记槽贯穿超级结结构，并深入至衬底内部；S3) From the upper surface of the super junction structure, along the direction perpendicular to the upper surface of the substrate, a marking groove is formed downward, and the marking groove penetrates the super junction structure and penetrates into the interior of the substrate;
S4)在标记槽内形成填充材料层，形成零层标记，该零层标记的深宽比范围为大于0.1且小于0.5。S4) forming a filling material layer in the marking groove to form a zero-layer mark, and the aspect ratio of the zero-layer mark ranges from greater than 0.1 to less than 0.5.
第三实施例；third embodiment;
继续参考图1所示，本发明提供超级结器件零层标记制作方法，包括以下步骤：Continuing to refer to FIG. 1, the present invention provides a method for fabricating a zero-layer mark of a super junction device, including the following steps:
S1)提供衬底；S1) provide a substrate;
S2)在衬底表面形成超级结结构；S2) forming a super junction structure on the surface of the substrate;
S3)从超级结结构上表面，沿垂直衬底上表面方向，向下形成标记槽，标记槽贯穿超级结结构，并深入至衬底内部；S3) From the upper surface of the super junction structure, along the direction perpendicular to the upper surface of the substrate, a marking groove is formed downward, and the marking groove penetrates the super junction structure and penetrates into the interior of the substrate;
S4)在标记槽内形成填充材料层，形成零层标记，该零层标记的深宽比范围大于0.15且小于0.25，优选，该零层标记的深宽比为0.2。S4) A filling material layer is formed in the marking groove to form a zero-layer mark. The aspect ratio of the zero-layer mark is greater than 0.15 and less than 0.25. Preferably, the zero-layer mark has an aspect ratio of 0.2.
其中，所述超级结器件的硬掩模版是气相沉积法(PECVD)生长的聚氧化乙烯(PEOX)，所述零层标记是零层套刻标记和/或零层对位标记。Wherein, the hard mask of the super junction device is polyethylene oxide (PEOX) grown by vapor deposition (PECVD), and the zero-layer mark is a zero-layer overlay mark and/or a zero-layer alignment mark.
第四实施例；fourth embodiment;
如图2所示，本发明提供一种超级结器件零层标记结构，包括：在衬底表面形成的超级结结构，从超级结结构上表面，沿垂直衬底上表面方向，向下形成的标记槽，标记槽贯穿超级结结构，并深入至衬底内部，在标记槽内形成填充材料层形成的零层标记，该零层标记的深宽比小于0.5。As shown in FIG. 2 , the present invention provides a zero-layer marking structure of a super junction device, including: a super junction structure formed on the surface of a substrate, from the upper surface of the super junction structure, along the direction perpendicular to the upper surface of the substrate, downwardly formed The marking groove penetrates the super junction structure and penetrates deep into the substrate, and a zero-layer mark formed by a filling material layer is formed in the marking groove, and the aspect ratio of the zero-layer mark is less than 0.5.
第五实施例；fifth embodiment;
继续图2所示，本发明提供一种超级结器件零层标记结构，包括：在衬底表面形成的超级结结构，从超级结结构上表面，沿垂直衬底上表面方向，向下形成的标记槽，标记槽贯穿超级结结构，并深入至衬底内部，在标记槽内形成填充材料层形成的零层标记，该零层标记的深宽比范围为大于0.1且小于0.5。Continuing as shown in FIG. 2 , the present invention provides a zero-layer marking structure for a super junction device, including: a super junction structure formed on the surface of the substrate, from the upper surface of the super junction structure, along the direction perpendicular to the upper surface of the substrate, downwardly formed Marking grooves. The marking grooves penetrate the super junction structure and penetrate deep into the substrate. A zero-layer mark formed by a filling material layer is formed in the marking groove. The aspect ratio of the zero-layer mark ranges from greater than 0.1 to less than 0.5.
第六实施例；sixth embodiment;
继续图2所示，本发明提供一种超级结器件零层标记结构，包括：在衬底表面形成的超级结结构，从超级结结构上表面，沿垂直衬底上表面方向，向下形成的标记槽，标记槽贯穿超级结结构，并深入至衬底内部，在标记槽内形成填充材料层形成的零层标记，该零层标记的深宽比范围大于0.15且小于0.25。Continuing as shown in FIG. 2 , the present invention provides a zero-layer marking structure for a super junction device, including: a super junction structure formed on the surface of the substrate, from the upper surface of the super junction structure, along the direction perpendicular to the upper surface of the substrate, downwardly formed The marking groove penetrates the super junction structure and penetrates deep into the substrate, and a zero-layer mark formed by a filling material layer is formed in the marking groove, and the aspect ratio of the zero-layer mark is greater than 0.15 and less than 0.25.
其中，所述超级结器件的硬掩模版是气相沉积法(PECVD)生长的聚氧化乙烯(PEOX)，所述零层标记是零层套刻标记和/或零层对位标记。Wherein, the hard mask of the super junction device is polyethylene oxide (PEOX) grown by vapor deposition (PECVD), and the zero-layer mark is a zero-layer overlay mark and/or a zero-layer alignment mark.
除非另有定义，否则这里所使用的全部术语(包括技术术语和科学术语)都具有与本发明所属领域的普通技术人员通常理解的意思相同的意思。还将理解的是，除非这里明确定义，否则诸如在通用字典中定义的术语这类术语应当被解释为具有与它们在相关领域语境中的意思相一致的意思，而不以理想的或过于正式的含义加以解释。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary should be construed to have meanings consistent with their meanings in the relevant art context, rather than ideally or excessively The formal meaning is explained.
以上通过具体实施方式和实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the present invention. Without departing from the principles of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.
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