CN113241946B - A DC/DC conversion circuit and a DC/DC converter - Google Patents

Abstract

The invention provides a direct current/direct current conversion circuit and a direct current/direct current converter, and relates to the technical field of integrated circuits. The circuit comprises: the device comprises an output unit, a rectifying unit and a detection control unit; the output unit receives an input voltage and outputs a first output voltage to the rectifying unit and the detection control unit; the rectification unit rectifies and filters the first output voltage, outputs a second output voltage, generates a first signal and transmits the first signal to the detection control unit; the detection control unit receives the first signal and the first output voltage and generates a control signal to control the DC/DC conversion circuit to work in an accelerated charging mode, a normal charging mode or a sleep mode. The direct current/direct current conversion circuit of the embodiment of the invention shortens the establishment time of the output voltage of the direct current/direct current converter while reducing the output voltage ripple, and has higher practical value.

Description

A DC/DC conversion circuit and a DC/DC converter

technical field

The present invention relates to the technical field of integrated circuits, and in particular, to a DC/DC conversion circuit and a DC/DC converter.

Background technique

At present, DC/DC converters have important applications in MEMS accelerometers and MEMS gyroscope interface integrated circuits. In particular, the boost DC/DC converter provides a high enough drive voltage for closed-loop MEMS inertial sensors to generate a high enough electrostatic force for the closed-loop feedback function. The closed-loop MEMS inertial sensor system has high requirements on the settling time and ripple amplitude of the driving voltage. The traditional DC/DC (direct current/direct current) converter often uses a charging current that is fixed or proportional to the difference between the reference voltage and the output voltage. It is difficult to meet the requirements of low ripple and fast settling while maintaining a low static power consumption state.

The charging current of the boost DC/DC converter with the traditional structure is inversely proportional to the voltage settling time, and proportional to the ripple size and the static power consumption. In order to ensure low static power consumption, the traditional structure of the DC/DC converter is difficult to achieve. The rapid establishment of the voltage, usually the voltage establishment time is in the order of tens of milliseconds, cannot meet the requirement that the voltage establishment time of the MEMS inertial sensor is less than 10 milliseconds. Even if a dynamic charging current is used to make the charging current proportional to the difference between the reference voltage and the output voltage, when the output voltage is close to the reference voltage, the charging current becomes smaller, which increases the stabilization time for the output voltage to rise to the preset value, still unable to It can meet the requirement that the driving voltage of the MEMS inertial sensor is completely and stably established in a short time. In addition, high-precision MEMS inertial sensors require the ripple of the driving voltage to be less than 1mV, and it is difficult for the traditional DC/DC converter to limit the ripple to less than 1mV. Therefore, how to shorten the settling time of the output voltage of the boost DC/DC converter while reducing the output voltage ripple is an urgent problem to be solved.

SUMMARY OF THE INVENTION

The present invention provides a DC/DC conversion circuit and a DC/DC converter, and proposes a technical scheme that not only reduces the output voltage ripple, but also shortens the settling time of the output voltage of the boosted DC/DC converter.

A first aspect of the embodiments of the present invention provides a DC/DC conversion circuit, the circuit includes: an output unit, a rectification unit, and a detection control unit;

the output unit receives an input voltage, and outputs a first output voltage to the rectification unit and the detection control unit, where the first output voltage is higher than the input voltage;

The rectifying unit rectifies and filters the first output voltage, outputs a second output voltage, and generates a first signal and transmits it to the detection control unit, where the first signal represents whether the establishment of the second output voltage is completed ;

The detection control unit receives the first signal and the first output voltage, and generates a control signal to control the DC/DC conversion circuit to work in an accelerated charging mode, or in a normal charging mode, or in a sleep mode ;

Wherein, the accelerated charging mode is: a mode in which the first output voltage is increased with the highest allowable charging current;

The normal charging mode is: a mode in which the first output voltage is increased by a preset charging current;

The sleep mode is a mode in which the raising of the first output voltage is stopped until the first output voltage drops below a reference voltage.

Optionally, the output unit includes: an inductor, a first power transistor and a second power transistor;

The first end of the inductor receives the input voltage, and the second end of the inductor is connected to the drain of the first power transistor and the drain of the second power crystal, respectively;

The gate of the first power transistor is connected to the driving module in the detection control unit;

the source of the first power transistor is grounded;

the gate of the second power transistor is connected to the driving module;

The source of the second power transistor is connected to the rectifying unit, and the source of the second power transistor outputs the first output voltage.

Optionally, the rectifying unit includes: a third power transistor, a first resistor, a second resistor, a first inverter, and an operational amplifier;

the source of the third power transistor is connected to the source of the second power transistor;

The gate of the third power transistor is connected to the output end of the operational amplifier and the input end of the first inverter respectively;

The drain of the third power transistor is connected to the first end of the first resistor, and the drain of the third power transistor outputs the second output voltage;

The second end of the first resistor is connected to the first end of the second resistor and the non-inverting end of the operational amplifier;

the second end of the second resistor is grounded;

an inverting terminal of the operational amplifier receives the reference voltage;

The output end of the first inverter is connected to the first pulse generating module in the detection control unit, and the output end of the first inverter outputs the first signal.

Optionally, the detection control unit includes: a third resistor, a fourth resistor, a first comparator, a second comparator, a second pulse generation module, a logic control module, and a second inverter;

The first end of the third resistor is connected to the non-inverting end of the first comparator, and the first end of the third resistor receives the first output voltage;

The second end of the third resistor is connected to the first end of the fourth resistor and the non-inverting end of the second comparator respectively;

the second end of the fourth resistor is grounded;

the inverting terminal of the first comparator receives the voltage of the second terminal of the inductor;

The output end of the first comparator is connected to the input end of the logic control module, and the output end of the first comparator outputs a third signal, and the third signal represents the second end of the inductance, and is connected to the second end of the inductor. the current flow between the sources of the second power transistor;

an inverting terminal of the second comparator receives the reference voltage;

The output end of the second comparator is connected to the input end of the logic control module, the output end of the second comparator outputs a second signal, and the second signal represents the first output voltage and the reference The magnitude relationship between the voltages;

The output end of the logic control module is connected with the input end of the driving module;

The output end of the driving module is respectively the gate of the first power transistor, the gate of the second power transistor, the input end of the second inverter, and the input end of the second pulse generating module. connected, the drive module outputs the control signal;

The output end of the second pulse generating module is connected with the logic control module;

The output end of the second inverter is connected to the first pulse generating module.

Optionally, the method includes: the first pulse generating module includes: an energy storage capacitor array, a first common transistor, and a third comparator;

The first end of the energy storage capacitor array is respectively connected with the charging current source, the non-inverting end of the third comparator, and the drain of the first common transistor;

The second end of the energy storage capacitor array receives the first signal and the external digital control signal;

The third end of the energy storage capacitor array is connected to the source of the first common transistor and grounded;

The gate of the first common transistor is connected to the output end of the second inverter;

an inverting terminal of the third comparator receives the reference voltage;

The output end of the third comparator is connected to the logic control module, and the output end of the third comparator outputs the first pulse signal.

Optionally, the energy storage capacitor array includes: a second common transistor, a third common transistor, a fourth common transistor, a fifth common transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth Capacitor, first OR gate, second OR gate, third OR gate;

The drain stages of the second common transistor, the third common transistor, the fourth common transistor, and the fifth common transistor are all connected to the charging current source, the non-inverting terminal of the third comparator, The drain of the first common transistor and the first end of the fifth capacitor are respectively connected.

The gate of the second ordinary transistor and the first input terminal of the first OR gate, the first input terminal of the second OR gate, the first input terminal of the third OR gate, the first input terminal of the The output terminals of the inverter are respectively connected;

the source of the second common transistor is connected to the first end of the first capacitor;

the second end of the first capacitor, the second end of the second capacitor, the second end of the third capacitor, the second end of the fourth capacitor, the second end of the fifth capacitor, The sources of the first common transistors are respectively connected and grounded;

the gate of the third common transistor is connected to the output end of the first OR gate;

the gate of the fourth common transistor is connected to the output end of the second OR gate;

the gate of the fifth common transistor is connected to the output end of the third OR gate;

the second input terminal of the first OR gate receives the first digital control signal in the external digital control signal;

the second input terminal of the second OR gate receives the second digital control signal in the external digital control signal;

The second input terminal of the third OR gate receives a third digital control signal of the external digital control signals.

Optionally, the first signal being a high level indicates that the establishment of the second output voltage is completed, and the first signal being a low level indicates that the second output voltage has not been established;

The high level of the third signal indicates that the second terminal of the inductor and the source of the second power transistor flow in the direction of: from the source of the second power transistor to the source of the inductor. second end;

The low level of the third signal indicates the second terminal of the inductor, and the current flow between the second terminal of the inductor and the source of the second power transistor is: from the second terminal of the inductor to the second power transistor the source;

The high level of the second signal indicates that the first output voltage is higher than the reference voltage, and the low level of the second signal indicates that the first output voltage is lower than the reference voltage.

Optionally, the standard for completing the establishment of the second output voltage is: the magnitude of the second output voltage is equal to the product of the reference voltage and the first ratio;

The criterion that the second output voltage is not established is: the magnitude of the second output voltage is smaller than the product of the reference voltage and the first ratio;

The criterion that the first output voltage is higher than the reference voltage is: the magnitude of the first output voltage is greater than the product of the reference voltage and a second ratio, wherein the second ratio is greater than the first ratio;

The criterion that the first output voltage is lower than the reference voltage is that the magnitude of the first output voltage is not greater than the product of the reference voltage and the second ratio.

Optionally, when the first signal is at a high level, the second common transistor, the third common transistor, the fourth common transistor, and the fifth common transistor are all turned on, and the energy storage capacitor is turned on. The capacitance value of the array is a preset maximum capacitance value, and the first pulse signal maintains a low level for the longest duration;

When the first signal is at a low level, the second common transistor is turned off, the third common transistor, the fourth common transistor, and the fifth common transistor are controlled by the external digital signal, and the The capacitance value of the energy storage capacitor array is determined by the external digital signal, and the duration that the first pulse signal remains at a low level is determined by the external digital signal.

A second aspect of the embodiments of the present invention provides a DC/DC converter, where the DC/DC converter includes: the circuit according to any one of the first aspects.

In the DC/DC conversion circuit provided by the present invention, the output unit receives the input voltage and outputs a first output voltage higher than the input voltage to the rectifier unit and the detection control unit, and the rectifier unit rectifies and filters the first output voltage to reduce the first output voltage. The ripple of the voltage outputs a second output voltage with low ripple. At the same time, the rectifier unit generates a first signal indicating whether the establishment of the second output voltage is completed, and transmits it to the detection control unit. The detection control unit receives the first signal, the first signal After the voltage is output, a control signal is generated to control the DC/DC conversion circuit to work in an accelerated charging mode, or in a normal charging mode, or in a sleep mode. Among them, when the DC/DC conversion circuit works in the accelerated charging mode, the entire circuit increases the first output voltage with the highest allowable charging current, so that the first output voltage is quickly established, which is equivalent to the second output voltage being rapidly increased Compared with the current traditional DC/DC conversion circuit, it shortens the time for the output voltage to establish. The detection control unit can switch between the accelerated charging mode and the normal charging mode based on the first signal and the first output voltage. In the accelerated charging mode, the charging current is large to shorten the output voltage settling time. output current and ensure low output ripple, improving the noise performance of the sensor. The DC/DC conversion circuit of the present invention reduces the output voltage ripple and shortens the settling time of the output voltage of the DC/DC converter, which has high practical value.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the drawings that are used in the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. , for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative labor.

Fig. 1 is the circuit structure diagram of the boost type DC/DC converter of the traditional structure;

2 is a modular schematic diagram of a DC/DC conversion circuit according to an embodiment of the present invention;

3 is a schematic structural diagram of a preferred DC/DC conversion circuit in an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a preferred rectifier circuit 200 in an embodiment of the present invention;

5 is a schematic structural diagram of a preferred first pulse generation module 340 in an embodiment of the present invention;

FIG. 6 is a schematic waveform diagram of a DC/DC conversion circuit in an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The inventor found that it is difficult to limit the ripple to a low level in the current traditional DC/DC converter, and at the same time, the settling time of the output voltage is long, which is difficult to meet the working requirements of the MEMS inertial sensor. The inventors have further studied and found the reasons for the above problems. Combined with the circuit structure diagram of the boost DC/DC converter with the traditional structure shown in FIG. 1 , FIG. 1 includes a P-type power transistor M ₁ and an N-type power transistor M ₂ . , inductor L, resistor divider circuit (composed _of resistors R1 and R2 ₎ , comparator CMP, current detection module ISENSE, pulse generator PULSE, logic controller LOGIC, driver DRIVER for power transistors (M1 and M2).

When the circuit in FIG. 1 is working, the resistor divider circuit will divide the voltage to obtain a feedback voltage V _FB proportional to the output voltage V _OUT , which is compared with the voltage V _SW of the second end of the inductor L through the comparator CMP to generate a judgment signal and output to The logic control circuit LOGIC; the pulse generator PULSE generates a pulse signal that controls the charging time of the inductor L, and then controls the charging current to the source of the P-type power transistor M ₁ to output V _OUT ; the current detection module ISENSE detects the current flowing through the P-type power transistor by detecting Whether the charging current _of M1 is zero, it is judged whether the charging of the output _VOUT is completed, and the P _- type power transistor M1 is turned off after the charging is completed.

Since the charging current of the DC/DC converter is inversely proportional to the voltage settling time, and proportional to the ripple size and static power consumption, the DC/DC converter with the traditional structure in Figure 1 is difficult to achieve low static power consumption in order to ensure low static power consumption. The fast settling time of the MEMS inertial sensor, usually the voltage settling time is in the order of tens of milliseconds, which cannot meet the requirement that the voltage settling time of the MEMS inertial sensor is less than 10 milliseconds. Even if a dynamic charging current is used to make the charging current proportional to the difference between the reference voltage and the output voltage, when the output voltage is close to the reference voltage, the charging current becomes smaller, which increases the stabilization time for the output voltage to rise to the preset value, still unable to It can meet the requirement that the driving voltage of the MEMS inertial sensor is completely and stably established in a short time. In addition, high-precision MEMS inertial sensors require the ripple of the driving voltage to be less than 1mV, while the DC/DC converter with the traditional structure in Figure 1 is difficult to limit the ripple to less than 1mV due to the circuit structure and the characteristics of the components themselves.

Based on the above problems, the inventor creatively proposes the DC/DC conversion circuit of the embodiment of the present invention through a lot of research, actual testing, and simulation.

Referring to FIG. 2 , a modular schematic diagram of a DC/DC conversion circuit according to an embodiment of the present invention is shown. The DC/DC conversion circuit includes: an output unit, a rectification unit, and a detection control unit; the output unit receives an input voltage, and outputs a first output voltage higher than the input voltage to the rectification unit and the detection control unit; Rectification and filtering to output the second output voltage with reduced ripple. At the same time, the rectification unit generates a first signal indicating whether the establishment of the second output voltage is completed and transmits it to the detection control unit; the detection control unit receives the first signal and the first output voltage. , and generate a control signal to control the DC/DC conversion circuit to work in an accelerated charging mode, or in a normal charging mode, or in a sleep mode. Among them, the accelerated charging mode is: a mode in which the first output voltage is increased with the highest allowable charging current, thus ensuring the rapid establishment of the second output voltage; after the establishment of the second output voltage is completed, the normal charging mode is entered, and the normal working mode is : A mode in which the first output voltage is boosted with a preset charging current. The detection circuit unit switches between the accelerated charging mode and the normal charging mode based on the first signal and the first output voltage. In the accelerated charging mode, the charging current is large to shorten the settling time of the output voltage. In the normal charging mode, a proper output is maintained. current and ensure lower output ripple, improving the noise performance of the sensor. In addition, when the first output voltage is relatively high, a sleep mode is entered, and the sleep mode is a mode in which the increase of the first output voltage is stopped until the first output voltage drops below the reference voltage. Since only some components work in the sleep mode, this indirectly reduces the static power consumption of the DC/DC conversion circuit.

Referring to FIG. 3 , a schematic structural diagram of a preferred DC/DC conversion circuit in an embodiment of the present invention is shown. FIG. 3 includes an output circuit 100 , a rectifier circuit 200 and a detection control circuit 300 . The output circuit 100 specifically includes: an inductor L, a first power transistor MN_PW and a second power transistor MP_PW. The specific structure of the rectifier circuit 200 can be referred to below and shown in FIG. 4 , which will not be described in detail. The detection control circuit 300 includes: a voltage divider circuit 310 composed of a third resistor R ₃ and a fourth resistor R ₄ , a first comparator 320 , a second comparator 330 , a first pulse generation module 340 , and a second pulse generation module 350 , the logic control module 360 , and the drive module 370 . The specific structure of the first pulse generating module 340 can be referred to below and shown in FIG. 5 , which will not be described in detail.

In FIG. 3 , V _in represents the input voltage, V _OUT1 represents the first output voltage, and V _SW represents the voltage of the second terminal of the inductor L, ie the drain voltage of the first power transistor MN_PW and the drain voltage of the second power transistor MP_PW. SN represents the gate control signal of the first power transistor MN_PW, SP represents the gate control signal of the second power transistor MP_PW, which is sent by the driving module 370, and the driving module 370 receives the logic signal sent by the logic control module 360 to generate two control signal. TM1 represents the first pulse signal, TM2 represents the second pulse signal, D represents the external digital control signal, and NSN represents the inverted signal of the SN signal. H1 represents the first signal, H2 represents the second signal, H3 represents the third signal, C ₀ represents the output capacitance of the first output voltage, and _RL and _CL represent the load resistance and load capacitance of the second output voltage, respectively.

In FIG. 3 , the first end of the inductor L receives the input voltage V _in , and the second end of the inductor L is connected to the drain of the first power transistor MN_PW and the drain of the second power transistor MP_PW respectively; the gate of the first power transistor MN_PW The source of the first power transistor MN_PW is grounded; the gate of the second power transistor MP_PW is connected to the drive module 370; the source of the second power transistor MP_PW is connected to the rectifier unit 200, The source of the second power transistor MP_PW outputs the first output voltage V _OUT1 .

In the embodiment of the present invention, the first power transistor MN_PW and the second power transistor MP_PW are controlled to be turned on alternately to realize voltage conversion. The first power transistor MN_PW and the second power transistor MP_PW are not turned on at the same time, but may be turned off at the same time. That is, when the first power transistor MN_PW is turned on, the second power transistor MP_PW is turned off, and when the second power transistor MP_PW is turned on, the first power transistor MN_PW is turned off, or the first power transistor MN_PW and the second power transistor MP_PW are turned off at the same time. open.

In the embodiment of the present invention, as a preferred manner, the inductor L may be provided outside the chip, and other circuit parts may be integrated in the chip. In addition, in the embodiment of the present invention, the output circuit 100 in the DC/DC conversion circuit is a boost type, and the circuit in the embodiment of the present invention can also be applied to a structure in which the output circuit 100 is a step-down type. In this case, the output circuit The connection relationship between the inductor L, the first power transistor MN_PW, and the second power transistor MP_PW in 100 will be adjusted, and the specific connection relationship belongs to the prior art, and will not be described here.

Referring to FIG. 4 , a schematic structural diagram of a preferred rectifier circuit 200 in an embodiment of the present invention is shown. FIG. 4 includes: a first resistor R ₁ , a second resistor R ₂ , an operational amplifier 220 , a third power transistor MP0 , and a first inverter INV1 , wherein the first resistor R ₁ and the second resistor R ₂ form a Voltage sampling circuit 210 .

The source of the third power transistor MP0 is connected to the source of the second power transistor MN_PW, which is equivalent to receiving the first output voltage V _OUT1 ; the gate of the third power transistor MP0 is connected to the output end of the operational amplifier 220 and the first inverter The input terminals of INV1 are respectively connected; the drain of the third power transistor MP0 is connected to the first terminal of the _first resistor R1, and the drain of the third power transistor MP0 outputs the second output voltage V _OUT2 ; the second output voltage V _OUT2 available to the load. That is, the second output voltage V _OUT2 is the external output voltage of the DC/DC converter.

The second end of the first resistor R1 is connected to the _first end of the _second resistor R2 and the non-inverting end of the operational amplifier 220, and the voltage divider circuit formed by the _first resistor R1 and the _second resistor R2 is responsible for the second output voltage V _OUT2 divides the voltage to obtain the second feedback voltage V _FB2 , and the second feedback voltage V _FB2 is input as the non-inverting terminal of the operational amplifier 220 ; the second terminal of the second resistor R ₂ is grounded; the inverting terminal of the operational amplifier 220 receives the reference voltage V _REF ; The output end of the first inverter 220 is connected to the first pulse generation module 340 in the detection control unit, and the output end of the first inverter 220 outputs the first signal H1 to the first pulse generation module 340 .

In the embodiment of the present invention, the operational amplifier 220 obtains the error amplification voltage N1 based on the second feedback voltage V _FB2 and the reference voltage V _REF , and the gate of the third power transistor MP0 is controlled by the error amplification voltage N1 to adjust the magnitude of the second output voltage V _OUT2 The charging current suppresses the ripple of the second output voltage V _OUT2 . After simulation and actual measurement, the ripple amplitude of the second output voltage V _OUT2 of the rectifier circuit 200 is attenuated by about 50 times compared with the ripple amplitude of the first output voltage V _OUT1 , which is greatly reduced compared to the current traditional DC/DC converter. the second output voltage V _OUT2 ripple.

At the same time, the first inverter INV1 obtains the first signal H1 based on the error amplifying voltage N1 output by the operational amplifier 220, and the first signal H1 being at a high level indicates that the second output voltage V _OUT2 is equal to the reference voltage V _REF and the first ratio Product, the second output voltage V _OUT2 has been established, the first signal H1 is low level indicates that the second output voltage is lower than the product of the reference voltage V _REF and the first ratio, the second output voltage V _OUT2 has not been established. The first ratio is a design value, which is calculated according to the preset second output voltage V _OUT2 and the reference voltage V _REF .

3 , the detection control unit 300 includes: a third resistor R ₃ , a fourth resistor R ₄ , a first comparator 330 , a second comparator 320 , a first pulse generation module 340 , a second pulse generation module 350 , a logic control Module 360, driving module 370, second inverter INV2.

The first end of the third resistor R ₃ is connected to the non-inverting end of the first comparator 330 , and the first end of the third resistor R ₃ receives the first output voltage V _OUT1 ; that is, the non-inverting end of the first comparator 330 receives the first output voltage V OUT1 ; The first output voltage V _OUT1 .

The second end of the third resistor R ₃ is connected to the first end of the fourth resistor R ₄ and the non-inverting end of the second comparator 320 respectively; the second end of the fourth resistor R ₄ is grounded; the third resistor R ₃ , the fourth The resistor R ₄ forms another divided voltage 310 , which also divides the first output voltage V _OUT1 to obtain the first feedback voltage V _FB1 . The first feedback voltage V _FB1 is input as the non-inverting terminal of the second comparator 320 .

The inverting terminal of the first comparator 330 receives the voltage of the second terminal of the inductor L (represented by V _SW in FIG. 2 ); the output terminal of the first comparator 330 is connected to the input terminal of the logic control module 360 , and the first comparator 330 The output terminal of the output terminal outputs a third signal H3, and the third signal H3 represents the current flow between the second terminal of the inductor L and the source of the second power transistor MP_PW; that is, the third signal H3 represents the relationship between V _SW and V _OUT1 direction of current flow. When the third signal H3 is at a high level, it means that the current flow between V _SW and V _OUT1 is: from V _OUT1 to V _SW ; when the third signal H3 is at a low level, it means that the current flow between V _SW and V _OUT1 is: from V _SW flows to V _OUT1 .

The inverting terminal of the second comparator 320 receives the reference voltage V _REF ; the output terminal of the second comparator 320 is connected to the input terminal of the logic control module 360 , and the output terminal of the second comparator 320 outputs the second signal H2 , the second signal H2 represents the magnitude relationship between the first output voltage V _OUT1 and the reference voltage V _REF . The high level of the second signal H2 indicates that the first output voltage V _OUT1 is higher than the product of the reference voltage V _REF and the second ratio, and the third signal H2 is low level indicates that the first output voltage V _OUT1 is lower than the reference voltage V _REF and The product of the second ratio, wherein the second ratio is greater than the first ratio.

The output terminal of the logic control module 360 is connected to the input terminal of the driving module 370; the output terminal of the driving module 370 is connected to the gate of the first power transistor MN_PW, the gate of the second power transistor MP_PW, and the input terminal of the second inverter INV2 The input terminals of the second pulse generating module 350 are respectively connected, and the driving module 370 outputs the control signal based on the received logic signal of the logic control module 360, the gate control signal SN of the first power transistor MN_PW and the gate of the second power transistor MP_PW. pole control signal SP.

The output end of the second pulse generation module 350 is connected to the logic control module 360; the output end of the second inverter INV2 is connected to the first pulse generation module 340, which inverts the gate control signal SN of the first power transistor MN_PW to obtain The NSN signal is output to the first pulse generating module 340 .

Referring to FIG. 5 , a schematic structural diagram of a preferred first pulse generating module 340 in an embodiment of the present invention is shown. FIG. 5 includes: storage capacitor array 341, first common transistor MN1, third comparator 342; first end of storage capacitor array 341 (V _RAMP in FIG. 5 ) and charging current source ( _IB in FIG. 5 ) , the non-inverting end of the third comparator 342 and the drain of the first common transistor MN1 are respectively connected; the second end of the energy storage capacitor array 341 receives the first signal H1 and the external digital control signal D[2:0]; the energy storage capacitor The third end of the array 341 is connected to the source of the first common transistor MN1 and grounded; the gate of the first common transistor MN1 is connected to the output end of the second inverter INV2, that is, the gate of the first common transistor MN1 receives NSN signal.

The inverting terminal of the third comparator 342 receives the reference voltage V _REF ; the output terminal of the third comparator 342 is connected to the logic control module 360 , and the output terminal of the third comparator 342 outputs the first pulse signal TM1 .

Specifically, the energy storage capacitor array 341 includes: a second common transistor MN2, a third common transistor MN3, a fourth common transistor MN4, a fifth common transistor MN5, a first capacitor C ₁ , a second capacitor C ₂ , and a third capacitor C _3. The fourth capacitor C ₄ , the fifth capacitor C ₅ , the first OR gate OR1, the second OR gate OR2, and the third OR gate OR3.

The drain stages of the second common transistor MN2, the third common transistor MN3, the fourth common transistor MN4, and the fifth common transistor MN5 are all connected with the charging current source _IB , the non-inverting terminal of the third comparator 342, and the first common transistor MN1. The drain of , and the first end of the fifth capacitor _C5 are respectively connected. The voltage on the respective drains of the second common transistor MN2, the third common transistor MN3, the fourth common transistor MN4, and the fifth common transistor MN5 is V _RAMP .

The gate of the second ordinary transistor MN2 is connected to the first input terminal of the first OR gate OR1, the first input terminal of the second OR gate OR2, the first input terminal of the third OR gate OR3, and the output of the first inverter INV1 The terminals are respectively connected to receive the first signal H1; the source of the second ordinary transistor MN2 is connected to the first terminal of the first capacitor _{C1 ;} the second terminal of the first capacitor C1, the _second terminal of the second capacitor C2, The second end of the _third capacitor C3, the second end of the fourth capacitor _C4 , the second end of the fifth capacitor _C5 , and the source of the first common transistor MN1 are respectively connected and grounded. The gate of the third ordinary transistor MN3 is connected to the output terminal of the first OR gate OR1; the gate of the fourth ordinary transistor MN4 is connected to the output terminal of the second OR gate OR2; the gate of the fifth ordinary transistor MN5 is connected to the third OR gate The output of gate OR3 is connected.

The second input terminal of the first OR gate OR1 receives the first digital control signal D[2] in the external digital control signal D[2:0]; the second input terminal of the second OR gate OR2 receives the external digital control signal D[ 2:0] in the second digital control signal D[1]; the second input terminal of the third OR gate OR3 receives the third digital control signal D[0] in the external digital control signal D[2:0].

5, the width of the first pulse signal TM1 is a function of the charging current source _IB and the effective capacitance value of the energy storage capacitor array 341, wherein the effective capacitance value of the energy storage capacitor array 341 is controlled by the external digital control signal D[2:0] and the first signal H1 control. The first pulse signal TM1 is used to control the on-time of the first power transistor MN_PW, thereby controlling the charging current for the first output voltage V _OUT1 . When the entire conversion current works in the accelerated charging mode, the capacitance value of the energy storage capacitor array 341 is configured to be the preset maximum value. At this time, the pulse width of the first pulse signal TM1 output by the first pulse generation module 340 is the widest. A power transistor MN_PW conducts the longest time and charges the first output voltage V _OUT1 with the maximum current, that is, the first output voltage V _OUT1 is increased with the highest allowable charging current. When the entire conversion current works in other modes, the capacitance value of the energy storage capacitor array 341 is determined by the external digital control signal D[2:0]. At this time, the width of the first pulse signal TM1 output by the first pulse generation module 340 is also Determined by an external digital control signal D[2:0], it charges the first output voltage V _OUT1 with a corresponding current.

The charging current source _IB provides a reference current to charge the energy storage capacitor array 341; the first ordinary transistor MN1 charges the energy storage capacitor array 341 according to the inverted signal NSN of the gate control signal SN of the first power transistor MN_PW when NSN is at a high level. The upper plate voltage V _RAMP of the array 341 (ie the voltage at the first end of the storage capacitor array 341 ) is rapidly discharged to zero level; the third comparator 342 compares the upper plate voltage V _RAMP of the storage capacitor array with the reference voltage V _REF to obtain The first pulse signal TM1. When the upper plate voltage V _RAMP of the energy storage capacitor array 341 is greater than the reference voltage V _REF , the first pulse signal TM1 is at a high level, and the first power transistor MN_PW is turned off; when the upper plate voltage V _RAMP of the energy storage capacitor array 341 is at a high level When the voltage is lower than the reference voltage V _REF , the first pulse signal TM1 is at a low level, and the first power transistor MN_PW is turned on.

In the embodiment of the present invention, the second pulse generation module 350 is similar in structure to the first pulse generation module 340, but the size of the storage capacitor in the storage capacitor array is fixed, and the storage capacitor is charged by the charging current source _IB to generate a specified width The second pulse signal TM2 is not shown separately because of its similar structure.

The width of the second pulse signal TM2 is a function of the charging current source _IB and the storage capacitor. The second pulse generating module 350 is configured to limit the time when the first power transistor MN_PW and the second power transistor MP_PW are turned off at the same time, and the time when the second power transistor MP_PW is turned on, the first power transistor MN_PW and the second power transistor MP_PW are turned off at the same time After the off time or the on time of the second power transistor MP_PW exceeds the width of the second pulse signal TM2, the switching operation of this cycle is restarted to avoid the state lock of the entire DC/DC conversion circuit due to insufficient charging current or heavy load.

In the embodiment of the present invention, the logic control module 360 receives various signals to determine the working state of the DC/DC converter. Various signals include: a third signal H3, a second signal H2, a first pulse signal TM1, and a second pulse signal TM2. The logic control module 360 generates control logic that the detection control circuit 300 wishes to implement according to various signals. Since the driving of the power transistor requires a higher voltage, a driving circuit 370 is designed. The driving circuit 370 receives the logic signal generated by the logic control module 360 and boosts it to generate the gate control signal SN of the first power transistor MN_PW to generate The gate control signal of the second power transistor MP_PW drives the signal SP. The second inverter is used to generate an inversion signal NSN, and the inversion signal NSN is used to control the turn-on and turn-off of the first common transistor MN1 in the first pulse generating module 340 .

Combining the above structure, with reference to Figure 3, Figure 4, and Figure 5, the working principle of the DC/DC conversion circuit according to the embodiment of the present invention is as follows:

When the duty cycle of the DC/DC conversion circuit starts, the first power transistor MN_PW and the second power transistor MP_PW are both turned off, and the second comparator 320 compares the first feedback voltage V _FB1 with the reference voltage V _REF , if the first feedback voltage V REF _FB1 is lower than the reference voltage V _REF , and the second signal H2 output by the second comparator 320 is at a low level, indicating that the first output voltage V _OUT1 is not higher than the product of the reference voltage V _REF and the second ratio, and it is necessary to continue to measure the first output voltage V OUT1 . The output voltage V _OUT1 is charged. At this time, the logic control module 360 controls the first common transistor MN1 of the first pulse generation module 340 to turn off, and the charging current source _IB charges the upper plate V _RAMP of the energy storage capacitor array 341. When the plate voltage V _RAMP is lower than the reference voltage V _REF , the first pulse signal TM1 output by the third comparator 342 is at a low level. During the period when the first pulse signal TM1 is at a low level, the first power transistor MN_PW is turned on, and the first pulse signal TM1 is turned on. Two power transistors MP_PW are turned off. The time that the first pulse signal TM1 remains low is about:

Wherein, C _T is the capacitance value of the energy storage capacitor array 341 . When the second feedback voltage V _FB2 in the rectifier circuit 200 is much lower than the reference voltage V _REF , the potential of the output node N1 of the operational amplifier 220 is close to zero, the third power transistor MP0 is fully turned on, and the second output voltage V _OUT2 and the first output The voltages V _OUT1 are approximately equal. The potential of the output node N1 of the operational amplifier 220 is lower than the threshold V _T of the first inverter INV1 , and the first signal H1 output by the first inverter INV1 is at a high level, indicating that the second output voltage V _OUT2 is not higher than the reference voltage The product of V _REF and the first ratio requires accelerated charging to shorten the settling time of the second output voltage V _OUT2 . At this time, the DC/DC conversion circuit operates in the accelerated charging mode. At this time, the second common transistor MN2, the third common transistor MN3, the fourth common transistor MN4, and the fifth common transistor MN5 in the energy storage capacitor array 341 are all turned on, and the capacitance value of the energy storage capacitor array 341 is the maximum capacitance value C _Tmax :

C _Tmax =C ₁ +C ₂ +C ₃ +C ₄ +C ₅

Wherein, C ₁ , C ₂ , C ₃ , C ₄ , and C ₅ are the respective capacitances of the first capacitor C ₁ , the second capacitor C ₂ , the third capacitor C ₃ , the fourth capacitor C ₄ , and the fifth capacitor C ₅ . value. The second common transistor MN2, the third common transistor MN3, the fourth common transistor MN4, and the fifth common transistor MN5 are all turned on, and the first pulse signal TM1 is at a low level for the longest time; when the second feedback voltage of the rectifier circuit 200 When V _FB2 is close to the reference voltage V _REF , when the potential of the output node N1 of the operational amplifier 220 rises and is higher than the threshold VT of the first inverter _INV1 , the first signal H1 output by the first inverter INV1 jumps from a high level When it becomes a low level, it indicates that the second output voltage V _OUT2 has been established, and no accelerated charging is required, and the DC/DC conversion circuit enters the normal charging mode. At this time, the second common transistor MN2 is turned off, and the turn-on or turn-off of the third common transistor MN3, the fourth common transistor MN4, and the fifth common transistor MN5 is determined by the external digital control signal D[2:0], and the energy storage capacitor The capacitance value C _T of the array 341 is also determined by the external digital control signal D[2:0], and the corresponding turn-on time of the first power transistor MN_PW is also determined by the external digital control signal D[2:0].

When the upper plate voltage V _RAMP of the energy storage capacitor array 341 is higher than V _REF , the first pulse signal TM1 output by the third comparator 342 changes from a low level to a high level. At this time, the first power transistor MN_PW, the first pulse signal TM1 The two power transistors MP_PW are both turned off, and the second pulse signal TM2 output by the second pulse generating module 350 changes from a high level to a low level. During the period when the second pulse signal TM2 is at a low level, if the third signal H3 output by the first comparator 330 is at a high level, it means that the voltage of V _SW is lower than the first output voltage V _OUT1 and cannot pass through the second power transistor MP_PW charges the first output voltage V _OUT1 , at this time the first power transistor MN_PW and the second power transistor MP_PW are both kept off to wait for V _SW to rise; when the second pulse signal TM2 changes from a low level to a high level , if the third signal H3 is still at a high level, it means that the on-time of the first power transistor MN_PW is too short and the charging current is too small. A power transistor MN_PW until V _SW is higher than the first output voltage V _OUT1 when both the first power transistor MN_PW and the second power transistor MP_PW remain off.

During the period when the second pulse signal TM2 is at a low level, if the third signal H3 changes from a high level to a low level, it means that the V _SW voltage is higher than the first output voltage V _OUT1 , and the first power transistor MN_PW is turned off at this time , the second power transistor MP_PW is turned on, and V _SW charges the first output voltage V _OUT1 .

During the period when the second pulse signal TM2 is at a low level, if the third signal H3 changes from a low level to a high level, it means that the charging of the first output voltage V _OUT1 is completed. At this time, the first power transistor MN_PW and the second power transistor MN_PW and the second The power transistors MP_PW are all turned off, the logic control module 360 controls the first common transistor MN1 in the first pulse generation module 340 to be turned on, the voltage of the V _RAMP node on the upper plate of the energy storage capacitor array 341 is reset to zero, and the DC/DC conversion circuit When the work cycle ends, enter the next work cycle.

If the second pulse signal TM2 changes from a low level to a high level during the period when the third signal H3 is at a low level, it indicates that the load is relatively heavy, and the normal charging mode can no longer drive such a heavy load, and the DC/DC conversion circuit Enter the continuous working mode, forcibly turn off the first power transistor MN_PW and the second power transistor MP_PW, the logic control module 360 controls the first common transistor MN1 in the first pulse generating module 340 to conduct, and the upper plate V _RAMP of the energy storage capacitor array 341 The node voltage is reset to zero, the working cycle of the DC/DC conversion circuit ends, and the next working cycle is entered.

If the first feedback voltage V _FB1 in the rectifier circuit 200 is higher than the reference voltage V _REF at the beginning of the working cycle of the DC/DC conversion circuit, the second signal H2 output by the second comparator 320 is at a high level, indicating that the first output The voltage V _OUT1 is already higher than the product of the reference voltage V _REF and the second ratio, and there is no need to charge the first output voltage V _OUT1 . At this time, the DC/DC conversion circuit enters the sleep mode, and the first power transistor MN_PW and the second power transistor MP_PW Both remain disconnected until the second signal H2 output from the second comparator 320 transitions from a high level to a low level. In the sleep mode, only a few components in the second comparator 320 and the rectifier circuit 200 in FIG. 2 are working, and the rest of the components are turned off, so the current of the DC/DC conversion circuit is very low in the sleep mode , after testing the current of the entire DC/DC conversion circuit can be as low as around 5uA.

Referring to FIG. 6 , a schematic waveform diagram of a DC/DC conversion circuit in an embodiment of the present invention is shown. When the second output voltage V _OUT2 does not rise above the product of the reference voltage V _REF and the first ratio, the DC/DC conversion circuit enters the accelerated charging mode, the first power transistor MN_PW conducts for the longest time, and the current flowing through the inductor L The charging current _IL is the largest. When the charging current IL of the inductor _L drops to 0, the second power transistor MP_PW is turned off and enters the next working cycle. In the accelerated charging mode, the first output voltage V _OUT1 rises faster; When the output voltage V _OUT2 is higher than the product of the reference voltage V _REF and the first ratio, but the first output voltage V _OUT1 is not higher than the product of the reference voltage V _REF and the second ratio, the DC/DC conversion circuit enters the normal charging mode, The conduction time of the first power transistor MN_PW is determined by the external digital control signal, and the charging current IL flowing through the inductor _L is also determined by the external digital control signal. When the charging current IL of the inductor _L drops to 0, the second power transistor MP_PW It is disconnected to enter the next working cycle. In the normal charging mode, the first output voltage V _OUT1 rises at a set rate, so as to avoid a large voltage ripple in the steady state due to an excessively fast boost rate. When the first output voltage V _OUT1 is higher than the product of the reference voltage V _REF and the second ratio, the DC/DC conversion circuit enters the sleep mode, the first power transistor MN_PW and the second power transistor MP_PW are both turned off, and the inductor L charges the current I _L is zero, thereby reducing the quiescent operating current until the first output voltage V _OUT1 falls below the product of the reference voltage V _REF and the second ratio, and the DC/DC conversion circuit enters the normal charging mode again.

Based on the above DC/DC conversion circuit, an embodiment of the present invention further provides a DC/DC converter, where the DC/DC converter includes: the DC/DC conversion circuit described above.

To sum up, in the DC/DC conversion circuit of the embodiment of the present invention, the output unit receives the input voltage, and outputs a first output voltage higher than the input voltage to the rectifier unit and the detection control unit, and the rectifier unit rectifies and filters the first output voltage, The ripple of the first output voltage is reduced, and a second output voltage with low ripple is output. At the same time, the rectifier unit generates a first signal indicating whether the establishment of the second output voltage is completed, and transmits it to the detection control unit, and the detection control unit receives the first signal. After a signal and the first output voltage, a control signal is generated to control the DC/DC conversion circuit to work in an accelerated charging mode, or in a normal charging mode, or in a sleep mode. Among them, when the DC/DC conversion circuit works in the accelerated charging mode, the entire circuit increases the first output voltage with the highest allowable charging current, so that the first output voltage is quickly established, which is equivalent to the second output voltage being rapidly increased Compared with the current traditional DC/DC conversion circuit, it shortens the time for the output voltage to establish. The detection control unit can switch between the accelerated charging mode and the normal charging mode based on the first signal and the first output voltage. In the accelerated charging mode, the charging current is large to shorten the output voltage settling time. Output current and ensure low output ripple, improve the noise performance of the sensor, and the power consumption of the DC/DC conversion circuit is extremely small in sleep mode. The DC/DC conversion circuit of the present invention reduces the output voltage ripple and shortens the settling time of the output voltage of the DC/DC converter, which has high practical value.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The embodiments of the present invention have been described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific embodiments, which are merely illustrative rather than restrictive. Under the inspiration of the present invention, without departing from the scope of protection of the present invention and the claims, many forms can be made, which all belong to the protection of the present invention.

Claims (10)

1. A DC/DC conversion circuit, characterized in that the circuit comprises: an output unit, a rectifier unit, and a detection control unit; the output unit receives an input voltage, and outputs a first output voltage to the rectification unit and the detection control unit, where the first output voltage is higher than the input voltage; The rectifying unit rectifies and filters the first output voltage, outputs a second output voltage, and generates a first signal and transmits it to the detection control unit, where the first signal represents whether the establishment of the second output voltage is completed ; The detection control unit receives the first signal and the first output voltage, and generates a control signal to control the DC/DC conversion circuit to work in an accelerated charging mode, or in a normal charging mode, or in a sleep mode ; Wherein, the accelerated charging mode is: a mode in which the first output voltage is increased with the highest allowable charging current; The normal charging mode is: a mode in which the first output voltage is increased by a preset charging current; The sleep mode is a mode in which the raising of the first output voltage is stopped until the first output voltage drops below a reference voltage. 2. The circuit according to claim 1, wherein the output unit comprises: an inductor, a first power transistor and a second power transistor; The first end of the inductor receives the input voltage, and the second end of the inductor is connected to the drain of the first power transistor and the drain of the second power crystal, respectively; The gate of the first power transistor is connected to the driving module in the detection control unit; the source of the first power transistor is grounded; the gate of the second power transistor is connected to the driving module; The source of the second power transistor is connected to the rectifying unit, and the source of the second power transistor outputs the first output voltage. 3. The circuit according to claim 2, wherein the rectifier unit comprises: a third power transistor, a first resistor, a second resistor, a first inverter, and an operational amplifier; the source of the third power transistor is connected to the source of the second power transistor; The gate of the third power transistor is connected to the output end of the operational amplifier and the input end of the first inverter respectively; The drain of the third power transistor is connected to the first end of the first resistor, and the drain of the third power transistor outputs the second output voltage; The second end of the first resistor is connected to the first end of the second resistor and the non-inverting end of the operational amplifier; the second end of the second resistor is grounded; an inverting terminal of the operational amplifier receives the reference voltage; The output end of the first inverter is connected to the first pulse generating module in the detection control unit, and the output end of the first inverter outputs the first signal. 4. The circuit according to claim 3, wherein the detection control unit comprises: a third resistor, a fourth resistor, a first comparator, a second comparator, a second pulse generation module, a logic control module, the second inverter; The first end of the third resistor is connected to the non-inverting end of the first comparator, and the first end of the third resistor receives the first output voltage; The second end of the third resistor is connected to the first end of the fourth resistor and the non-inverting end of the second comparator respectively; the second end of the fourth resistor is grounded; the inverting terminal of the first comparator receives the voltage of the second terminal of the inductor; The output end of the first comparator is connected to the input end of the logic control module, and the output end of the first comparator outputs a third signal, and the third signal represents the second end of the inductance, and is connected to the second end of the inductor. the current flow between the sources of the second power transistor; an inverting terminal of the second comparator receives the reference voltage; The output end of the second comparator is connected to the input end of the logic control module, the output end of the second comparator outputs a second signal, and the second signal represents the first output voltage and the reference The magnitude relationship between the voltages; The output end of the logic control module is connected with the input end of the driving module; The output end of the driving module is respectively the gate of the first power transistor, the gate of the second power transistor, the input end of the second inverter, and the input end of the second pulse generating module. connected, the drive module outputs the control signal; The output end of the second pulse generating module is connected with the logic control module; The output end of the second inverter is connected to the first pulse generating module. 5 . The circuit according to claim 4 , wherein: the first pulse generating module comprises: an energy storage capacitor array, a first common transistor, and a third comparator; 5 . The first end of the energy storage capacitor array is respectively connected to the charging current source, the non-inverting end of the third comparator, and the drain of the first common transistor; The second end of the energy storage capacitor array receives the first signal and the external digital control signal; The third end of the energy storage capacitor array is connected to the source of the first common transistor and grounded; the gate of the first common transistor is connected to the output end of the second inverter; an inverting terminal of the third comparator receives the reference voltage; The output end of the third comparator is connected to the logic control module, and the output end of the third comparator outputs the first pulse signal. 6. The circuit according to claim 5, wherein the energy storage capacitor array comprises: a second common transistor, a third common transistor, a fourth common transistor, a fifth common transistor, a first capacitor, a second capacitor , the third capacitor, the fourth capacitor, the fifth capacitor, the first OR gate, the second OR gate, the third OR gate; The drain stages of the second common transistor, the third common transistor, the fourth common transistor, and the fifth common transistor are all connected with the charging current source, the non-inverting terminal of the third comparator, The drain of the first common transistor and the first end of the fifth capacitor are respectively connected; The gate of the second ordinary transistor and the first input terminal of the first OR gate, the first input terminal of the second OR gate, the first input terminal of the third OR gate, the first input terminal of the The output ends of the inverters are respectively connected; the source of the second common transistor is connected to the first end of the first capacitor; the second end of the first capacitor, the second end of the second capacitor, the second end of the third capacitor, the second end of the fourth capacitor, the second end of the fifth capacitor, The sources of the first common transistors are respectively connected and grounded; the gate of the third common transistor is connected to the output end of the first OR gate; the gate of the fourth common transistor is connected to the output end of the second OR gate; the gate of the fifth common transistor is connected to the output end of the third OR gate; the second input terminal of the first OR gate receives the first digital control signal in the external digital control signal; the second input terminal of the second OR gate receives the second digital control signal in the external digital control signal; The second input terminal of the third OR gate receives a third digital control signal of the external digital control signals. 7 . The circuit according to claim 4 , wherein the first signal is at a high level to indicate that the second output voltage is established, and the first signal is at a low level to indicate the second output voltage. 8 . not completed; The high level of the third signal indicates that the second terminal of the inductor and the source of the second power transistor flow in the direction of: from the source of the second power transistor to the source of the inductor. second end; The low level of the third signal indicates the second terminal of the inductor, and the current flow between the second terminal of the inductor and the source of the second power transistor is: from the second terminal of the inductor to the second power transistor the source; The high level of the second signal indicates that the first output voltage is higher than the reference voltage, and the low level of the second signal indicates that the first output voltage is lower than the reference voltage. 8 . The circuit according to claim 7 , wherein the standard for completing the establishment of the second output voltage is: the magnitude of the second output voltage is equal to the product of the reference voltage and the first ratio; 9 . The criterion that the second output voltage is not established is: the magnitude of the second output voltage is smaller than the product of the reference voltage and the first ratio; The criterion that the first output voltage is higher than the reference voltage is: the magnitude of the first output voltage is greater than the product of the reference voltage and a second ratio, wherein the second ratio is greater than the first ratio; The criterion that the first output voltage is lower than the reference voltage is that the magnitude of the first output voltage is not greater than the product of the reference voltage and the second ratio. 9 . The circuit according to claim 6 , wherein when the first signal is at a high level, the second common transistor, the third common transistor, the fourth common transistor, the fifth common transistor, and the fifth The common transistors are all turned on, the capacitance value of the energy storage capacitor array is a preset maximum capacitance value, and the first pulse signal maintains a low level for the longest time; When the first signal is at a low level, the second common transistor is turned off, the third common transistor, the fourth common transistor, and the fifth common transistor are controlled by the external digital control signal, so The capacitance value of the energy storage capacitor array is determined by the external digital control signal, and the duration that the first pulse signal remains at a low level is determined by the external digital control signal. 10. A DC/DC converter, characterized in that the DC/DC converter comprises: the circuit according to any one of claims 1-9.

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