CN113225076A - Frequency synthesizer - Google Patents
Frequency synthesizer Download PDFInfo
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- CN113225076A CN113225076A CN202110537821.9A CN202110537821A CN113225076A CN 113225076 A CN113225076 A CN 113225076A CN 202110537821 A CN202110537821 A CN 202110537821A CN 113225076 A CN113225076 A CN 113225076A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
本发明公开一种频率综合器，包括鉴相器、电荷泵、压控振荡单元、分频器、自动频率控制器、电压比较电路、重锁控制电路、频率稳定检测电路；所述鉴相器的第一输入端与所述压控振荡单元的输出端电连接，所述鉴相器的第二输入端与参考频率输入端电连接，所述鉴相器的输出端与所述电荷泵的输入端电连接，所述电荷泵的输出端与所述压控振荡单元的输入端电连接。采用本发明的技术方案，可以减小频率综合器的功耗。
The invention discloses a frequency synthesizer, comprising a phase detector, a charge pump, a voltage-controlled oscillation unit, a frequency divider, an automatic frequency controller, a voltage comparison circuit, a relock control circuit, and a frequency stability detection circuit; the phase detector The first input terminal of the phase detector is electrically connected to the output terminal of the voltage-controlled oscillation unit, the second input terminal of the phase detector is electrically connected to the reference frequency input terminal, and the output terminal of the phase detector is electrically connected to the output terminal of the charge pump. The input terminal is electrically connected, and the output terminal of the charge pump is electrically connected to the input terminal of the voltage-controlled oscillation unit. By adopting the technical scheme of the present invention, the power consumption of the frequency synthesizer can be reduced.
Description
Technical Field
The invention belongs to the technical field of frequency synthesis, and particularly relates to a frequency synthesizer.
Background
A frequency synthesizer is an indispensable essential element in radio frequency circuits. However, there is a contradiction between the noise performance and the frequency tuning range of the frequency synthesizer. When the frequency tuning range is relatively large, the tuning gain of a Voltage-Controlled Oscillator (VCO) in the frequency synthesizer is very large, so that the VCO is sensitive to noise, the overall noise performance of the frequency synthesizer is deteriorated, and the requirements of customers cannot be met. In addition, when the frequency tuning range of the frequency synthesizer is large, the capacitor array of the VCO is large, so that the VCO needs a large oscillation starting current to start oscillation, the power consumption of the VCO can be increased, and the power consumption of the frequency synthesizer is further increased.
Disclosure of Invention
The invention aims to provide a frequency synthesizer, which can reduce the power consumption of the frequency synthesizer.
In order to achieve the purpose, the invention adopts the following technical scheme:
a frequency synthesizer comprises a phase discriminator, a charge pump, a voltage-controlled oscillation unit, a frequency divider, an automatic frequency controller, a voltage comparison circuit, a relock control circuit and a frequency stability detection circuit; the first input end of the phase discriminator is electrically connected with the output end of the voltage-controlled oscillation unit, the second input end of the phase discriminator is electrically connected with the reference frequency input end, the output end of the phase discriminator is electrically connected with the input end of the charge pump, and the output end of the charge pump is electrically connected with the input end of the voltage-controlled oscillation unit; the phase discriminator is used for comparing the phases of the reference clock and the feedback clock of the voltage-controlled oscillator; when the phase of the feedback clock lags behind the phase of the reference clock, the phase discriminator outputs a pulse signal UP signal for increasing the frequency;
the automatic frequency controller comprises a counter, a timing circuit, a comparator and a logic control circuit, wherein the input end of the counter is connected with the other output end of the frequency divider, the input end of the timing circuit is connected with a reference signal, the output end of the timing circuit is connected with the counter and provides a periodic signal for the counter, the output end of the counter is connected with the input end of the comparator, the output end of the comparator is connected with the input end of the logic control circuit, and the output end of the logic control circuit outputs a control signal for controlling a switch capacitor array control word of the voltage-controlled oscillator when the phase-locked loop frequency synthesizer is in an open-loop frequency coarse adjustment stage so as to adjust the output frequency of the voltage-controlled oscillator;
the voltage comparison circuit judges whether the tuning voltage Vtune output to the voltage-controlled oscillator by the low-pass loop filter is in a preset voltage range in real time when the frequency synthesizer is in the phase of phase-locked loop loss detection, and the relock control circuit dynamically adjusts the value of a control word of a switch capacitor array of the voltage-controlled oscillator according to the comparison result of the voltage comparison circuit; when the tuning voltage Vtune is within a preset voltage range, the relocking control circuit does not work, when the tuning voltage Vtune is larger than the preset voltage range, the relocking control circuit controls the value of the switch capacitor array control word of the voltage-controlled oscillator to increase or decrease by one unit, and when the tuning voltage Vtune is smaller than the preset voltage range, the relocking control circuit controls the value of the switch capacitor array control word of the voltage-controlled oscillator to decrease or increase by one unit;
the frequency stability detection circuit is used for detecting whether the frequency of a reference signal and the frequency of a feedback signal of the voltage-controlled oscillator after frequency division by the frequency divider are stable or not before the frequency synthesizer enters an open-loop coarse adjustment stage, and sending a control signal after the frequency of the reference signal and the frequency of the feedback signal are both stable, so that the phase-locked loop frequency synthesizer starts a coarse tuning loop and enters the open-loop coarse adjustment stage, wherein the voltage-controlled oscillator is provided with a fixed control voltage in the process from starting to entering the open-loop coarse adjustment stage.
Preferably, the phase detector comprises two resettable DFFs; when the UP signal and the DOWN signal are both high, at least one of the two DFFs (D-type flip-flops) is delayed, causing both DFFs to be reset; when a PLL (Phase Locked Loop) is in lock, the Phase detector operates in the linear region.
Preferably, the phase detector comprises at least one delay driving unit connected to one of the two DFFs; and the delay driving unit drives the DFF connected with the delay driving unit to delay when the UP signal and the DOWN signal are both high.
Preferably, the frequency tuning gains of at least two of the voltage controlled oscillators are equal.
Preferably, the voltage controlled oscillator comprises a CMOS LC oscillator.
Preferably, the system also comprises a frequency divider; the phase discriminator and the voltage-controlled oscillation unit are electrically connected through the frequency divider; the input end of the frequency divider is electrically connected with the output end of the voltage-controlled oscillation unit, and the first output end of the frequency divider is electrically connected with the first input end of the phase discriminator; the frequency divider is used for dividing frequency according to the frequency output by the voltage-controlled oscillation unit.
Preferably, the system further comprises a loop filter; the charge pump is electrically connected with the voltage-controlled oscillation unit through the loop filter; the input end of the loop filter is electrically connected with the output end of the charge pump, and the output end of the loop filter is electrically connected with the input end of the voltage-controlled oscillation unit; the loop filter is used for filtering the signal output by the charge pump.
Preferably, the system also comprises a frequency pre-adjusting unit; a first input end of the frequency pre-adjusting unit is electrically connected with a second output end of the frequency divider, a second input end of the frequency pre-adjusting unit is electrically connected with a preset frequency input end, and an output end of the frequency pre-adjusting unit is electrically connected with a pre-adjusting input end of the voltage-controlled oscillator; the frequency pre-adjusting unit is used for adjusting the frequency of the voltage-controlled oscillator by adopting a dichotomy.
According to the invention, the voltage-controlled oscillation unit is arranged in the frequency synthesizer, when the frequency synthesizer works, one voltage-controlled oscillator can be selected to work according to the tuning frequency of the frequency synthesizer, so that the frequency tuning range of the voltage-controlled oscillation unit is increased on the basis of not increasing the tuning gain of the voltage-controlled oscillator, the frequency tuning range of the frequency synthesizer is increased on the basis of not reducing the noise performance of the frequency synthesizer, and the use range of the frequency synthesizer is increased. In addition, the tuning gain of the voltage-controlled oscillator is smaller, so that a capacitor array in the voltage-controlled oscillator is smaller, and the parasitic resistance of the voltage-controlled oscillator is smaller, so that the power consumption of the voltage-controlled oscillator can be reduced, and the power consumption of the frequency synthesizer is further reduced. While DFF1 and DFF2 experience different delays being reset when both the UP and DOWN signals are high. In this way, the input-output curve is shifted down (or up) so that the phase detector operates in the linear region when the PLL is in lock. Thus, the present invention can improve the in-band phase noise and spurs of the PLL. Whether the phase-locked loop is unlocked or not is judged by setting an analog circuit to detect the tuning voltage Vtune of the voltage-controlled oscillator, so that the increase of reference harmonic energy is avoided, and the interference is reduced; and a frequency stability detection circuit is arranged to detect whether the reference clock and the feedback clock are stable before the open loop coarse adjustment is carried out, so that the failure of the open loop coarse adjustment is avoided, and the coarse adjustment time is greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a frequency synthesizer according to the present invention.
Detailed Description
The present invention will be described in detail with reference to the following embodiments, wherein like or similar elements are designated by like reference numerals throughout the several views, and wherein the shape, thickness or height of the various elements may be expanded or reduced in practice. The examples are given solely for the purpose of illustration and are not intended to limit the scope of the invention. Any obvious modifications or variations can be made to the present invention without departing from the spirit or scope of the present invention.
As shown in fig. 1, the present invention provides a frequency synthesizer, which includes a phase discriminator, a charge pump, a voltage-controlled oscillation unit, a frequency divider, an automatic frequency controller, a voltage comparison circuit, a relock control circuit, and a frequency stability detection circuit; the first input end of the phase discriminator is electrically connected with the output end of the voltage-controlled oscillation unit, the second input end of the phase discriminator is electrically connected with the reference frequency input end, the output end of the phase discriminator is electrically connected with the input end of the charge pump, and the output end of the charge pump is electrically connected with the input end of the voltage-controlled oscillation unit; the voltage-controlled oscillation unit comprises at least two voltage-controlled oscillators; at least two of the voltage-controlled oscillators are connected in parallel; the minimum tuning frequency in the frequency tuning range of the voltage-controlled oscillator is less than the minimum tuning frequency in the frequency tuning range of another voltage-controlled oscillator, and the maximum tuning frequency in the frequency tuning range of one voltage-controlled oscillator is greater than or equal to the minimum tuning frequency in the frequency tuning range of another voltage-controlled oscillator.
The automatic frequency controller comprises a counter, a timing circuit, a comparator and a logic control circuit, wherein the input end of the counter is connected with the other output end of the frequency divider, the input end of the timing circuit is connected with a reference signal, the output end of the timing circuit is connected with the counter and provides a periodic signal for the counter, the output end of the counter is connected with the input end of the comparator, the output end of the comparator is connected with the input end of the logic control circuit, and the output end of the logic control circuit outputs a control signal for controlling a switch capacitor array control word of the voltage-controlled oscillator when the phase-locked loop frequency synthesizer is in an open-loop frequency coarse adjustment stage so as to adjust the output frequency of the voltage-controlled oscillator;
the voltage comparison circuit judges whether the tuning voltage Vtune output to the voltage-controlled oscillator by the low-pass loop filter is in a preset voltage range in real time when the frequency synthesizer is in the phase of phase-locked loop loss detection, and the relock control circuit dynamically adjusts the value of a control word of a switch capacitor array of the voltage-controlled oscillator according to the comparison result of the voltage comparison circuit; when the tuning voltage Vtune is within a preset voltage range, the relocking control circuit does not work, when the tuning voltage Vtune is larger than the preset voltage range, the relocking control circuit controls the value of the switch capacitor array control word of the voltage-controlled oscillator to increase or decrease by one unit, and when the tuning voltage Vtune is smaller than the preset voltage range, the relocking control circuit controls the value of the switch capacitor array control word of the voltage-controlled oscillator to decrease or increase by one unit;
the frequency stability detection circuit is used for detecting whether the frequency of a reference signal and the frequency of a feedback signal of the voltage-controlled oscillator after frequency division by the frequency divider are stable before the frequency synthesizer enters an open-loop coarse adjustment stage, and sending a control signal after the frequency of the reference signal and the frequency of the feedback signal are both stable, so that the phase-locked loop frequency synthesizer starts a coarse tuning loop and enters the open-loop coarse adjustment stage, wherein the voltage-controlled oscillator is provided with a fixed control voltage in the process from starting to entering the open-loop coarse adjustment stage.
Further, the minimum tuning frequency in the frequency tuning range of the voltage-controlled oscillator is smaller than the minimum tuning frequency of another voltage-controlled oscillator, and the maximum tuning frequency in the frequency tuning range of one voltage-controlled oscillator is larger than the minimum tuning frequency of another voltage-controlled oscillator.
Further, the phase discriminator is used for comparing the phases of the reference clock and the feedback clock of the voltage-controlled oscillator; when the phase of the feedback clock lags behind the phase of the reference clock, the phase discriminator outputs a pulse signal UP signal for increasing the frequency; when the phase of the feedback clock exceeds the phase of the reference clock, the phase discriminator outputs a pulse signal DOWN signal for reducing the frequency; the phase detector comprises two resettable DFFs (D-type flip-flops); when the UP signal and the DOWN signal are both high, at least one of the two DFFs is delayed, so that the two DFFs are reset; when a PLL (Phase Locked Loop) is in lock, the Phase detector operates in the linear region.
Further, the phase detector further comprises at least one delay driving unit connected to one of the two DFFs; and the delay driving unit drives the DFF connected with the delay driving unit to delay when the UP signal and the DOWN signal are both high. In this way, the input-output curve is shifted down (or up) so that the phase detector operates in the linear region when the PLL is in lock. In this way, in-band phase noise and spurs of the PLL can be improved. Preferably, the delay difference of the two DFFs is greater than a minimum value. This minimum is chosen so that the PLL operates in the linear region under any circumstances of the application.
Further, the phase detector further comprises two delay driving units which are respectively connected with the two DFFs; and when the UP signal and the DOWN signal are both high, the delay driving unit respectively drives the DFF connected with the delay driving unit to delay, and the two delays are different in time.
Further, the frequency tuning gains of at least two of the voltage controlled oscillators are equal.
Further, the voltage controlled oscillator comprises a CMOS LC oscillator.
Further, the frequency divider is also included; the phase discriminator and the voltage-controlled oscillation unit are electrically connected through the frequency divider; the input end of the frequency divider is electrically connected with the output end of the voltage-controlled oscillation unit, and the first output end of the frequency divider is electrically connected with the first input end of the phase discriminator; the frequency divider is used for dividing frequency according to the frequency output by the voltage-controlled oscillation unit.
Further, the system also comprises a loop filter; the charge pump is electrically connected with the voltage-controlled oscillation unit through the loop filter; the input end of the loop filter is electrically connected with the output end of the charge pump, and the output end of the loop filter is electrically connected with the input end of the voltage-controlled oscillation unit; the loop filter is used for filtering the signal output by the charge pump. The loop filter comprises a plurality of first resistors connected in series, a plurality of second resistors connected in series, a first capacitor, a plurality of second capacitors connected in parallel, a plurality of third capacitors connected in parallel and a plurality of switches; the switch is respectively connected with the plurality of first resistors and the plurality of second resistors in parallel and respectively connected with the plurality of second capacitors and the plurality of third capacitors in series; the first end of the first capacitor is electrically connected with the first end of the first resistor in series and the first end of the second resistor in series and serves as the input end of the loop filter, the second end of the first resistor in series is electrically connected with the first end of the second capacitor, and the second end of the second resistor in series is electrically connected with the first end of the third capacitor and serves as the output end of the loop filter.
Further, the device also comprises a frequency pre-adjusting unit; a first input end of the frequency pre-adjusting unit is electrically connected with a second output end of the frequency divider, a second input end of the frequency pre-adjusting unit is electrically connected with a preset frequency input end, and an output end of the frequency pre-adjusting unit is electrically connected with a pre-adjusting input end of the voltage-controlled oscillator; the frequency pre-adjusting unit is used for adjusting the frequency of the voltage-controlled oscillator by adopting a dichotomy. Specifically, when the output frequency of the voltage-controlled oscillator in the voltage-controlled oscillation unit is adjusted, it may be coarsely adjusted by the frequency pre-adjustment unit. Before the charge pump provides the voltage-controlled oscillator with the output frequency of the voltage-controlled oscillator, the frequency pre-adjusting unit performs coarse adjustment on the output frequency of the voltage-controlled oscillator. When the output frequency of the voltage-controlled oscillator is coarsely regulated, a path between the input end of the voltage-controlled oscillator and the reference signal is disconnected. At this time, the second output end of the frequency divider outputs the frequency divided by the voltage-controlled oscillator and outputs the frequency to the counter of the frequency pre-adjusting unit, the counter counts the frequency divided by the voltage-controlled oscillator according to the period of the reference signal and compares the frequency with the number of the frequencies input by the preset frequency input end through the comparator, and the comparator outputs according to the comparison result and controls the capacitor array of the voltage-controlled oscillator, so that the coarse adjustment of the output frequency of the voltage-controlled oscillator is realized. In the adjusting process, the output frequency of the voltage-controlled oscillator is adjusted by adopting a dichotomy, so that the coarse adjusting time of the output frequency of the voltage-controlled oscillator can be reduced, and the efficiency of the frequency synthesizer is improved.
According to the invention, the voltage-controlled oscillation unit is arranged in the frequency synthesizer, when the frequency synthesizer works, one voltage-controlled oscillator can be selected to work according to the tuning frequency of the frequency synthesizer, so that the frequency tuning range of the voltage-controlled oscillation unit is increased on the basis of not increasing the tuning gain of the voltage-controlled oscillator, the frequency tuning range of the frequency synthesizer is increased on the basis of not reducing the noise performance of the frequency synthesizer, and the use range of the frequency synthesizer is increased. In addition, the tuning gain of the voltage-controlled oscillator is smaller, so that a capacitor array in the voltage-controlled oscillator is smaller, and the parasitic resistance of the voltage-controlled oscillator is smaller, so that the power consumption of the voltage-controlled oscillator can be reduced, and the power consumption of the frequency synthesizer is further reduced. While DFF1 and DFF2 experience different delays being reset when both the UP and DOWN signals are high. In this way, the input-output curve is shifted down (or up) so that the phase detector operates in the linear region when the PLL is in lock. Thus, the present invention can improve the in-band phase noise and spurs of the PLL.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (8)
1. A frequency synthesizer is characterized by comprising a phase discriminator, a charge pump, a voltage-controlled oscillation unit, a frequency divider, an automatic frequency controller, a voltage comparison circuit, a relock control circuit and a frequency stability detection circuit; the first input end of the phase discriminator is electrically connected with the output end of the voltage-controlled oscillation unit, the second input end of the phase discriminator is electrically connected with the reference frequency input end, the output end of the phase discriminator is electrically connected with the input end of the charge pump, and the output end of the charge pump is electrically connected with the input end of the voltage-controlled oscillation unit; the phase discriminator is used for comparing the phases of the reference clock and the feedback clock of the voltage-controlled oscillator; when the phase of the feedback clock lags behind the phase of the reference clock, the phase discriminator outputs a pulse signal UP signal for increasing the frequency;
the automatic frequency controller comprises a counter, a timing circuit, a comparator and a logic control circuit, wherein the input end of the counter is connected with the other output end of the frequency divider, the input end of the timing circuit is connected with a reference signal, the output end of the timing circuit is connected with the counter and provides a periodic signal for the counter, the output end of the counter is connected with the input end of the comparator, the output end of the comparator is connected with the input end of the logic control circuit, and the output end of the logic control circuit outputs a control signal for controlling a switch capacitor array control word of the voltage-controlled oscillator when the phase-locked loop frequency synthesizer is in an open-loop frequency coarse adjustment stage so as to adjust the output frequency of the voltage-controlled oscillator;
the voltage comparison circuit judges whether the tuning voltage Vtune output to the voltage-controlled oscillator by the low-pass loop filter is in a preset voltage range in real time when the frequency synthesizer is in the phase of phase-locked loop loss detection, and the relock control circuit dynamically adjusts the value of a control word of a switch capacitor array of the voltage-controlled oscillator according to the comparison result of the voltage comparison circuit; when the tuning voltage Vtune is within a preset voltage range, the relocking control circuit does not work, when the tuning voltage Vtune is larger than the preset voltage range, the relocking control circuit controls the value of the switch capacitor array control word of the voltage-controlled oscillator to increase or decrease by one unit, and when the tuning voltage Vtune is smaller than the preset voltage range, the relocking control circuit controls the value of the switch capacitor array control word of the voltage-controlled oscillator to decrease or increase by one unit;
the frequency stability detection circuit is used for detecting whether the frequency of a reference signal and the frequency of a feedback signal of the voltage-controlled oscillator after frequency division by the frequency divider are stable or not before the frequency synthesizer enters an open-loop coarse adjustment stage, and sending a control signal after the frequency of the reference signal and the frequency of the feedback signal are both stable, so that the phase-locked loop frequency synthesizer starts a coarse tuning loop and enters the open-loop coarse adjustment stage, wherein the voltage-controlled oscillator is provided with a fixed control voltage in the process from starting to entering the open-loop coarse adjustment stage.
2. The frequency synthesizer of claim 1, wherein the phase detector comprises two resettable DFFs; when the UP signal and the DOWN signal are both high, at least one of the two DFFs is delayed, so that the two DFFs are reset; when the PLL is in lock, the phase detector operates in the linear region.
3. The frequency synthesizer of claim 2, wherein the phase detector comprises at least one delay drive unit connected to one of the two DFFs; and the delay driving unit drives the DFF connected with the delay driving unit to delay when the UP signal and the DOWN signal are both high.
4. The frequency synthesizer of claim 1, wherein the frequency tuning gains of at least two of the voltage controlled oscillators are equal.
5. The frequency synthesizer of claim 1, wherein the voltage controlled oscillator comprises a CMOS LC oscillator.
6. The frequency synthesizer of claim 1, further comprising a frequency divider; the phase discriminator and the voltage-controlled oscillation unit are electrically connected through the frequency divider; the input end of the frequency divider is electrically connected with the output end of the voltage-controlled oscillation unit, and the first output end of the frequency divider is electrically connected with the first input end of the phase discriminator; the frequency divider is used for dividing frequency according to the frequency output by the voltage-controlled oscillation unit.
7. The frequency synthesizer of claim 1, further comprising a loop filter; the charge pump is electrically connected with the voltage-controlled oscillation unit through the loop filter; the input end of the loop filter is electrically connected with the output end of the charge pump, and the output end of the loop filter is electrically connected with the input end of the voltage-controlled oscillation unit; the loop filter is used for filtering the signal output by the charge pump.
8. The frequency synthesizer of claim 1, further comprising a frequency preconditioning unit; a first input end of the frequency pre-adjusting unit is electrically connected with a second output end of the frequency divider, a second input end of the frequency pre-adjusting unit is electrically connected with a preset frequency input end, and an output end of the frequency pre-adjusting unit is electrically connected with a pre-adjusting input end of the voltage-controlled oscillator; the frequency pre-adjusting unit is used for adjusting the frequency of the voltage-controlled oscillator by adopting a dichotomy.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110537821.9A CN113225076A (en) | 2021-05-18 | 2021-05-18 | Frequency synthesizer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110537821.9A CN113225076A (en) | 2021-05-18 | 2021-05-18 | Frequency synthesizer |
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| CN113225076A true CN113225076A (en) | 2021-08-06 |
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| CN202110537821.9A Withdrawn CN113225076A (en) | 2021-05-18 | 2021-05-18 | Frequency synthesizer |
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